JP3114861B2 - Adaptive receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an adaptive receiver having an adaptive matched filter, and more particularly to an adaptive receiver capable of removing the fluctuation when receiving data having fluctuation due to satellite communication or the like.

[0002]

2. Description of the Related Art Conventionally, as an adaptive receiver designed to remove fluctuations in received data, an adaptive receiver which employs an adaptive matched filter and uses a Doppler buffer at the output side to remove the fluctuations has been implemented. I have. FIG. 3 is a diagram showing a circuit configuration of a conventional adaptive receiver in which received data is synchronized with a reference clock as a reference clock using such a Doppler buffer.

[0003] In FIG. 3, an adaptive matched filter (hereinafter, referred to as "AMF") 301 receives a received signal as an input, and performs timing control or the like to converge a signal dispersed on a time axis to a phase of a reference determination data signal. It performs frequency / phase control, and when diversity is configured, the signal-to-noise power ratio (S / N
Ratio) for maximizing the ratio, and outputting the result.

[0004] A decision feedback equalizer (hereinafter referred to as "DFE") 302 receives an output signal of the AMF 301 as an input,
The signal is output after intersymbol interference due to a leading wave or a lagging wave generated in the propagation path is removed.

[0005] The determiner 303 receives the analog output signal of the DFE 302 as an input, shapes it into a digital signal, and outputs the digital signal.
The Doppler buffer 304 receives the digital signal and temporarily stores the digital signal in a memory. The stored data is output in synchronization with the reference clock.

Next, the clock extraction circuit 305
A signal obtained by branching the output of 302 is input and a clock component is extracted and transmitted. The phase comparator 306 receives the signal of the clock component as an input and outputs a voltage-controlled oscillation circuit VC described later.
The phase correlation with the output signal of O308 is determined, and the information is output. The loop filter 307 is basically a low-pass filter (LPF), and outputs only information of a low-frequency phase difference. The VCO 308 receives this information and outputs a signal of an appropriate frequency. This clock is sent to the phase comparator and used as a comparison target with the clock component.

The phase comparator 306, loop filter 307, and VCO 308 after the clock extraction circuit 305
An LL circuit is formed, and an output signal of the VCO 308 serves as a master clock of a receiving system. Clock extraction circuit 30
5 are referred to as “CLK SYNC” circuits.

Next, the operation of the conventional adaptive receiver shown in FIG. 3 will be described.

FIG. 4 is a diagram showing an example of the configuration of the AMF 301. 4, reference numerals 401a and 401b denote delay elements having a delay time τ, reference numerals 402a to 402c denote correlators, and reference numerals 403a to 403.
3c is a complex multiplier, and 404 is a combiner.

Now, received signals a ₀ · h ₊₁ , a ₀ · h ₀ , a ₀ · h _-1 having an impulse response as shown in FIG.
Is input to the AMF 301. Here, a ₀ indicates a data sequence at time 0, h ₊₁ , h ₀ , and h _-1 are impulse responses, respectively, where h ₀ is a main wave at time 0, and h _-1 is τ with respect to h _0.
H ₊₁ indicates a wave delayed by τ with _respect to h ₀ .

Therefore, at the time τ, on the AMF 301, the point A in FIG. 4 receives a ₀ · h ₊₁ , the point B receives a ₀ · h ₀ with a delay of τ, and the point C receives a delay of 2τ and a ₀ · h ₋₁ is distributed.

These are correlated by the correlator 402a to 402c in the route of each circuit with the decision data signal a _R which is the output signal of the decision unit 303. Here, assuming that the determination data signal a _R has a symmetrical impulse response such as a solid line 205 shown in FIG. 2, a tap coefficient (hereinafter, referred to as “tap weight”) that is an output of each correlator. Is that 402a is h _{+ 1} ^* , 4
02b is h ₀ ^* , and 402c is h _-1 ^* . Here, "*" (asterisk) on the right shoulder indicates that it is a complex conjugate. These outputs are output from complex multipliers 403a to 403c.
Is multiplied by the signal for each route. That is, the multiplication results in the complex multipliers 403a, 403b, and 403c are as follows.

[0013] _{403a: a 0 · h +1 ×} h +1 * = a 0 · h +1 2 403b: a 0 · h 0 × h 0 * = a 0 · h 0 2 403c: a 0 · h -1 ^{_{× h -1 * = a 0 ·}} h -1 h +1 2 in ² above equation, h ₀ ^2, h _-1 ² is for showing the squared value of the amplitude of each impulse response, real values is there. These are combined in a subsequent synthesizer 404, the ^{_{a 0 · (h +1 2 +}} h 0 2 + h -1 2). Wherein ^{_{h +1 2 + h 0 2 +}} h -1 2 , the signal energy which has been dispersed in ± tau time (the amplitude of the impulse response), represents that it is focused at time 0 is the center of the root The phase and frequency match those of the decision data signal having symmetrical impulse response characteristics described above. This is apparent from the correlation with the decision data signal.

The above is the main operation of the AMF 301. A
The timing control, which is one of the functions of the MF, utilizes this.

The DFE 302 takes in the output of the AMF 301 whose timing matches the decision data signal and removes the intersymbol interference.

The output of the AMF 301 is subjected to signal enhancement and S / N ratio maximization by converging to a center tap (route B in FIG. 4). Impulse responses located at integer multiples of T, such as = ± T, ± 2T, are not zero. This means that the distortion-free condition is not satisfied, and there is intersymbol interference. In the DFE 302, a forward equalizer (FE) which is a component thereof removes a leading wave component of -T or -2T existing at the same time as the main wave of the AMF output, and a backward equalizer (BE) removes + T or -T. A + 2T delayed wave component is removed.
As described above, by setting the response located at an integer multiple of T to 0, a received signal that satisfies the distortion-free condition and has no intersymbol interference is obtained.

The decision unit 303 receives the output signal of the DFE 302 as an input, amplifies the signal level until the signal is sufficiently saturated, and shapes and outputs the data signal with a steep slope. That is, a digital waveform is created from the analog waveform. This output signal becomes a demodulated data signal, and this signal is fed back to the AMF 301 to serve as a reference signal (determination data signal) for the AMF 301.

The Doppler buffer 304 receives the output signal of the determiner 303 as an input, performs storage and readout operations on the determination data signal with a stable reference clock, removes the remaining fluctuation of the determination data signal, and outputs the result. .

Next, the operation of the clock system will be described. The clock extraction circuit 305 receives the output signal of the DFE 302 as an input and squares this. The following is a description of the equation using an example.

If the output waveform pattern of the DFE 302 is a sine waveform with a period of 2T, the signal y can be expressed as y = sin (2π / 2T) t. When this is squared, y ² = (１ ／) {1−cos (2π / T) t}, and the period becomes the same as the clock period T.

As described above, when the signal is squared and its time change is averaged, a sine wave component having a period T, that is, a clock component can be extracted. Phase comparator 306
Receives the output signal of the clock extraction circuit 305 as an input, and receives the signal oscillated by the VCO 308 as an input to detect a phase difference between the two signals. The loop filter 307 outputs only the phase difference component. This output signal is an error voltage proportional to the phase difference, and is fed back to the VCO 308 to control the clock phase. The clock obtained as described above is used as a reference clock in the demodulation processing.

[0022]

The above-mentioned adaptive receiver uses an adaptive matched filter so that the received data signal dispersed on the time axis coincides with the phase of a decision data signal serving as a reference signal. It has a timing control or phase control function that can converge and suppress fluctuations in received data.

However, in the conventional adaptive receiver, with respect to the fluctuation of the received data caused by the Doppler of the satellite in the satellite communication, a considerable amount of fluctuation remains in the clock extracted and generated from the received data. Therefore, the determination data signal also fluctuates, and in order to prevent this, a Doppler buffer is provided and the timing is reset by a stable reference clock. However, in such a configuration, the provision of the Doppler buffer not only reduces the reliability of data but also increases the circuit scale and increases the cost.

(Object of the Invention) It is an object of the present invention to provide an adaptive receiver capable of eliminating fluctuations in received data without using a large-scale circuit.

[0025]

In order to achieve the above object, the present invention focuses on the timing control function of the AMF and synchronizes a reference signal to be fed back to the AMF with a reference clock having no fluctuation in advance. Means for removing the fluctuation component of the demodulated data without using a buffer is provided. Means for supplying a reference clock to the phase comparator (105 in FIG. 1) instead of the output of the voltage controlled oscillator VCO, and flip-flops the output signal of the decision unit (103 in FIG. 1) that feeds back to the AMF (101 in FIG. 1). The clock circuit (108 in FIG. 1) has means for adjusting the timing with the clock of the VCO (107 in FIG. 1) output.

More specifically, the adaptive receiver of the present invention comprises:
An adaptive matched filter that receives received data, a determiner that outputs a determination data signal from an output of the adaptive matched filter, a reference clock, and a phase of the clock signal component of the output of the adaptive matched filter and the reference clock. A phase comparator to be compared, a voltage controlled oscillator controlled by a phase difference component from the phase comparator, and the determination data signal synchronized with an output phase of the voltage controlled oscillator and output as a reference signal of the adaptive matched filter. Timing means.

The adaptive receiver includes a decision feedback equalizer between the adaptive matched filter and the decision unit. Further, the output of the voltage control transmitter is used as a master clock of a receiving system. The timing means has a flip-flop for latching a decision data signal according to an output of a voltage controlled oscillator.

[0028]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit configuration of an embodiment of the present invention.

The characteristic configuration of FIG. 1 is that, instead of directly using the decision data signal output from the decision unit 103 as a reference signal of the AMF 101, the decision data signal is applied to a voltage controlled oscillator VCO10 in a flip-flop F / F 108.
7, the output frequency and the phase of the VCO 107 are obtained by comparing the phase of the clock signal component extracted by the clock extraction circuit 104 with the phase of the reference clock in the phase comparator 105. The configuration is controlled by the phase error signal output from the filter 106.

In the present embodiment, the AMF 101
Received data is input, timing control and frequency / phase control are performed by a reference signal (output signal of F / F), and output. The DFE 102 receives the signal and removes a leading wave and a delayed wave component existing in the signal and outputs the signal. The determiner 103 receives the output signal of the DFE 102 as an input, amplifies the signal until the signal is sufficiently saturated, converts an analog signal into a digital signal, and outputs the digital signal.

On the other hand, the clock extraction circuit 104
The output signal branched from 102 is input, and a clock component is extracted from the input signal and output. Phase comparator 10
Reference numeral 5 receives the output of the clock extraction circuit 104, compares the phase with the reference clock, determines the correlation, and outputs the result. The loop filter 106 receives the output signal as an input, passes only an error component, and outputs the error signal. VCO 107
Upon receiving the output signal, a clock signal having a frequency and a phase corresponding to the error voltage is output. This output becomes the standard clock signal of the receiving circuit.

A flip-flop (F / F) 108
For example, using a D-type flip-flop, the clock signal and the determination data signal from the determination unit 103 are input,
Synchronizing the determination data signal with the clock signal, A
Send to MF101. The AMF 101 performs the above-described various controls based on the output signal.

Next, the operation of this embodiment shown in FIG. 1 will be described.

AMF 101, DFE 102, decision unit 10
3. The main operation of the clock extraction circuit 104 is the same as that of the prior art. However, in the present embodiment, the clock signal extracted from the output of the DFE 102 by the clock A stable reference clock is used as an input to the phase comparator 105, a phase comparison output is generated from the phase comparator 105, and the phase error component is output from the loop filter 106 to generate a VC.
It is configured to control the output phase of O107. According to this configuration, the fluctuation-free decision data signal synchronized with the reference clock is fed back to the AMF 101, the clock timing on the output side of the AMF 101 is stabilized, and the fluctuation-free decision data signal is output from the decision unit 103. PLL operation can be realized.

The operation of the present embodiment, which can be regarded as constituting a PLL circuit using the timing control and phase / frequency control functions of the AMF 101 and using a reference clock, will be described below.

FIG. 2 is a diagram for explaining the operation of the AMF. The input impulse response and its change, and the change of the tap weight of the AMF caused by the correlation operation between the input impulse response and a reference signal (judgment data signal) are shown. FIG.

In FIG. 2, reference numerals 201a to 201c denote tap weights of respective routes, reference numerals 202a to 202b denote delay elements having a delay amount T / 2, reference numerals 203a to 203c denote complex multipliers, reference numeral 204 denotes a combiner, and reference numeral 205 denotes an input impulse. response,
206 is the output waveform of the DFE 102, 207 is the AMF10
1 shows a clock synchronized with the determination data signal that has returned to 1.

Reference numerals 201a to 201c denote correlation values between the signals of the respective routes and the feedback decision data signals. The larger the value, the higher the correlation. Actually, the correlation value is represented as a complex number including phase information, but here, the phase is ignored for simplicity.

Here, the impulse response of the received data is
Fluctuation occurs in the delay direction as indicated by the broken line curve of the impulse response 205 in FIG.
Let us consider a case where the state does not match the center tap 201b.

At this time, the AMF 101 calculates the tap coefficient W
By changing _-1 , W ₀ , and W ₊₁ , an attempt is made to make the main response of the impulse response at the output coincide with the center tap (reference timing). That is, the impulse response of the received data is shifted in the direction in which the impulse response is delayed as indicated by the dotted line of the impulse response 205 in FIG. The specific gravity of the tap weight of the complex multiplier 203a on the side is increased. This is the complex multiplier 203a
This is because the correlation with the determination data signal is higher in the case of 203c than in the case of 203c. Those drawn by broken lines 201a to 201c are tap weight values indicating the correlation at that time. If the main response matched the center tap, ie 20
Unlike the solid lines 1a to 201c, the balance between the magnitudes of the impulse responses of 201a and 201c is broken, and 201a is larger and 201c is smaller.

For this reason, the impulse response of the AMF 101 shifts its center to the side 203a, and changes its characteristic in a direction to reduce the amount of delay in the AMF 101 with respect to fluctuation in the delay direction of received data. Such AMF10
The operation of No. 1 is the same also in the case of fluctuation in the advancing direction of the received data. In this case, the AMF 101 changes the characteristic so as to increase the amount of delay in reverse.

Considering a case where the influence of the fluctuation of the received data signal remains at the outputs of the AMF 101 and the DFE 102, the fluctuation affects the clock itself extracted by the clock extracting circuit 104 and the phase Appears as fluctuations. This phase change is caused by the phase comparator 1
05 is output as an error signal due to the phase difference from the reference clock as a reference, and the phase error signal is supplied to the voltage controlled oscillator
7 to change its output frequency and phase.

The flip-flop 108 is connected to the VCO 107
The latch operation of the decision data signal from the decision unit 103 is performed by the output of the VCO 107, so that the reference signal (decision data signal) whose phase is controlled by the output of the VCO 107 is output. The output of the flip-flop 108 becomes a reference signal (judgment data signal) for the correlation operation in the AMF 101,
The phase change operates in a direction to suppress the phase fluctuation of the output of the AMF 101.

As a result, the phase of the output data or clock component of the AMF 101 is locked to the phase and frequency of the reference clock. Then, in this large PLL circuit, an effect of suppressing fluctuations in proportion to the reciprocal of the loop gain can be obtained. Therefore, the fluctuation of the output of the AMF 101, that is, the output of the determiner 103 is always suppressed with high accuracy.

Reference numerals 206 and 207 shown in FIG. 2 show the output waveform of the DFE 102 and the output waveform of the reference clock, respectively. As can be seen from both waveforms, even if the received data fluctuates, the phase of the waveform 206 matches the output waveform 207 of the reference clock,
From No. 3, a determination data signal without fluctuation is obtained.

Here, the waveform of 206 will be described. The symbol 206 is a symbol sequence in which "0" and "1" are arranged in various orders, which are superimposed on the display surface of the oscilloscope. Focusing on the curve, it is called an eye pattern from its shape. The maximum distance of the curve is referred to as the opening degree, and “0”, “1” at the timing when the opening degree becomes maximum.
Is determined, the probability of erroneous signal is minimized. Therefore, it is very important to match this timing.

As described above, according to the phase locked circuit configuration using the AMF of the present invention, the timing control function of the AMF that the received data becomes the same as the determination data signal is used, and the reference signal supplied to the AMF is further supplied. Is fixed by a stable reference clock.

The reason why the delay amount of the delay element is T / 2 is to make it possible to control the timing by making the delay amount of the delay element smaller than T.

[0049]

According to the present invention, the timing of the output side of the AMF is stabilized by positively utilizing the timing control function of the AMF. There is no need to use peripheral circuits.

Therefore, the size of the adaptive receiver can be reduced,
It is possible to reduce costs.

Further, since it is not necessary to output the received data through the Doppler buffer, data errors due to data slip and the influence of the temperature of the semiconductor circuit can be eliminated, and the output data signal of the adaptive receiver can be eliminated. It is possible to improve reliability.

[0052]

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating the operation of AMF timing control.

FIG. 3 is a diagram illustrating an example of a conventional circuit for removing clock fluctuation.

FIG. 4 is a diagram showing an example of an AMF circuit when the number of taps is three.

FIG. 5 is a diagram showing an input impulse response of the AMF.

[Explanation of symbols]

 101, 301 Adaptive Matched Filter (AMF) 102, 302 Decision Feedback Equalizer (DFE) 103, 303 Judge 104, 305 Clock Extraction Circuit 105, 306 Phase Comparator 106, 307 Loop Filter 107, 308 Voltage Controlled Oscillator (VCO) 108 Flip-flops 201a to 201c Tap weight size 202a, 202b, 401a, 401b Delay element 203a to 203c 403a to 403c Complex multiplier 204, 404 Synthesizer 205 Impulse response 206 Output waveform (eye pattern) 207 Reference clock 304 Doppler buffer 402a-402c correlator

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04B ⁷ /00-7/015 H04B 1/10

Claims (4)

(57) [Claims] 1. An adaptive matched filter to which received data is input, a decision unit that outputs a decision data signal from an output of the adaptive matched filter, a reference clock, a clock signal component of an output of the adaptive matched filter, and the reference A phase comparator for comparing the phase with a clock, a voltage-controlled oscillator controlled by a phase difference component from the phase comparator, and synchronizing the decision data signal with an output phase of the voltage-controlled oscillator to adjust the adaptive matched filter. Timing means for outputting as a reference signal. 2. The adaptive receiver according to claim 1, further comprising a decision feedback equalizer provided between said adaptive matched filter and said decision unit. 3. An output of the voltage controlled oscillator is used as a master clock of a receiving system.
The adaptive receiver described. 4. The apparatus according to claim 1, wherein said timing means includes a flip-flop for latching said determination data signal in response to an output of a voltage controlled oscillator.
The adaptive receiver described.