JP2009081722A - Adaptive receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an adaptive receiver capable of maintaining stable clock generation and timing control function, even when code-code interference is produced due to multi-path fading. <P>SOLUTION: Since a clock synchronizing circuit is arranged on the post stage of a decising feedback type equalizer, the effect off code-code interference is suppressed to a minimum in CLK extraction. Furthermore, as a phase shifter is provided at an output part of a complex multiplier of an adaptive matching filter, the phase of signal can be matched with the phase of decision data signal to ensure ideal synthesis which is less apt to be affected by clock. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an adaptive receiver, and more particularly to an adaptive receiver having a diversity configuration.

  An adaptive receiver including an adaptive matched filter (AMF: Adaptive Matched Filter) and a decision feedback equalizer (DFE) is used to perform high-quality communication in a propagation path with severe multipath fading. It has been.

In relation to such an adaptive receiver, Patent Document 1 (Japanese Patent Laid-Open No. 6-232774) discloses an invention relating to a demodulation system.
The demodulation system of the invention of Patent Document 1 includes a demodulator, an analog / digital converter, an adaptive matched filter, a decision feedback equalizer, and a reset circuit. Here, the demodulator demodulates the modulation signal in the intermediate frequency band having intersymbol interference due to propagation path fading or the like into an analog baseband signal. The analog-to-digital converter samples and quantizes the analog baseband signal and outputs a digital baseband signal. The adaptive matched filter receives the digital baseband signal, symmetrizes the asymmetric impulse response of the propagation path in the digital baseband signal, and outputs a matched signal. The decision feedback equalizer receives the matched signal, removes intersymbol interference of the matched signal, and outputs an equalized signal. Based on the tap coefficient of the decision feedback equalizer, the reset circuit taps the adaptive matched filter in the case of fading starting from 0 <ρ <1 (ρ is the amplitude ratio of the delayed wave to the main wave). The coefficient is fixed to a predetermined value.

  FIG. 1 is an example of a configuration diagram of an adaptive receiver according to a technique related to the present invention. The adaptive receiver in FIG. 1 includes a mixer 300, a local frequency oscillator 301 (LO: LOcal), an analog / digital conversion circuit 310 (A / D: Analog / digital converter), and a voltage controlled crystal oscillator 311 (VCXO: Voltage). Controlled CRYStal Oscillator), demodulator circuit 320 (DEM: DEModulator), adaptive matched filter 330 (AMF), synthesizer 340, decision feedback equalizer 350 (DFE), and determiner 360 Yes.

  Here, the mixer 300 demodulates the input signal R in the intermediate frequency band into a baseband signal. The analog / digital conversion circuit 310 converts an analog baseband signal into digital. The voltage controlled crystal oscillator 311 transmits a clock signal corresponding to the voltage supplied from the demodulation circuit 320 and outputs the clock signal to the analog / digital conversion circuit 310. The demodulation circuit 320 includes a carrier wave (CARR: CARRier) synchronization circuit 321 and a clock recovery circuit. The carrier synchronization circuit 321 removes the remaining carrier phase difference. The adaptive matched filter 330 performs impulse response symmetry, phase control, and timing control. The combiner 340 performs diversity combining. The decision feedback equalizer 350 removes intersymbol interference. The determiner 360 determines a code.

  In addition, although the adaptive receiver in FIG. 1 has a double diversity configuration, this is merely an example.

  Here, the connection relationship between the components of the adaptive receiver in FIG. 1 will be described. The mixer 300 is connected to the outside to which the input signal R is input, the local frequency oscillator 301, and the analog / digital conversion circuit 310. The analog / digital conversion circuit 310 is further connected to a voltage controlled crystal oscillator 311 and a demodulation circuit 320. The demodulator circuit 320 is further connected to a voltage controlled crystal oscillator 311, an adaptive matched filter 330, and a decision feedback equalizer 350. The adaptive matched filter 330 is further connected to a diversity combiner 340 and a sign determiner 360. Diversity combiner 340 is further connected to another adaptive matched filter 330 that constitutes diversity, and decision feedback equalizer 350. The decision feedback equalizer 350 is further connected to a plurality of demodulation circuits 320 that constitute diversity and a code decision unit 360. The code determination unit 360 is further connected to the outside which outputs the determination data signal S.

  Here, the configuration of the demodulation circuit 320 will be described. The demodulation circuit 320 includes a carrier synchronization circuit 321, a clock extraction circuit 322, a phase comparator 323, a loop filter (LPF: LoopP Filter) 324, and a digital / analog conversion circuit (D / A: Digital / Analog converter) 325. It is equipped with.

  The carrier wave synchronization circuit 321 is connected to the analog / digital conversion circuit 310, the clock extraction circuit 322, the adaptive matched filter 330, and the decision feedback equalizer 350. The clock extraction circuit 322 is further connected to the phase comparator 323. The phase comparator 323 is further connected to the analog / digital conversion circuit 310 and the loop filter 324. The loop filter 324 is further connected to a digital / analog conversion circuit 325. The digital / analog conversion circuit 325 is further connected to a voltage controlled crystal oscillator 311.

  Here, the configuration of the adaptive matched filter 330 will be described. Adaptive matched filter 330 includes delay elements 331a-b, complex multipliers 332a-c, combiner 333 (Σ), delay element 334, delay elements 335a-b, and correlators 336a-c. ing.

  The complex multiplier 332a is connected to the carrier wave synchronization circuit 321, the clock extraction circuit 322, the delay element 331a, the combiner 333, the delay element 334, and the correlator 336a. The delay element 331a is further connected to a carrier wave synchronization circuit 321, a clock extraction circuit 322, a complex multiplier 332b, a delay element 331b, and a delay element 334. The complex multiplier 332b is further connected to a delay element 331b, a correlator 336b, and a combiner 333. The delay element 331b is further connected to a complex multiplier 332c. The complex multiplier 332 c is further connected to a correlator 336 c and a combiner 333. The combiner 333 is further connected to the diversity combiner 340. The delay element 334 is further connected to the delay element 335a and the correlator 336a. The correlator 336a is further connected to a code determiner 360. The delay element 335a is further connected to the delay element 335b and the correlator 336b. The correlator 336b is further connected to a sign determination unit 360. The delay element 335b is further connected to a correlator 336c. The correlator 336c is further connected to a code determination unit 360.

  Here, the operation of the adaptive receiver in FIG. 1 will be described. The adaptive receiver in FIG. 1 has a quasi-synchronous detection scheme. In the quasi-synchronous detection method, carrier synchronization is achieved by the carrier synchronization circuit 321 at the subsequent stage. Therefore, the local frequency oscillator 301 does not require strict accuracy. Furthermore, since a part of the circuit is digitized, no adjustment is required.

  The reception signal R in the intermediate frequency band is input to the mixer 300, mixed with the local signal output from the local frequency oscillator 301, and then output. The output signal from the mixer 300 is a baseband signal. As described above, since the local frequency of the input signal R and the local frequency of the receiver are not synchronized, phase rotation still remains. Since the carrier wave synchronization circuit 321 for removing the phase rotation is digital processing, digital conversion processing is performed on the output signal of the mixer 300 before that. The output signal of the mixer 300 is input to the A / D conversion circuit 310, and after digital conversion, is output. The clock for digital conversion is supplied from a voltage controlled crystal oscillator 311. This clock is frequency-divided to the same frequency as the data signal in the A / D conversion circuit 310 and then output together with the data. The output clock is used as the master clock for the adaptive receiver. The voltage controlled crystal oscillator 311 receives a signal output from the clock recovery circuit in the demodulation circuit 320 and converted into an analog signal as a control signal, and outputs a signal having a predetermined frequency.

  The signal output from the A / D conversion circuit 310 is input to the demodulation circuit 320. In the demodulation circuit 320, the carrier synchronization circuit 321 includes an output signal from the A / D conversion circuit 310 and a signal output from the decision feedback equalizer 350 (CARR PD: CARRier Phase Difference, carrier phase difference in FIG. 1). As inputs. The carrier synchronization circuit 321 then synchronizes the carrier by rotating the phase of the received signal R according to the carrier phase difference signal, and outputs the demodulated signal.

  The output signal of the carrier wave synchronization circuit 321 is output as the output signal of the demodulation circuit 320, while being branched and input to the clock extraction circuit 322. The clock extraction circuit 322 receives the output signal of the carrier wave synchronization circuit 321 as an input, extracts a clock component, and outputs it. The phase comparator 323 receives the output of the clock extraction circuit 322 and the output clock of the A / D conversion circuit 310 as inputs. The phase comparator 323 compares both signals and outputs phase difference information after comparing these phases. The loop filter 324 receives the output signal from the phase comparator 323, integrates it, suppresses noise, and outputs it. The digital / analog conversion circuit 325 receives the output signal of the LPF 324 as an input, converts it into an analog signal, and outputs it. The output signal of the digital / analog conversion circuit 325 is input to the voltage controlled crystal oscillator 311 as described above. Since the voltage control crystal oscillator 311 performs analog control and the loop filter 324 performs a digital circuit, a D / A conversion circuit 325 is required.

  The output signal of the carrier wave synchronization circuit 321 is input to the adaptive matched filter 330. The adaptive matched filter 330 is a transversal filter including a multiplier unit, a delay element 334, and a correlator unit. Here, the multiplier unit includes delay elements 331a to 331b, complex multipliers 332a to 332c, and a combiner 333. The correlator section includes delay elements 335a to 335b and correlators 336a to 336c.

  The signal input to the adaptive matched filter 330 from the carrier synchronization circuit 321 is distributed to the multiplier unit and the correlator unit at point P in FIG. In the multiplier section, the delay elements 331a and 331b are delay elements having a delay time of T / 2, and are connected in series. Here, T represents the symbol period of the signal input to the multiplier section.

  The delay element 331a receives the signal output from the carrier wave synchronization circuit 321 and outputs it with a delay time of T / 2. The delay element 331b receives the signal output from the delay element 331a as input, and further outputs a delay time of T / 2. That is, at a certain time, there are three types: a signal with a delay time of 0, a signal before time T / 2 based on the signal, and a signal before time T.

  The complex multiplier 332a receives an input signal of the adaptive matched filter 330 (= a signal having a delay time of 0). The complex multiplier 332b receives the output signal of the delay element 331a (= the signal before time T / 2). The complex multiplier 332c receives the output signal of the delay element 331b (= signal before time T). Each of the complex multipliers 332a to 332c multiplies the input signals by the tap coefficients Wa to c and outputs the result.

  The combiner 333 receives the signals output from the complex multipliers 332a to 332c, inputs them, and outputs the combined signals. The signal output from the combiner 333 is the output signal of the adaptive matched filter 330.

  On the other hand, the delay element 334 receives the signal branched at the point P in FIG. 1, gives a delay time τ, and outputs it to the correlator unit. Here, the delay time τ is a time difference provided for the same symbol signal that is input to the adaptive matched filter 330 and branched at the point P in FIG. 1 to be simultaneously input to the correlator unit from two directions. . In one of the two directions, the signal branched at point P in FIG. 1 is input to the correlator section as it is through the delay element 334. In the other of the two directions, the signal branched at a point P in FIG. 1 is converted into a determination data signal S through a multiplier unit and others and input to the correlator unit.

  As an example, a route passing through the complex multiplier 332b is set as a reference tap, and a more specific description will be given. First, when the signal output from the demodulation circuit 320 is input to the adaptive matched filter 330, the signal is distributed to the multiplier unit and the correlator unit at point P in FIG. On the other hand, there is a delay time from the point P in FIG. 1 until it is input to the correlator 336b through the delay element 334 and the delay element 335a. On the other hand, it passes through the delay element 331a, the complex multiplier 332b, the combiner 333, the combiner 340, the decision feedback equalizer 350, and the determiner 360 to the correlator 336b as the decision data signal S. There is a delay time until input.

  The correlation of a plurality of signals cannot be obtained unless the symbols of all the signals are the same. Therefore, it is necessary to match the time when the two signals are input to the correlator unit. The signal output from the delay element 334 is further branched and input to the delay element 335a and the correlator 336a. The delay elements 335a and 335b in the correlator section are delay elements having a delay time T / 2, similar to the delay elements 331a and 331b in the multiplier section. Moreover, the point connected in series is also the same. The delay element 335a receives the output signal of the delay element 334 as input, and outputs it after giving a delay time T / 2. The delay element 335b receives the output of the delay element 335a as an input, and outputs this after giving a delay time T / 2.

  Correlator 336a receives the output signal of delay element 334, correlator 336b receives the output signal of delay element 335a, and correlator 336c receives the output signal of delay element 335b. The correlators 336a to 336c perform correlation processing between the input signals and the determination data signal S, and then output the results. The outputs of the correlators 336a to 336c are input as tap coefficients Wa to c to the complex multipliers 332a to 332c, respectively, to the complex multipliers having the same delay time.

  In the case of the diversity configuration, the circuits from the mixer 300 to the adaptive matched filter 330 are provided for a plurality of diversity branches. Output signals from the plurality of circuits are synthesized by a synthesizer 340.

  At this time, the combination in the combiner 340 is a maximum ratio combination that maximizes the signal-to-noise power ratio. This is because the phase of the output signal of the adaptive matched filter in each of all the diversity branches is aligned with the phase of the determination data signal S that is the reference signal. Since the phases of the output signals of all the diversity branches match, the energy after synthesis in the synthesizer 340 becomes maximum.

  The decision feedback equalizer 350 receives the output signal of the synthesizer 340, the signal after the decision by the decision unit 360, and the error signal obtained by taking the difference before and after the decision. The residual intersymbol interference is removed from these input signals and then output.

  The decision feedback equalizer 350 includes a circuit that detects the phase error of the input signal, and digitizes the deviation from the lattice point and outputs it as a carrier phase difference signal. The decision unit 360 receives the output signal of the decision feedback equalizer 350 from which the intersymbol interference is removed, makes a decision of 0 or 1, and outputs it. The output signal becomes the determination data signal S.

  Next, the operation of the adaptive matched filter 330 will be described in detail. Signal processing in the adaptive matched filter is generally referred to as “matched filtering”. The functions include convergence and symmetrization of impulse responses distributed on the time axis, signal enhancement associated therewith, and timing control functions.

  FIG. 2 is a diagram for explaining an impulse response in the adaptive matched filter. FIG. 2A is an example of a configuration diagram of a general adaptive matched filter. 2B to 2D are diagrams showing the distribution of impulse responses in each tap, where the horizontal axis represents time and the vertical axis represents magnitude. FIG. 2B is an example of a waveform diagram of the input impulse response. FIG. 2C is an example of a tap coefficient distribution diagram. FIG. 2D is an example of a waveform diagram of the output impulse response obtained in FIGS.

  In FIG. 2A, the wave at the center tap is considered as the main wave at time t = 0. The impulse response of the tap wave advanced by T / 2 with respect to h0 and h0 is h-1, and the impulse response of the tap wave delayed by T / 2 is h + 1. At this time, the adaptive matched filter 330 estimates a distribution that is a time-reversed complex conjugate of the impulse response as a tap coefficient as shown in FIG. This can be shown by the following calculation formula.

  Before showing the calculation formula, the correlators 336a to 336c will be supplemented. Each of the correlators 336a to 336c includes a 90 ° phase distributor, a multiplier, a double amplifier, and a low-pass filter. The signals input to the correlators 336a to 336c are first output with their phases rotated to 0 ° and 90 ° by a 90 ° phase distributor. Thereafter, both outputs are multiplied by the determination data signal S, amplified by a factor of 2, and the high-frequency component is cut by a low-pass filter and output as a tap coefficient.

Now, the input signal D and determination data signal S of the correlators 336a to 336c are defined as follows.
D = a × cos (ω _C t + θ) (Formula 1)
S = cos (ω _R t) (Formula 2)

In Equation 1, a, ω _C , and θ are the amplitude, angular velocity, and phase angle of the input signal D, respectively. In Equation 2, ω _R is the angular velocity of the determination data signal S. Note that the amplitude of the determination data signal is 1.

At this time, the correlator output Y is E, where the symbol representing the time average is
Real part: Y _R = E [a × cos (ω _C t + θ) × cos (ω _R t) × 2] (Equation 3)
Imaginary part: Y _I = E [−a × sin (ω _C t + θ) × cos (ω _R t) × 2] (Formula 4)
It becomes. However, in Equation 4,
a × cos (ω _C t + θ + π / 2) = − a × sin (ω _C t + θ)
Note that

Expanding Equation 3,
Y _R = E [a ((1/2) × cos ((ω _R t) − (ω _C t + θ)) + cos ((ω _R t) + (ω _C t + θ))) × 2] (formula 5)
_{Y R = E [a × cos} ((ω R -ω C) t-θ) + a × cos ((ω R + ω C) t + θ)] ··· ( Equation 6)
here,
cosA × cosB = (1/2) (cos (A−B) + cos (A + B)))
Using
Y _R = a × cos ((ω _R −ω _C ) t−θ)) (Expression 7)
Is obtained. Where
a × cos ((ω _R + ω _C ) t + θ)
Note that this term has been removed with a low-pass filter.

Similarly, if Equation 4 is expanded,
Y _I = a × sin ((ω _R −ω _C ) t−θ)) (Equation 8)
Is obtained.

Here, when ω _R = ω _C , it can be further simplified as the following equation.
Y _R = a × cos (−θ) (Formula 9)
Similarly, from Equation 8,
Y _I = a × sin (−θ) (Equation 10)
Is obtained.

  At this time, in the complex plane, the input signal D is at a point advanced by θ in the positive direction at a distance a, whereas the output Y is at a point advanced by θ in the negative direction at a distance a (= a point delayed by θ). It will be. This indicates that the output signal Y is complex conjugate with the input signal D.

In addition, when FIG. 2B and FIG. 2C are compared as follows, it becomes clear that the time is reversed. That is, consider the case where the impulse response shown in FIG. 2B is input to the adaptive matched filter in FIG. The main wave h _{0 in} FIG. 2 (B) corresponds to the W ₀ tap in FIG. 2 (C). Similarly, the leading wave h ₋₁ is distributed to the W _{+ 1} tap that has been delayed by T / 2 from the W ₀ tap, and the delayed wave h ₊₁ is distributed to the W ₋₁ tap that has been advanced by T / 2 from the W ₀ tap. . That is, the waves on the time axis, to match the time of the main wave h _0, it's distributed by time reversal.

  From the above, it can be explained that the adaptive matched filter estimates a distribution that is a time-reversed complex conjugate as a tap coefficient.

Further, the output signal Z of the adaptive matched filter can be obtained from the equations 1, 7, and 8. The formula is
_{Z = a × cos (ω C} t + θ) × a × cos ((ω R -ω C) t-θ) + (- a × sin (ω C t + θ)) × a × sin ((ω R -ω C) t-θ)
It is. The following formula is applied to this equation.
cos (A) × cos (B) = (1/2) (cos (A−B) + cos (A + B))
sin (A) * sin (B) = (1/2) (cos (AB) -cos (A + B))
Then
^{Z = (a 2/2)} (cos ((2ω C -ω R) t + 2θ) + cos (ω R t)) + (- a 2/2) (cos ((2ω C -ω R) t + 2θ) -cos ( ω _R t))
= A ² cos (ω _R t) (Formula 11)
It becomes. From Equation 11, it can be seen that the phase of the output signal of the adaptive matched filter is aligned with the phase of the determination data signal S, and the amplitude is the square of the input signal.

Figure 2 (D) is an illustration of the distribution of the output impulse response signal, and has a symmetrical on the time axis around the h ₀ at time t = 0. In addition, the energy of h ₀ is also higher than that at the time of input. This is because time-dispersed impulse responses converge at time t = 0 and signal enhancement is performed, and is one of the features of matched filtering.

Next, timing control will be described.
The timing control is realized by a transversal filter whose delay time is a fraction of a symbol period (for example, 1/2 in this case). In addition, the received signal timing in which the delay time fluctuates due to fluctuations in the propagation path is matched with the clock timing phase of the receiver.

In the symbol sequence of the transmission signal, the sampling interval is T. On the other hand, the sampling interval of the adaptive matched filter is T / 2 because it depends on the delay time of the delay element. Therefore, one symbol is always distributed on two or more taps. Here, for example, consider a case where the symbol S ₀ is distributed over the center tap and a tap that is delayed in time by T / 2. At this time, the relative relationship between the magnitude of the tap coefficients W _-1 and W _0, it is possible to vary the timing of S ₀ at the output. That is equivalent to delaying the W _-1 W ₀ increases in time if more, it become to proceed if larger than W _-1 to W ₀ in the opposite.

  The adaptive matched filter operates using this property to match the timing of the received signal of each diversity branch with the clock timing phase of the receiver. FIG. 3 is an example of various waveform diagrams for explaining the timing control function in the adaptive matched filter. 3A to 3C show output waveforms of diversity branches 1 to 3 when matched filtering is not performed. FIG. 3D shows a waveform of a clock signal in the receiver. 3E to 3G show output waveforms when diversity filtering is performed on diversity branches 1 to 3, respectively.

  Since the received signals from the diversity branches are subjected to independent fluctuations in the propagation path, the timings do not match. Therefore, if diversity combining is performed as it is, time dispersion is promoted and the Nyquist no-distortion condition is not satisfied. As a result, the intersymbol interference increases, and there is a high possibility that it cannot be removed by the subsequent decision feedback equalizer. Therefore, in order to satisfy the above condition, it is necessary to absorb the timing shift between the diversity units, and the adaptive matched filter plays this role.

  The above is the description regarding the operation of the adaptive matched filter.

In relation to the above, Patent Document 2 (Japanese Patent Laid-Open No. 7-321866) discloses an invention relating to a demodulator.
The demodulator according to the invention of Patent Document 2 includes a demodulator, an A / D converter, a decision feedback equalizer, a frame synchronization detector, and a clock synchronization circuit. Here, the demodulating means obtains a demodulated baseband signal by separately multiplying the input digital modulated wave by two reproduction carriers each having a phase difference of 90 °. The A / D converter converts the demodulated baseband signal extracted from the demodulator into a digital signal based on the input clock signal. The decision feedback equalizer receives the output digital signal from the A / D converter and equalizes waveform distortion due to fading. The frame synchronization detector receives the output data of the decision feedback equalizer as an input signal and detects frame synchronization. The clock synchronization circuit extracts a clock signal component from the demodulated baseband signal, and generates a clock signal phase-synchronized with the extracted clock signal component when a signal at the time of frame synchronization detection is input from the frame synchronization detector. When it is output to the D conversion means and a signal at the time of non-detection of frame synchronization is input from the frame synchronization detector, a clock signal having a frequency corresponding to the extracted clock signal component is generated and output to the A / D conversion means.

Patent Document 3 (Japanese Patent Laid-Open No. 8-251088) discloses an invention relating to a demodulation system.
The demodulation system of the invention of Patent Document 3 includes a detector, a baseband amplifier, an AD converter, a fading amount detection unit, a reference voltage generator, and an AGC amplifier. Here, the detector detects a received signal which is a signal obtained by wireless transmission of a digitally modulated signal. The baseband amplifier amplifies the baseband signal output from the detector. The AD converter analog-digital converts the signal amplified by the baseband amplifier. The fading amount detection means detects a fading amount received by the received signal in a demodulation system including a decision feedback equalizer that equalizes the data signal output from the AD converter, and outputs a signal representing the fading amount. Output. The reference voltage generator takes a predetermined value when the fading amount is zero based on the output signal of the fading amount detection means, generates a voltage that takes a value that decreases as the fading amount increases, and outputs the analog input signal to the AD converter. It is supplied as a reference voltage which is a reference for comparison. The AGC amplifier adjusts the level of the received signal so as to reduce the error of the value of the data signal equalized and output by the decision feedback equalizer and is supplied to the detector as an input signal to be detected. .

Patent Document 4 (Japanese Patent Laid-Open No. 10-285091) discloses an invention relating to a demodulator.
The demodulator according to Patent Document 4 receives and demodulates a multilevel quadrature amplitude modulated wave. Further, the apparatus includes an automatic amplitude equalizing means, a demodulating means, a waveform equalizing means, a control means, a detecting means, and a limiting means. Here, the automatic amplitude equalization means equalizes the amplitude of the received signal on the frequency axis. The demodulating means demodulates the output of the automatic amplitude equalizing means. The waveform equalization means equalizes the waveform on the time axis of the demodulated output. The control means controls the automatic amplitude equalization means according to the output of the waveform equalization means. The detecting means detects the level of the predetermined frequency region of the received signal. The limiting unit limits the amplitude correction amount of the automatic amplitude equalizing unit according to the detection level.

Patent Document 5 (Japanese Patent Laid-Open No. 10-341193) discloses an invention relating to an adaptive receiver.
The adaptive receiver of the patent document 5 has an adaptive matched filter, a determiner, a reference clock, a phase comparator, a voltage control oscillator, and timing means. Here, the adaptive matched filter receives received data. The determiner outputs a determination data signal from the output of the adaptive matched filter. The phase comparator compares the phase of the clock signal component of the output of the adaptive matched filter and the reference clock. The voltage control oscillator is controlled by the phase difference component from the phase comparator. The timing means synchronizes the determination data signal with the output phase of the voltage control oscillator and outputs it as a reference signal for the adaptive matched filter.

Japanese Patent Laid-Open No. 6-232774 Japanese Patent Laid-Open No. 7-321866 JP-A-8-251088 Japanese Patent Laid-Open No. 10-285091 Japanese Patent Laid-Open No. 10-341193

The conventional adaptive receiver has the following problems.
The first problem is that when the multipath fading is received in the propagation path, the phase of the clock is changed.

  The cause is that the clock extraction circuit is arranged in front of the adaptive matched filter. Intersymbol interference remains before the adaptive matched filter. Therefore, the data conversion point shifts due to the influence of the forward wave and the delayed wave due to multipath fading. Since the clock extraction circuit refers to the data conversion point, the phase variation of the clock occurs as a result.

  The second problem is that the phase rotation performed in the quasi-synchronous detection competes with the timing control function in the adaptive control filter.

  As a result, the position of the reference tap is inadvertently shifted, and the jitter component is promoted.

  An object of the present invention is to provide an adaptive receiver that can maintain stable clock recovery and a timing control function even when intersymbol interference occurs due to multipath fading.

  Hereinafter, means for solving the problem will be described using the numbers used in (Best Mode for Carrying Out the Invention). These numbers are added to clarify the correspondence between the description of (Claims) and (Best Mode for Carrying Out the Invention). However, these numbers should not be used to interpret the technical scope of the invention described in (Claims).

  The adaptive receiver according to the present invention includes a demodulation matching circuit (100, 101, 110, 111, 120, 130), a decision feedback equalizer (150), and a clock synchronization circuit (180). Here, the demodulation matching circuit (100, 101, 110, 111, 120, 130) synchronizes, demodulates, matches, and outputs the input signal. The decision feedback equalizer (150) is connected to the subsequent stage of the demodulation and matching circuit (100, 101, 110, 111, 120, 130), removes the intersymbol interference of the main signal and outputs it, and also outputs the carrier phase difference. Is also output. The clock synchronization circuit (180) is connected to the subsequent stage of the decision feedback equalizer and controls the clock phase information according to the carrier phase difference.

  In the adaptive receiver according to the present invention, the demodulation matching circuit (100, 101, 110, 111, 120, 130) includes an adaptive matched filter (130) having a plurality of taps. Here, the adaptive matched filter (130) includes a plurality of complex multipliers (132a-c), a plurality of correlators (138a-c), and a tap coefficient output circuit (139). Here, the plurality of complex multipliers (132a to 132c) complex-multiply the input signal with tap coefficients for each of the plurality of taps and output the result. The plurality of correlators (138a to 138c) output tap coefficients. The tap coefficient output circuit (139) outputs the tap coefficients output from the plurality of correlators (138a to 138c) to the plurality of complex multipliers (132a to c). The demodulation matching circuit (100, 101, 110, 111, 120, 130) further includes a carrier synchronization circuit (121) that performs carrier phase control according to the distribution of tap coefficients.

  In the adaptive receiver according to the present invention, the adaptive matched filter (130) further includes a plurality of phase shifters (133a-c) that align phases of a plurality of signals output from the plurality of complex multipliers (132a-c). To do.

  The demodulation matching circuit (100, 101, 110, 111, 120, 130) according to the present invention includes a local frequency oscillator (101) that oscillates and outputs a predetermined frequency, and a voltage-controlled crystal oscillator that outputs a clock signal according to an input voltage. (111).

  The adaptive receiver according to the present invention includes one or more demodulation matching circuits connected in parallel to the demodulation matching circuits (100, 101, 110, 111, 120, 130) and a plurality of demodulation matching circuits (100, 101, 110). , 111, 120, 130) and a diversity combiner (140) for combining the outputs and inputting the decision feedback equalizer (150).

  In the adaptive receiver according to the present invention, each of the plurality of demodulation matching circuits (100, 101, 110, 111, 120, 130) includes a local frequency oscillator (101) that oscillates and outputs a predetermined frequency, and a clock according to the input voltage. A voltage controlled crystal oscillator (111) for outputting a signal.

  The adaptive receiver according to the present invention includes a local frequency oscillator (101) that oscillates and outputs a predetermined frequency, and a voltage-controlled crystal oscillator (111) that outputs a clock signal according to an input voltage. The local frequency oscillator (101) and the voltage controlled crystal oscillator (111) are connected to a plurality of demodulation matching circuits (100, 101, 110, 111, 120, 130), respectively.

  The adaptive reception method according to the present invention includes (a) setting the operation of the adaptive matched filter (130) to one-tap operation when the adaptive receiver is asynchronous, and (b) carrier synchronization when the adaptive receiver is asynchronous. Setting the phase rotation speed of the circuit (121) to a predetermined initial value; and (c) setting the phase rotation speed of the carrier synchronization circuit (121) slower than the initial value when the adaptive receiver is synchronized. (D) when the adaptive receiver is synchronized, the operation of the adaptive matched filter (130) is set to a multi-tap operation; and (e) the plurality of taps of the adaptive matched filter (130) are monitored and a reference tap is set. And (f) returning the shifted reference tap to the center tap when it occurs continuously over a predetermined time.

  In the adaptive reception method according to the present invention, the step (e) includes (e-1) determining the occurrence of the shift when the shift of the reference tap is continuously observed for a predetermined time.

  In the adaptive reception method according to the present invention, step (f) comprises (f-1) rotating the phase of the carrier wave in a direction opposite to the direction when the reference tap shift occurs.

  In the adaptive receiver according to the present invention, a clock synchronization (CLK SYNC: CLocK SYNC) circuit is arranged after the decision feedback equalizer. As a result, the influence of intersymbol interference can be minimized in the CLK extraction.

  The tap coefficient output circuit in the adaptive matched filter in the adaptive receiver of the present invention monitors the tap coefficient distribution, and passes the synchronization information and information indicating the presence or absence of tap shift to the carrier wave synchronization circuit. In the carrier synchronization circuit, based on the synchronization information, the phase control is made fine during synchronization so as not to compete with the timing control function of the adaptive matched filter. Further, based on the information indicating the presence or absence of a tap shift, phase control is performed so that when there is a tap shift, the tap moves in a direction opposite to the shifted direction.

Furthermore, a phase shifter is provided at the output of the complex multiplier of the adaptive matched filter in the adaptive receiver of the present invention. As a result, by making the phase of the signal coincide with the phase of the determination data signal, it is possible to perform ideal synthesis that is not easily influenced by the clock.

  The best mode for carrying out an adaptive receiver according to the present invention will be described below with reference to the accompanying drawings.

(First embodiment)
FIG. 4 is an example of a configuration diagram of an adaptive receiver according to the first embodiment of the present invention. Here, for simplicity of explanation, the case of 3 taps is shown, but the number of taps is determined based on the delay profile of the propagation path, and the present invention is not limited to 3 taps.

  The adaptive receiver according to this embodiment includes a mixer 100, a local frequency oscillator 101, an analog / digital conversion circuit 110, a voltage control crystal oscillator 111, a demodulation circuit 120, an adaptive matched filter 130, and a diversity synthesizer 140. A decision feedback equalizer 150, a synchronization detection circuit 160, a sign determination unit 170, and a clock synchronization circuit 180.

  Here, the demodulation circuit 120 includes a carrier wave (CARR) synchronization circuit 121.

  The adaptive matched filter includes a multiplier unit, a delay element 136, and a correlator unit. The multiplier section includes delay elements 131a-b, complex multipliers 132a-c, phase shifters 133a-c, a combiner (Σ) 134, and a flip-flop 135. The correlator unit includes delay elements 137a to 137b, correlators 138a to 138c, and a tap coefficient output circuit 139.

  Further, the clock synchronization circuit 180 includes a clock extraction circuit 181, a phase comparator 182, a loop filter (LPF) 183, a voltage controlled oscillator (VCO), a frequency divider (1 / N) 185, It comprises.

Here, the connection relationship between the components in the adaptive receiver according to the present embodiment will be described.
The mixer 100 is connected to the outside that is the input source of the input signal R, the local frequency oscillator 101, and the analog / digital conversion circuit 110. The analog / digital conversion circuit 110 is further connected to a voltage controlled crystal oscillator 111 and a carrier wave synchronization circuit 121 of the demodulation circuit 120. The voltage controlled crystal oscillator 111 is further connected to the clock synchronization circuit 180. The carrier synchronization circuit 121 of the demodulation circuit 120 is further connected to the adaptive matched filter 130 and the decision feedback equalizer 150. The adaptive matched filter 130 is further connected to a diversity synthesizer 140, a sign determination unit 170, and a clock synchronization circuit 180. Diversity combiner 140 is further connected to decision feedback equalizer 150. The decision feedback equalizer 150 is further connected to a synchronization detection circuit 160 and a sign decision unit 170. The sign determination unit 170 is further connected to the outside, which is the output destination of the determination data signal S.

Here, the connection relationship between the components in the adaptive matched filter 130 will be described.
The carrier synchronization circuit 121 of the demodulation circuit 120 is connected to the delay element 131 a, the complex multiplier 132 a, and the delay element 136 in the adaptive matched filter 130. The delay element 131a is further connected to the delay element 131b and the complex multiplier 132b. The delay element 131b is further connected to a complex multiplier 132c. The complex multipliers 132a to 132c are further connected to the phase shifters 133a to 133c, respectively. The phase shifters 133a to 133c are further connected to the combiner 134 and the sign inverter 170. The combiner 134 is further connected to a flip-flop 135. The flip-flop 135 is further connected to the diversity combiner 140, the synchronization detection circuit 160, and the frequency dividing circuit 185.

  The delay element 136 is further connected to a delay element 137a and a correlator 138a. The delay element 137a is further connected to the delay element 137b and the correlator 138b. The delay element 137b is further connected to a correlator 138c. The correlators 138a to 138c are further connected to the tap coefficient output circuit 139. Tap coefficient output circuit 139 is further connected to carrier wave synchronization circuit 121 of demodulation circuit 120, complex multipliers 132a to 132c, and synchronization detection circuit 160.

Here, the connection relationship between the components in the clock synchronization circuit 180 will be described.
The decision feedback equalizer 150 is connected to the phase comparator 182. The synchronization detection circuit 160 is connected to the clock extraction circuit 181. The clock extraction circuit 181 is further connected to a phase comparator 182. The phase comparator 182 is further connected to the loop filter 183. The loop filter 183 is further connected to a voltage controlled oscillator 184. The voltage controlled oscillator 184 is further connected to the frequency dividing circuit 185 and the voltage controlled crystal oscillator 111 of each diversity branch. The frequency dividing circuit 185 is further connected to the phase comparator 182 and the flip-flop 135 of each diversity branch.

Here, the operation of the adaptive receiver according to the present embodiment will be described.
In FIG. 4, an input signal R is an intermediate frequency band signal received from the outside. The local frequency oscillator 101 outputs a local signal. The mixer 100 receives the input signal R and the local signal, demodulates the input signal R into a baseband signal, and outputs the demodulated signal. Note that the output signal of the local frequency oscillator 101 is not completely synchronized with the carrier wave. Therefore, the carrier phase rotation still remains in the output signal of the mixer 100.

  The voltage controlled crystal oscillator 111 oscillates and outputs a signal having a predetermined frequency. The A / D conversion circuit 110 receives the output signal of the mixer 100 and the output signal of the voltage controlled crystal oscillator 111. The A / D conversion circuit 110 samples the output signal of the mixer 100 with the output signal of the voltage controlled crystal oscillator 111 and converts it into a digital signal, and then outputs the digital signal.

  The carrier synchronization circuit 121 receives the output signal of the A / D conversion circuit 110, the output signal of the tap coefficient output circuit 139, and the carrier phase difference signal output from the decision feedback equalizer 150. The carrier synchronization circuit 121 removes the phase difference remaining in the output signal of the A / D conversion circuit 110 and then outputs this.

  The adaptive matched filter 130 receives the output signal of the carrier wave synchronization circuit 121, branches the signal into two, and guides the two branched signals to the multiplier unit and the correlator unit.

  In the multiplier section, the delay element 131a gives a delay time of T / 2 to the input signal and then outputs it. The delay element 131b receives the output signal of the delay element 131a, and similarly outputs a delay time of T / 2 after giving a delay time of T / 2. The complex multipliers 132a to 132c are inputted with output signals from the carrier synchronization circuit 121, the delay element 131a, and the delay element 131b, respectively. Each of the complex multipliers 132a to 132c performs a complex multiplication process on the input signals with the tap coefficients Wa to c, and outputs the result.

  That is, the complex multiplier 132a receives the output signal of the carrier wave synchronization circuit 121, performs a complex multiplication process on the input signal with the tap coefficient Wa, and outputs the result. Similarly, the complex multiplier 132b receives the output signal of the delay element 131a, performs complex multiplication processing on the input signal with the tap coefficient Wb, and outputs the resultant signal. The complex multiplier 132c receives the output signal of the delay element 131b, performs complex multiplication processing on the input signal by the tap coefficient Wc, and outputs the resultant signal.

  The phase shifters 133a to 133c receive the output signals of the complex multipliers 132a to 132c and the determination data signal S, respectively. That is, the phase shifter 133a receives the output signal of the complex multiplier 132a and the determination data signal S. The phase shifter 133b receives the output signal of the complex multiplier 132b and the determination data signal S. The phase shifter 133c receives the output signal of the complex multiplier 132c and the determination data signal S.

  The phase shifters 133a to 133c output the phase of the output signal of each complex multiplier 132a to 132c with the phase of the determination data signal S as a reference. That is, the phase shifter 133a outputs the phase of the output signal of the complex multiplier 132a with the phase of the determination data signal S as a reference. That is, the phase shifter 133b outputs the phase of the output signal of the complex multiplier 132b with the phase of the determination data signal S as a reference. That is, the phase shifter 133c matches the phase of the output signal of the complex multiplier 132c with the phase of the determination data signal S as a reference, and outputs it.

  The synthesizer 134 receives the output signals of the phase shifters 133a to 133c and outputs them after synthesizing them.

  The flip-flop 135 receives the output signal of the synthesizer 134, the clock signal output from the frequency dividing circuit 185, and the synchronization signal Y output from the synchronization detection circuit 160. The flip-flop 135 re-times the output signal of the synthesizer 134 with the clock signal and outputs it.

  On the other hand, first, the delay element 136 receives the output signal of the carrier wave synchronization circuit 121 and gives a delay time τ, and then outputs it to the correlator unit. Here, the delay time τ is the same value as in the prior art. That is, when there is no distortion, when the center tap is used as a reference tap, the delay time τ is determined so that the timings of two identical symbols input to the correlator 138b of the center tap match.

  The output signal of the delay element 136 is branched into two and input to the delay element 137a and the correlator 138a. The delay element 137a receives the output signal of the delay element 136, gives it a delay time T / 2, and outputs it. The delay element 137b receives the output signal of the delay element 137a, gives a delay time T / 2 thereto, and outputs it.

  Correlator 138a receives the output signal of delay element 136 and determination data signal S. The correlator 138a performs correlation processing between the output signal of the delay element 136 and the determination data signal S, and then outputs the result. The correlator 138b receives the output signal of the delay element 137a and the determination data signal S. The correlator 138b performs correlation processing between the output signal of the delay element 137a and the determination data signal S, and then outputs the result. The correlator 138c receives the output signal of the delay element 137b and the determination data signal S. The correlator 138c performs correlation processing between the output signal of the delay element 137b and the determination data signal S, and then outputs the result.

  The tap coefficient output circuit 139 receives the output signals of the correlators 138a to 138c and the synchronization signal Y. The tap coefficient output circuit 139 performs appropriate control according to the state of each input signal, and then outputs Wa to c to the complex multipliers 132 a to 132 c as tap coefficients. Similarly, the tap coefficient output circuit 139 outputs a control signal to the carrier wave synchronization circuit 121.

  Now, the description returns to the multiplier section. The output signal of the flip-flop 135 becomes the output signal of the adaptive matched filter 130. When the adaptive receiver of this embodiment has a diversity configuration, the output signals of the adaptive matched filters of a plurality of diversity branches are input to the combiner 140 and combined. At this time, the synthesis in the synthesizer 140 is the maximum ratio synthesis because the phases of the plurality of input signals are the same as in the prior art.

  An output signal from the combiner 140 is input to the decision feedback equalizer 150. The decision feedback equalizer 150 receives the input signal from the synthesizer 140, the error signal before and after the sign decision unit 170, and the decision data signal S. Here, the error signal before and after the code determiner 170 is a difference signal between the signal input to the code determiner 170 and the signal output from the code determiner 170.

  The decision feedback equalizer 150 removes the intersymbol interference contained in the input signal from the combiner 140 and outputs it. The decision feedback equalizer 150 includes a circuit that detects a phase error of the input signal from the synthesizer 140. The decision feedback equalizer 150 quantifies the deviation from the lattice point and outputs it as a carrier phase difference.

  The synchronization detection circuit 160 receives the output signal of the decision feedback equalizer 150 and determines whether or not the input signal is synchronized. The synchronization detection circuit 160 outputs the determination result as a synchronization signal Y. The synchronization detection circuit 160 outputs the signal input from the decision feedback equalizer 150 to the subsequent circuit as it is.

  The signal output from the synchronization detection circuit 160 is branched and input to the clock synchronization circuit 180 and the determination unit 170.

  The signal input to the clock synchronization circuit 180 is first input to the clock extraction circuit 181 as it is. The clock extraction circuit 181 extracts the clock component from the input signal and outputs it.

  The phase comparator 182 receives the clock component extracted and output by the clock extraction circuit 181, the carrier phase difference signal output from the decision feedback equalizer 150, and the clock signal output from the frequency divider 185. The The phase comparator 182 compares the phase of each input signal and then outputs the result as a voltage.

  The loop filter 183 receives the voltage output from the phase comparator 182, performs integration processing, and outputs it.

  The VCO 184 receives the output voltage of the loop filter 183 and outputs a sine wave having a frequency corresponding to this voltage. The output signal of the VCO 184 is used by the receiving apparatus as a clock signal having a period of N (fs).

  The frequency dividing circuit 185 receives the output signal of the VCO 184, divides the input signal by N, and outputs it. The output signal of the frequency dividing circuit 185 is input to the flip-flop 135 and the phase comparator 182 and used as a clock signal having the same cycle as the data.

  The determination unit 170 receives the output signal of the synchronization detection circuit 160 and determines whether the input signal is 0 or 1. The determiner 170 outputs the determination result as a determination data signal S.

Next, the operation of this embodiment shown in FIG. 4 will be described.
The detection method of the adaptive receiver of the present embodiment is a quasi-synchronous detection method as in the related art. The carrier synchronization circuit 121 removes the phase rotation component remaining in the received signal based on the carrier phase difference signal from the decision feedback equalizer 150. Here, as described above, in order to compete with the adaptive matched filter, after the synchronization is established, the control speed of the carrier synchronization circuit 121 is slowed down to a region where it does not compete. Specifically, the control is performed as follows.

FIG. 5 shows a control method for each state.
In step S1 of FIG. 5, the adaptive control filter is set to a 1-tap operation when the adaptive receiver is not synchronized, such as when it rises. In addition, the phase speed of the carrier wave synchronization circuit 121 is set as usual. Here, information on whether or not the adaptive receiver is in synchronization is obtained by receiving the synchronization signal Y through the tap coefficient output circuit 139.

The reason why the adaptive control filter is set to one tap operation will be described.
First, at the time when synchronization is not established, a correlation cannot be obtained between the signal output from the demodulation circuit 120 and the determination data signal S. Accordingly, the outputs of all the correlators 138a to 138c are almost zero, and the multiplication results in the complex multipliers 132a to 132c are also zero. This means that no signal passes through the adaptive matched filter.

  Since this state does not synchronize forever, it is necessary to forcibly give tap coefficients until the time of asynchronization, that is, until the correlators 138a to 138c are correlated and synchronized. As a means at this time, a one-tap operation is performed. That is, only the coefficient of the reference tap is set to 1, and the coefficients of other taps are set to 0. In this example, since the center tap is a reference tap, only the tap coefficient Wb of the complex multiplier 132b of the center tap is set to 1. Further, the tap coefficients Wa and Wc of the complex multipliers 132a and 132c in FIG. By fixing the tap coefficients in this way, the adaptive matched filter 130 is in the same state as passing the signal without processing.

  The tap coefficient is controlled by the tap coefficient output circuit 139 as described above. In step S2, since the tap coefficient output circuit 139 takes in the synchronization signal Y, it is possible to grasp the synchronization state. If it is determined that the state is an asynchronous state, in step S3, the complex multipliers 132a to 132c are operated so as to give a fixed value. That is, in the asynchronous state, the adaptive matched filter 130 is set to 1 tap operation. As described above, signal disconnection in the adaptive matched filter can be prevented.

  In addition, the carrier synchronization circuit 121 superimposes the SWEEPER signal when the step S3 is asynchronous, thereby increasing the amplitude of an APC (Automatic Phase Control) signal for carrier synchronization. As a result, the frequency range to be drawn is expanded.

  After the synchronization, in step S4, the phase control in the carrier wave synchronization circuit 121 is made fine. Specifically, the carrier wave synchronization circuit 121 is a PLL circuit and includes a loop filter therein. The output of the loop filter is an APC signal, and a CARR signal having a frequency corresponding to the APC signal is output. Therefore, in order to perform the phase control as described above, the output of the loop filter may be controlled. The loop filter integrates the phase error signal and suppresses the noise component. By changing the coefficient here, the noise bandwidth, damping factor, and loop gain can be changed. In this embodiment, not only the SWEEPER signal is stopped at the time of synchronization, but also the coefficient is changed to slow down the phase control. This prevents contention with the adaptive matched filter timing control.

  After delaying the phase control of the carrier wave synchronizing circuit 121, in step S5, the tap operation of the adaptive matched filter 130 is changed from one tap to a full tap. The tap coefficient output circuit 139 always observes the numerical value of the tap coefficient, and can detect even when the reference tap is shifted from the center. Normally, when there is no distortion in the propagation path that is not affected by multipath fading, the adaptive matched filter 130 of this embodiment operates so that the center tap becomes the reference tap. This is because if the reference tap is subjected to intersymbol interference with the end tap being left, it cannot be shifted any further because it is already at the end, and therefore a symmetric impulse response cannot be generated. Even if it is not at the end, since the taps in the same time axis direction as the shift are reduced, the generation of a symmetric impulse response is affected. That is, as a result, there is a possibility that the load on the decision feedback equalizer 150 in the subsequent stage increases and the intersymbol interference cannot be removed. The reason for placing the reference tap at the center tap is as described above.

Here, it is assumed that a delayed echo is generated due to the influence of the propagation path. At this time, in the tap coefficient distribution, the tap coefficient of the correlator 138a becomes large. When the magnitude of the delayed echo further increases and the D / U ratio (Desire to Undesiratio ratio) increases until it is reversed, the tap coefficient of the correlator 138a is more than the tap coefficient of the center tap. Becomes larger. In step S6, the tap coefficient output circuit 139 monitors the outputs of the correlators 138a to 138c. When recognizing that the reference tap is shifted from the center tap, the tap coefficient output circuit 139 controls the carrier wave synchronization circuit 121 in step S7. That is, control is performed to rotate the phase of the carrier wave so that the reference tap is returned to the center tap. However, since it is not necessary to react to instantaneous fading, it is desirable to determine the presence or absence of tap shift, which is a condition for performing the above-described operation, after observing continuously for a certain period of time. Further, the control for the carrier synchronization circuit 121 by the tap coefficient output circuit 139 is prioritized over the control by the carrier phase difference signal output from the decision feedback equalizer 150.
The above is the description regarding the carrier wave synchronization operation.

Next, as a point different from the related art, the point that the phase shifters 133a to 133c are provided in the adaptive matched filter 130 will be described.
When signals are synthesized by the synthesizer 134 or the synthesizer 140, the phases must be matched. The output signals of the complex multipliers 133a to 133c are aligned with the phase of the determination data signal S by the phase shifters 133a to 133c, respectively. Thereby, ideal signal enhancement and maximum ratio synthesis can be expected.

Next, the flip-flop 135 will be described.
The flip-flop 135 is provided at the final output stage of the adaptive matched filter 130 for the purpose of retiming the output signal of the adaptive matched filter 130 with the reception clock. Retiming prevents unexpected fluctuations in the clock phase due to fading. However, phase fluctuations may be promoted when the clock synchronization is not established. Accordingly, the flip-flop 135 performs an operation of passing a signal without performing retiming at the time of asynchronous in step S1 or step S3.

In addition, as a point different from the related art, a point that the clock synchronization circuit 180 is arranged at the subsequent stage of the decision feedback equalizer 150 will be described.
The intersymbol interference is removed from the signal input to the clock synchronization circuit 180 by the decision feedback equalizer 150. Therefore, the clock extraction circuit 181 is not affected by fading in CLK extraction. Therefore, the clock synchronization circuit 180 is sufficiently resistant to clock fluctuations in the input signal.

  However, the PLL in the clock synchronization circuit 180 and the loopback circuit of the decision feedback equalizer 150 form a double loop, and the operation of the adaptive receiver may become unstable.

  In order to avoid such a case, the carrier phase difference signal of the decision feedback equalizer 150 is taken into the phase comparator 182 in the clock synchronization circuit 180. In this way, the phase error of the carrier wave is always monitored. When the value of the phase error of the carrier wave exceeds the set threshold value, the CLK phase error signal output from the clock extraction circuit 181 is invalidated and the PLL is turned off. This operation prevents in advance the operation of the adaptive receiver from becoming unstable.

  In addition, the diversity structure of a present Example is not necessarily a structure required in this invention. If the adaptive receiver of the present invention does not have a diversity structure, the diversity combiner 140 can also be omitted.

(Second embodiment)
FIG. 6 is an example of a configuration diagram of an adaptive receiver according to the second exemplary embodiment of the present invention.
The adaptive receiver according to the second embodiment is a modification of the first embodiment with some modifications. That is, the local frequency oscillator 101 and the voltage controlled crystal oscillator 111 are shared by all or some of the diversity branches. In this case, there is no functional change, and the cost and mounting are excellent.

FIG. 1 is an example of a configuration diagram of an adaptive receiver according to a technique related to the present invention. FIG. 2 is a diagram for explaining an impulse response in the adaptive matched filter. FIG. 2A is an example of a configuration diagram of a general adaptive matched filter. FIG. 2B is an example of a waveform diagram of the input impulse response. FIG. 2C is an example of a tap coefficient distribution diagram. FIG. 2D is an example of a waveform diagram of the output impulse response obtained in FIGS. FIG. 3 is an example of various waveform diagrams for explaining the timing control function in the adaptive matched filter. 3A to 3C show output waveforms of diversity branches 1 to 3 when matched filtering is not performed. FIG. 3D shows a waveform of a clock signal in the receiver. 3E to 3G show output waveforms when diversity filtering is performed on diversity branches 1 to 3, respectively. FIG. 4 is an example of a configuration diagram of an adaptive receiver according to the first embodiment of the present invention. FIG. 5 is an example of a flowchart of an adaptive reception method according to the present invention. FIG. 6 is an example of a configuration diagram of an adaptive receiver according to the second exemplary embodiment of the present invention.

Explanation of symbols

100, 300 Mixer 101, 301 Local frequency oscillator (LO)
110, 310 Analog-to-digital (A / D) conversion circuit 111, 311 Voltage controlled crystal oscillator (VCXO)
120, 320 Demodulator (DEM)
121, 321 Carrier (CARR) synchronization circuit 130, 330 Adaptive matched filter (AMF)
131a-b, 331a-b Delay element 132a-c, 332a-c Complex multiplier 133a-c Phase shifter 134, 333 Synthesizer (Σ)
135 Flip-flop 136, 334 Delay element 137a-b, 335a-b Delay element 138a-c, 336a-c Correlator 139 Tap coefficient output circuit 140, 340 Diversity combiner 150, 350 Decision feedback equalizer (DFE)
160 Sync detection circuit 170, 360 Sign determination unit 180 Clock synchronization circuit (CLK SYNC)
181 and 322 Clock extraction circuit 182 and 323 Phase comparator 183 and 324 Loop filter (LPF)
184 Voltage controlled oscillator (VCO)
185 Frequency divider (1 / N)
325 Digital / analog (D / A) conversion circuit

Claims (10)

A demodulation matching circuit that synchronizes, demodulates, matches, and outputs an input signal;
A decision feedback equalizer that is connected to the subsequent stage of the demodulation and matching circuit and that outputs the main signal with the intersymbol interference removed, and also outputs the carrier phase difference,
An adaptive receiver comprising a clock synchronization circuit connected to a subsequent stage of the decision feedback equalizer and controlling clock phase information in accordance with the carrier phase difference. An adaptive receiver as claimed in claim 1,
The demodulation matching circuit is
Comprising an adaptive matched filter having a plurality of taps;
The adaptive matched filter is:
For each of the plurality of taps, a plurality of complex multipliers that complex-multiply an input signal with a tap coefficient and output,
A plurality of correlators that output the tap coefficients for each of the plurality of taps;
A tap coefficient output circuit that outputs the tap coefficients output from the plurality of correlators to the plurality of complex multipliers,
The demodulation matching circuit is
An adaptive receiver further comprising a carrier synchronization circuit that performs carrier phase control according to the distribution of the tap coefficients. The adaptive receiver according to claim 1 or 2,
The adaptive matched filter is:
An adaptive receiver further comprising a plurality of phase shifters for aligning phases of a plurality of signals output from the plurality of complex multipliers. The demodulation matching circuit according to any one of claims 1 to 3,
A local frequency oscillator that oscillates and outputs a predetermined frequency;
An adaptive receiver further comprising a voltage controlled crystal oscillator that outputs a clock signal in accordance with an input voltage. The adaptive receiver according to any one of claims 1 to 3,
One or more demodulation matching circuits connected in parallel to the demodulation matching circuit;
An adaptive receiver further comprising: a diversity combiner that combines outputs of the plurality of demodulation matching circuits and inputs the combined outputs to the decision feedback equalizer. The adaptive receiver according to claim 5, wherein
Each of the plurality of demodulation matching circuits is
A local frequency oscillator that oscillates and outputs a predetermined frequency;
An adaptive receiver comprising: a voltage-controlled crystal oscillator that outputs a clock signal according to an input voltage. The adaptive receiver according to claim 5 is:
A local frequency oscillator that oscillates and outputs a predetermined frequency;
A voltage controlled crystal oscillator that outputs a clock signal according to an input voltage,
The local frequency oscillator and the voltage controlled crystal oscillator are connected to each of the plurality of demodulation matching circuits. (A) when the adaptive receiver is asynchronous, setting the operation of the adaptive matched filter to a one-tap operation;
(B) setting the phase rotation speed of the carrier synchronization circuit to a predetermined initial value when the adaptive receiver is asynchronous.
(C) at the time of synchronization of the adaptive receiver, setting the phase rotation speed of the carrier synchronization circuit slower than the initial value;
(D) setting the operation of the adaptive matched filter to a multi-tap operation during the synchronization of the adaptive receiver;
(E) monitoring the plurality of taps of the adaptive matched filter to determine a shift of a reference tap from a center tap;
(F) The adaptive reception method comprising: returning the shifted reference tap to the center tap when the occurrence occurs continuously over a predetermined time. The adaptive reception method according to claim 8,
The step (e)
(E-1) An adaptive reception method comprising: determining that a shift of the reference tap has occurred when the shift of the reference tap is continuously observed for a predetermined time. The adaptive reception method according to claim 8 or 9,
The step (f)
(F-1) An adaptive reception method comprising rotating a phase of a carrier wave in a direction opposite to a direction when the reference tap shift occurs.

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