JP3114596B2 - Nuclear magnetic resonance inspection system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nuclear magnetic resonance inspection apparatus for performing imaging and spectroscopy measurement using a nuclear magnetic resonance phenomenon (MR phenomenon), and particularly to generating a gradient magnetic field and a waveform of a high-frequency excitation signal. It relates to improvement of a waveform generation circuit.

[0002]

2. Description of the Related Art In a nuclear magnetic resonance inspection apparatus, a subject is arranged in a static magnetic field generated by a main magnet, and a high frequency having a resonance frequency component corresponding to the strength of the static magnetic field is applied to the subject. An excitation signal and a gradient magnetic field that encodes an imaging section and position information in the imaging section are applied according to a predetermined pulse sequence. Then, after receiving a resonance signal generated by the nuclear magnetic resonance phenomenon in the subject and performing appropriate signal processing, the image is reconstructed by performing a Fourier transform.

As the high-frequency excitation signal, a signal obtained by amplitude-modulating a high-frequency signal having a resonance frequency into a predetermined pulse waveform is usually used. The gradient magnetic field is also applied in a predetermined pulse waveform. Conventionally, circuits for generating these waveforms have been configured as dedicated ones using a register memory, a counter, a waveform memory, a multiply-adder, and the like.

[0004]

However, the conventional waveform generating circuit has a problem that it is difficult to cope with the recent development of the nuclear magnetic resonance inspection apparatus. That is, the pulse sequence required for imaging has become complicated with the development of imaging techniques, and it has become necessary to perform complicated waveform processing at high speed. However, in order to respond to this, the complexity and scale of the circuit are inevitable, which not only increases the mounting area and power consumption, but also reduces the reliability of the circuit. .

SUMMARY OF THE INVENTION In view of the above, the present invention provides an improved waveform that can avoid an increase in the number of components, a mounting area, and power consumption due to the complexity of a circuit, and also avoid a decrease in circuit reliability. An object of the present invention is to provide a nuclear magnetic resonance inspection apparatus including a generation circuit.

[0006]

According to the present invention, there is provided a means for generating a static magnetic field, means for generating a gradient magnetic field so as to be superimposed on the static magnetic field, and transmission of a high-frequency excitation signal. Means, receiving means for receiving a resonance signal, detecting the received signal and performing A / D conversion to obtain data, means for processing the data to reconstruct an image, generation of a gradient magnetic field, transmission of a high-frequency excitation signal And a sequence control means for controlling the reception of the resonance signal, the nuclear magnetic resonance inspection apparatus, a waveform generating circuit for generating the waveform of the gradient magnetic field and the waveform of the high-frequency excitation signal, an input port,
A plurality of independent registers to which data is sent via the input port, a plurality of counters connected to each register so as to form a pair with these registers, and a combination for selecting an output of these counters in any combination A selector, an arithmetic circuit for performing a multiply-add process on an output of the combination selector, a chip controller for controlling the counter, the combination selector, and the arithmetic circuit based on data input through the input port; and an output port. Are stored in one chip and two one-chip circuits are configured. In one of the one-chip circuits, the initial value of each counter is sent to each register from the sequence control means via an input port, Each counter is controlled by the chip controller so that the time interval for counting operation is fixed. A count value that counts up at the determined time interval from the initial value is output, and each count value is selected in an arbitrary combination by a combination selector, and a value subjected to multiplication and addition processing by an arithmetic circuit is calculated. This one-chip circuit is configured as an address generation circuit for a waveform memory, and a value that is not processed is output as an address data of a waveform memory from an output port in an arbitrary combination. In the circuit, the peak value data read out from the waveform memory by addressing is stored in each register through the input port, and the peak value data stored in each register is combined through a counter controlled to be turned off by the chip controller. Sent to the selector, selected in any combination, and multiplied and added by the arithmetic circuit By being configured to be outputted as from the processed waveform data output port is, it has a feature that the one-chip circuit is configured as a processing circuit of the waveform data.

An address generating circuit of a waveform memory is constituted by using one one-chip circuit. In this one-chip circuit, by combining a counter with each of a plurality of independent registers, a count value output at an arbitrary time interval from an arbitrary initial value can be obtained from the counter. Also, the output of these counters is
Use the combination selector to select any combination,
Multiplication / addition processing can be performed by the arithmetic circuit. Then, the values subjected to the multiplication and addition processing and the values not subjected to such processing are output from the output port as address data of the waveform memory in an arbitrary combination. Therefore,
These outputs can be used as general-purpose address data when a waveform is generated by reading the peak value data by designating the address of the waveform memory. Therefore, by selecting these with the combination selector, any waveform data can be read from the waveform memory.
Further, a processing circuit for operating the read peak value data is also constituted by another one-chip circuit. In the one-chip circuit configured as the processing circuit, the waveform data is stored in the register, the operation of the counter is turned off, the selection is arbitrarily performed by the combination selector, and the arithmetic circuit performs an arbitrary multiplication and addition process. This makes it possible to freely process and process the waveform data itself. By using two one-chip circuits having the same configuration as described above, all waveform generation and waveform manipulation of the nuclear magnetic resonance inspection apparatus can be performed.

[0008]

Next, embodiments of the present invention will be described in detail with reference to the drawings. The entire nuclear magnetic resonance inspection apparatus according to the present invention is configured as shown in FIG. 2, and its magnetic field generator 11 and RF transmitter 1
2 includes a waveform generating circuit, which is configured as shown in FIG.

First, the whole configuration will be described. In FIG. 2, a nuclear magnetic resonance inspection apparatus includes a magnetic field generator 11 and
An RF transmitting device 12 and a receiving device 13 are provided. The magnetic field generator 11 generates a static magnetic field and a gradient magnetic field having a predetermined pulse waveform superimposed thereon. In order to generate a gradient magnetic field having a pulse waveform, the magnetic field generator 11 includes the waveform generating circuit shown in FIG. An object (not shown) is placed in the magnetic field. RF transmitter 12
Includes a waveform generation circuit shown in FIG. 1, amplitude-modulates a sine wave signal of a resonance frequency into a pulse waveform generated by the waveform generation circuit, irradiates the RF pulse to a subject, and emits the nuclear spin. To excite. The NMR signal generated from the excited subject is received by the receiving device 13. The sequence controller 14 controls the pulse waveform and generation timing of the gradient magnetic field, controls the frequency of the RF pulse carrier, the envelope waveform and the generation timing thereof, and further controls the reception device 13. The data obtained in the receiving device 13 is taken into the computer 15 and a process for image reconstruction is performed.

Next, the waveform generating circuit of FIG. 1 will be described. As shown in FIG. 1, the waveform generating circuit includes a plurality of independent registers 22. A general-purpose counter 23 is connected to each of the registers 22.
Each of these counters 23 counts a clock signal (not shown) with each output of the register 22 as an initial value, and sends the count value output to the combination selector 25. On / off of each of the counters 23 is controlled by a chip controller 31. The time interval for performing the counting operation is determined by the on / off control. Data are sent to the register 22 and the chip controller 31 from the sequence controller 14 (FIG. 2) via the input port 21. Further, a separate register 24 is provided, and data is sent to the register 24 via the input port 21, and data read from the register 24 is sent to the combination selector 25 without going through the counter.

Further, a multiplier 26 is provided in this waveform generating circuit.
, An adder 27, a register 28 for holding the output of the adder 27, a multiplexer 29 for sending the output of the register 28 to the adder 27, and an output port 30.

The combination selector 25 selects a plurality of inputs in an arbitrary combination and outputs the selected inputs. Here, four systems can be output as X, Y, X ', Y' outputs having different values. Two of the outputs X and Y are output from the multiplier 2
6 is multiplied and sent to the adder 27. The output of the adder 27 can be held in a register 28. By inputting the output to the adder 27 through a multiplexer 29, the output can be added as an offset value. That is, when performing such offset addition, first, "0" is selected by the multiplexer 29, "0" is added by the adder 27, and the output thereof is stored in the register 28.
Is stored as an offset value. Next, when an output is obtained from the multiplier 26, the
The value of 8 is selected and added to the output of the multiplier 26 in the adder 27.

The output of the adder 27 is output via an output port 30. Further, the X 'and Y' outputs of the combination selector 25 are output as they are (without performing arithmetic processing such as multiplication and addition) via the output port 30. Therefore, two outputs can be directly output via the output port 30.

The chip controller 31 has a register 2
2, 24, counter 23, combination selector 25, multiplier 26, adder 27, register 28, multiplexer 2
9 to control these. Then, an input port 21, a set of a plurality of pairs of registers 22, and a counter 23, a register 24, a combination selector 25, a multiplier 26, an adder 27, a register 28, a multiplexer 29, and an output port 30 And chip controller 3
1 is stored in one chip.

Here, since a plurality of sets of the register 22 and the counter 23 are provided, count values which count up from different initial values at different timings can be obtained. These are selected by the combination selector 25 and sequentially output from the output port 30 (for each count of the counter 23), and the output data is sent to a waveform memory (not shown) as address data. Thus, the peak value data stored at the corresponding address in the waveform memory can be sequentially read. In this case, it is assumed that time-series data of the peak value of each waveform is stored at each address in the waveform memory.
The time interval (timing) for reading the peak value data
Is set in the chip controller 31 from the sequence controller 14 (FIG. 2) via the input port 21 and the on / off control of the counter 23 is performed according to the sweep data, thereby generating the address data generation timing ( Time interval).

Therefore, the register 22 and the counter 23
Will function as a general-purpose address generator group. The output of the count value of each counter 23 can be output as it is from the output port 30 as address data. However, by performing arithmetic processing by the multiplier 26 and the adder 27, addition of an offset address and paging processing can also be performed. It is. And
As described above, since two-system address data can be directly output, it is possible to easily access a waveform memory constituted by a large-scale DRAM block.

The peak value data thus read out can be directly converted (without any processing) into an analog value, but can be further processed by using the circuit of FIG. That is, when processing the peak value data, the data is stored in the registers 22 and 24 via the input port 21. And this time, Counter 2
3 is controlled by the chip controller 31 so as not to operate, the data stored in the registers 22 and 24 are directly sent to the combination selector 25, and the outputs X and Y to the multiplier 26 are made valid and the multiplier 26 is made valid. I do. Thereby, the waveform data can be processed. Further, the adder 27 can add offset data to the output of the multiplier 26. The output of the register 24 is sent to the combination selector 25 without passing through the counter. However, by preparing such a system that does not pass through the counter, data transfer can be performed while avoiding the read / read cycle in the counter 23. .

According to the waveform generating circuit of FIG. 1, a general-purpose address generation for generating a waveform necessary for a nuclear magnetic resonance inspection apparatus and a processing of waveform data can be performed with a one-chip configuration. By using a plurality of these in combination, most of the waveform operations in the nuclear magnetic resonance inspection apparatus can be realized. In this way, since a simple circuit configuration composed of one chip is sufficient, the circuit configuration can be simplified.
The number of components can be reduced, the mounting area can be reduced, power consumption can be reduced, and reliability can be improved.

The above description relates to one example, and it goes without saying that various changes can be made without departing from the spirit of the present invention.

[0020]

As described above, according to the nuclear magnetic resonance inspection apparatus of the present invention, the waveform operation of the gradient magnetic field and the high frequency excitation signal is performed by using the one-chip waveform generating circuit and arbitrarily combining them. Can be performed, the circuit configuration can be simplified, the number of components can be reduced, the mounting area can be reduced, and power consumption can be reduced.
Improved reliability can also be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a waveform generation circuit of a nuclear magnetic resonance inspection apparatus according to the present invention.

FIG. 2 is a block diagram showing the overall configuration of the nuclear magnetic resonance inspection apparatus.

[Explanation of symbols]

Reference Signs List 11 magnetic field generator 12 RF transmitter 13 receiver 14 sequence controller 15 computer 21 input port 22, 24, 28 register 23 counter 25 combination selector 26 multiplier 27 adder 29 multiplexer 30 output port 31 chip controller

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) A61B 5/055

Claims (1)

(57) [Claims] 1. A means for generating a static magnetic field, a means for generating a gradient magnetic field so as to be superimposed on the static magnetic field, a means for transmitting a high-frequency excitation signal, a means for receiving a resonance signal, detecting the received signal, and Nuclear magnetic resonance comprising receiving means for obtaining data by D-conversion, means for processing the data to reconstruct an image, and sequence control means for controlling generation of a gradient magnetic field, transmission of a high-frequency excitation signal, and reception of a resonance signal. In the inspection apparatus, the waveform generating circuit that generates the waveform of the gradient magnetic field and the waveform of the high-frequency excitation signal includes an input port, a plurality of independent registers to which data is transmitted via the input port, and these registers. A plurality of counters connected to each register so as to form a pair, a combination selector for selecting an output of these counters in an arbitrary combination, and a combination selector An arithmetic circuit for performing a multiply-add process on an output, a chip controller for controlling the counter, combination selector and arithmetic circuit based on data input through the input port, and an output port stored in one chip In the one-chip circuit, the initial value of each counter is sent to each register from the sequence control means via an input port, and each counter is turned on / off by the chip controller. A time interval for performing a count operation by being controlled is determined, a count value that counts up at the determined time interval from the initial value is output, and each count value is selected in an arbitrary combination by a combination selector, An arbitrary combination of the value subjected to the multiplication and addition processing by the arithmetic circuit and the value not subjected to such processing is provided. In addition, by being configured to be output from the output port as the address data of the waveform memory, this one-chip circuit is configured as an address generation circuit of the waveform memory, and the other one-chip circuit is addressed and designated from the waveform memory. The read crest value data is stored in each register via the input port, and each crest value data stored in each register is sent to the combination selector via a counter controlled to be turned off by the chip controller, and in any combination. The one-chip circuit is configured as a waveform data processing circuit by being selected, multiplied and added by an arithmetic circuit, and output as processed waveform data from an output port. Nuclear magnetic resonance inspection equipment.