JP4350855B2 - Magnetic resonance imaging system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a magnetic resonance imaging apparatus, and more particularly to an eddy current correction circuit in a magnetic resonance imaging apparatus provided with an eddy current correction circuit for a gradient magnetic field coil.
[0002]
[Prior art]
In a magnetic resonance imaging (hereinafter referred to as “MRI”) apparatus that obtains a tomographic image of a subject using a nuclear magnetic resonance phenomenon, a gradient magnetic field is used to give positional information to a nuclear magnetic resonance signal. The gradient magnetic field is generated by driving a gradient magnetic field coil wound in the three axis directions of X, Y, and Z, and is controlled by a signal waveform applied to the gradient magnetic field coil.
[0003]
In the MRI system, the circuit that outputs the signal waveform output to the gradient coil uses three memories corresponding to the three gradient coils, and the eddy current is corrected using the signal waveforms temporarily stored in these memories. And a circuit for outputting a correction signal waveform. When photographing is performed while intermittently generating a gradient magnetic field, writing of new data (signal waveform) is repeated in each of the three memories each time a predetermined gradient magnetic field is generated. The stored contents of these three memories are initialized between the application of the gradient magnetic field and the next application of the gradient magnetic field. Initialization is performed by sequentially writing “0” to all addresses of each memory.
[0004]
[Problems to be solved by the invention]
However, the time required for such memory initialization may hinder the speeding up of processing. For example, if the number of addresses in each memory is n and it takes m hours to write to one address, there are three memories, so simply 3 × n × m hours are required for initialization. In this case, since it is necessary to provide a time for initialization between the measurements for at least 3 × n × m time or more, the entire processing is delayed by this amount.
[0005]
If the initialization process overlaps with the next gradient magnetic field generation timing due to such a delay in processing, a malfunction may occur and a normal image may not be acquired.
[0006]
Therefore, an object of the present invention is to initialize a plurality of memories at high speed and to increase the speed of the MRI apparatus.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the MRI apparatus of the present invention inputs a plurality of gradient magnetic field coils for applying a desired gradient magnetic field to a subject and a signal for driving the plurality of gradient magnetic field coils, and corrects the signal waveform. and a correcting means for, in using the nuclear magnetic resonance phenomenon magnetic resonance imaging apparatus for obtaining a tomographic image of a subject, wherein the correction means includes a plurality of memories for temporarily storing the signal waveform as digital data A memory control means for controlling writing of data to the plurality of memories; a switching means for switching between writing to each memory and writing to all memories by an output of the memory control means; and a signal stored in the memory Correction signal generation means for generating and outputting a correction waveform using the waveform;
It is provided with.
[0008]
According to such correction means, the memory control means performs control to simultaneously write data requested to be written to the plurality of memories when no gradient magnetic field is applied. Therefore, it is not necessary to sequentially write “0” for each memory for initialization, and all of a plurality of memories can be initialized in the time required for writing to a single memory. Processing speed can be increased. As a result, it is possible to prevent a malfunction due to the overlap between the initialization and the next generation of the gradient magnetic field and an image disturbance due to the malfunction.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the MRI apparatus of the present invention will be described.
[0010]
FIG. 1 shows the overall configuration of an MRI apparatus to which the present invention is applied.
[0011]
This MRI apparatus is an apparatus that obtains a tomographic image of the subject 1 using the nuclear magnetic resonance phenomenon, and as shown in the figure, a static magnetic field generating magnet 2, a gradient magnetic field generating system 3, a transmitting system 4, and a receiving device The system 5 includes a signal processing system 6, a sequencer 7, and a CPU (central processing unit) 8.
[0012]
The static magnetic field generating magnet 2 is a permanent magnet disposed in the space around the subject 1 or a normal or superconducting magnetic field generating source, and the body axis direction or body axis around the subject 1 A strong and uniform static magnetic field is generated in the orthogonal direction.
[0013]
The gradient magnetic field generation system 3 includes a gradient magnetic field coil 9 wound in the X, Y, and Z axial directions, an eddy current correction circuit 23, and a gradient magnetic field power source 10 that drives each gradient magnetic field coil 9. The eddy current correction circuit 23 controls the gradient magnetic field power supply 10 in accordance with the gradient magnetic field generation instruction signal sent from the sequencer 7 to obtain the gradient magnetic fields Gx, Gy, and Gz in the X, Y, and Z directions in the subject. Apply to 1. Here, the slice plane for the subject 1 is set depending on the method of applying the gradient magnetic field.
[0014]
The transmission system 4 includes a high-frequency oscillator 11, a modulator 12, a high-frequency amplifier 13, and a high-frequency coil 14 on the transmission side, and a high-frequency signal for causing nuclear magnetic resonance in atomic nuclei constituting the living tissue of the subject 1. Irradiate. That is, the high-frequency oscillator 11 outputs a high-frequency pulse, and the modulator 12 amplitude-modulates the high-frequency pulse in accordance with a command from the sequencer 7. The high-frequency amplifier 13 amplifies the amplitude-modulated high-frequency pulse and supplies the amplified high-frequency pulse to the high-frequency coil 14 disposed close to the subject 1. As a result, the high-frequency coil 14 generates electromagnetic waves and irradiates the subject 1.
[0015]
The receiving system 5 includes a high-frequency coil 15, an amplifier 16, a quadrature detector 17, and an A / D converter 18, and a high-frequency signal (NMR signal) emitted by nuclear magnetic resonance of the nucleus of the living tissue of the subject 1. Is detected. That is, the response electromagnetic wave (NMR signal) of the subject 1 with respect to the electromagnetic wave irradiated from the high-frequency coil 14 of the transmission side system 4 is detected by the high-frequency coil 15 disposed in the vicinity of the subject 1 and is orthogonal to the amplifier 16. The signal is input to the A / D converter l 8 via the phase detector 17, sampled by the A / D converter l 8, and converted into a digital quantity. Then, the digital quantity sampled by the A / D converter 18 is sent to the signal processing system 6 as collected data at a timing according to a command from the sequencer 7.
[0016]
The signal processing system 6 includes a CPU 8, a recording device such as a magnetic tape 20a and a magnetic disk 20b, a display 21 such as a CRT, and a keyboard 22. The CPU 8 performs processing such as Fourier transform, correction coefficient calculation, image reconstruction, etc. on the collected data sent from the A / D converter l 8 and obtains it by performing signal intensity distribution of an arbitrary cross section or appropriate calculation. The distribution is imaged and displayed on the display 21 as a tomographic image.
[0017]
The sequencer 7 operates under the control of the CPU 8 and issues commands to the transmission system 4 and the reception system 5 and performs gradients to the gradient magnetic field generation system 3 in order to execute an imaging sequence for collecting data on the subject 1. A magnetic field generation instruction signal is output.
[0018]
Hereinafter, details of the eddy current correction circuit 23 of the gradient magnetic field generation system 3 will be described.
[0019]
FIG. 2 shows the configuration of the eddy current correction circuit 23.
[0020]
As shown in the figure, the eddy current correction circuit 23 has a memory controller 24 and three systems of correction processing circuits 23a, 23b, and 23c of an X part, a Y part, and a Z part.
[0021]
The correction processing circuit 23a of the X section determines the drive amount of the gradient magnetic field coil 9 wound in the X-axis direction of the gradient magnetic field power supply 10 according to the gradient magnetic field generation instruction signal input from the sequencer 7 shown as X input in the figure. Outputs the specified drive control signal (X output). Similarly, the correction processing circuit 23b of the Y section is configured to supply the gradient magnetic field coil 9 wound in the Y-axis direction of the gradient magnetic field power supply 10 according to the gradient magnetic field generation instruction signal input from the sequencer 7 shown as Y input in the figure. A drive control signal (Y output) for designating the drive amount is output, and the correction processing circuit 23c of the Z section performs the gradient magnetic field power supply 10 according to the gradient magnetic field generation instruction signal input from the sequencer 7 shown as Z input in the figure. A drive control signal (Z output) for designating the drive amount of the gradient coil 9 wound in the Z-axis direction is output.
[0022]
The internal configuration of the three correction processing circuits 23a, 23b, and 23c of the X part, the Y part, and the Z part is the same, and as shown in FIG. 2 for the correction processing circuit 23a of the X part, the gradient magnetic field waveform control part 29, a memory 26, and a switch 30.
[0023]
The switching unit 30 selectively selects one of the gradient magnetic field waveform control unit 29 and the address bus, data bus, and control signal line group of the memory controller 24 according to the switching signal from the CPU 8, the address bus of the memory 26, Connect to data bus and control signal line group. Here, the control signal line group includes, for example, a chip select signal line for activating the memory 26, a write signal line for writing data to the memory 26, a read signal line for reading data from the memory 26, and the like. including.
[0024]
When the gradient magnetic field is generated, the switch 30 connects the address bus, data bus, and control signal line group of the gradient magnetic field waveform control unit 29 to the address bus, data bus, and control signal line group of the memory 26. The gradient magnetic field waveform control unit 29 performs the following operation using the memory 26.
[0025]
That is, in the correction processing circuit 23a of the X section, the gradient magnetic field waveform control section 29 receives a gradient magnetic field generation instruction signal (X input) having a signal waveform as shown in FIG. In order to correct the eddy current generated in the gradient coil 9 and perform optimum measurement while reading, the rise time (down) of the waveform of the gradient magnetic field generation instruction signal (X input) and the amount of overshoot are reduced. As shown in FIG. 3b, a signal having an adjusted signal waveform is generated and output as a drive control signal (X output).
[0026]
The same operation of the gradient magnetic field waveform control unit 29 is also performed in the correction processing circuit 23b of the Y part and the correction processing circuit 23c of the Z part.
[0027]
In such an MRI apparatus, the gradient magnetic field generation operation is repeatedly performed with or without moving the slice plane. And each time the gradient magnetic field generation is completed so that the next gradient magnetic field generation operation does not malfunction due to the contents written at the time of the previous gradient magnetic field generation in the three memories 26 of the correction processing circuits 23a, 23b, 23c, Until the next gradient magnetic field generation operation starts, each memory 26 is initialized by writing data “0” to all addresses of each memory 26.
[0028]
Hereinafter, initialization operations of the three memories 26 will be described. In the following, in order to distinguish the three memories 26 of the correction processing circuits 23a, 23b, and 23c, the memory 26 of the correction processing circuit 23a is the XM 26a, the memory 26 of the correction processing circuit 23a is the YM 26b, and the memory of the correction processing circuit 23c. 26 is shown as ZM26c.
[0029]
The initialization of XM26a, YM26b, and ZM26c is performed by the CPU 8 in accordance with the switching signal to the switching unit 30 of each correction processing circuit 23a, 23b, 23c, and the address bus, data bus, and control signal line group of the memory controller 24 are stored in the memory 26. This is done by writing “0” to all addresses of XM26a, YM26b, and ZM26c via the memory controller 24.
[0030]
Here, a memory map of XM26a, YM26b, and ZM26c for the CPU 8 is shown in FIG.
[0031]
As shown in the drawing, in this embodiment, four address ranges each having the same size as the address space of each of XM26a, YM26b, and ZM26c are assigned to XM26a, YM26b, and ZM26c.
[0032]
In the case of the figure, the second address range is a range assigned to XM26a, the third address range is a range assigned to YM26b, and the fourth address range is a range assigned to ZM26c. The first address range is a range commonly assigned to XM26a, YM26b, and ZM26c.
[0033]
The memory controller 24 controls the access of the CPU 8 to the XM 26a, YM 26b, and ZM 26c according to such a memory map. That is, the logical connection state shown in FIG. 5 formed by connecting the XM26a, YM26b, ZM26c and the address bus, data bus, and control signal line group of the memory controller 24 by the switching unit 30 now. When the address output by the CPU 8 is within the second address range, the memory controller 24 has enough control signals to write / read according to the CPU 8 write / read request only to the XM26a. Is output. Similarly, if the address output by CPU8 is within the third address range, only control signals to write / read according to the CPU8 write / read request are output to YM26b only. When the address output by the CPU 8 is within the fourth address range, a control signal sufficient for writing / reading according to the CPU 8 write / read request is output only to the ZM26c.
[0034]
On the other hand, if the address output by CPU8 is within the first address range, it is sufficient to write / read all XM26a, YM26b, and ZM26c according to the CPU8 write / read request. Output a control signal. In any case, the address output by the CPU 8 is output to all of the XM26a, YM26b, and ZM26c. Note that the data bus between the CPU 8 and the XM 26a, YM 26b, and ZM 26c is connected directly (through the switching unit 30) without going through the memory controller 24.
[0035]
More specifically, for example, assuming that each address space of XM26a, YM26b, ZM26c is expressed by a 4-bit address, the address range of 010000-011111 is a range assigned to XM26a, and the address range of 100000-101111 is The range assigned to YM26b, the address range of 110000-111111 is the range assigned to ZM26c, the address range 00000000-00111111 is the range assigned to XM26a, YM26b, ZM26c in common, and XM26a, When YM26b and ZM26c are memory elements activated by a chip select signal and controlled to be written / read by a write / read signal only in the activated state, the memory controller 24 outputs, for example, the CPU 8 While relaying the lower 4 bits of the address and the write / read signals to all XM26a, YM26b, and ZM26c, the upper 2 bits of the address output by the CPU 8 are decoded. When the upper 2 bits are 00, all XM26a, YM26b, ZM26c, when the upper 2 bits are 01, only XM26a, when the upper 2 bits is 10, only YM26b, when the upper 2 bits are 11, Asserts the chip select signal only to ZM26c.
[0036]
According to the memory map and operation of the memory controller 24 as described above, the CPU 8 writes to one address in the address range (the first address range in FIG. 4) that is commonly assigned to the XM26a, YM26b, and ZM26c. The data is written simultaneously to the corresponding addresses of all XM26a, YM26b, and ZM26c. Therefore, the CPU 8 can write “0” to all addresses of XM26a, YM26b, and ZM26c by writing “0” to all addresses within the address range commonly assigned to XM26a, YM26b, and ZM26c. That is, all addresses “0” of XM26a, YM26b, and ZM26c that constitute three times the address space can be written according to the number of write times and the write time for the number of addresses included in each address space of XM26a, YM26b, and ZM26c. become.
[0037]
In addition, according to the memory map and the operation of the memory controller 24 as described above, the CPU 8 assigns address ranges individually assigned to the XM26a, YM26b, and ZM26c as necessary (the second, third, and fourth addresses in FIG. 4). It is also possible to individually perform write / read access to each of XM26a, YM26b, and ZM26c using addresses in the address range.
[0038]
In the MRI apparatus as described above, initialization of XM26a, YM26b, and ZM26c is realized by the following operation of the CPU8.
[0039]
That is, as shown in FIG. 6, the CPU 8 operates the switching signal every time one gradient magnetic field generation operation is finished, and controls the memory controller 24 and the data bus, address bus, and control signal line group of the XM26a, YM26b, and ZM26c. Connect. Then, XM26a, YM26b, and ZM26c are simultaneously initialized at time T by writing “0” to all addresses within the address range commonly assigned to XM26a, YM26b, and ZM26c. Then, before the next gradient magnetic field generation operation starts, the switching signal is operated to connect the data bus gradient magnetic field waveform control unit 29 of XM26a, YM26b, and ZM26c to prepare for the next gradient magnetic field generation.
[0040]
Here, if the number of addresses of each of XM26a, YM26b, and ZM26c is n and it takes m hours to write to one address, simply the time T required for initialization in FIG. Thus, the time required for sequentially initializing each of XM26a, YM26b, and ZM26c is 1/3.
[0041]
As described above, according to this embodiment, “0” can be written in all addresses of a plurality of memories in the time required to write “0” to all addresses of one memory. Therefore, it becomes possible to initialize a plurality of memories at a higher speed.
[0042]
In the above embodiment, the memory controller 24 is described as a part of the eddy current correction circuit 23. However, the memory controller 24 is used for the CPU 8 to access a memory other than the XM26a, YM26b, and ZM26c. The memory controller used may be shared.
[0043]
In addition, the present embodiment has been described by taking an example of application to initialization of a plurality of memories used for generating a gradient magnetic field of an MRI apparatus, but the technique for simultaneously initializing the above-described plurality of memories may be an MRI apparatus or another The present invention can be similarly applied to initialization of a plurality of memories in a data processing apparatus.
[0044]
Further, the processing performed by the memory controller of the present invention is not limited to initialization, but can be applied to the case where the same contents are simultaneously written in a plurality of memories.
[0045]
【The invention's effect】
As described above, according to the MRI apparatus of the present invention, the memory control means for controlling the writing to the plurality of memories is provided, and the simultaneous writing to the plurality of memories is enabled, thereby enabling the high-speed initialization of the gradient magnetic field waveform. This enables high-speed switching of the gradient magnetic field and high-speed imaging. Further, malfunction during gradient magnetic field driving and accompanying image degradation can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of an MRI apparatus to which the present invention is applied.
FIG. 2 is a block diagram showing an embodiment of the eddy current correction circuit of the present invention.
FIG. 3 is a diagram showing input / output signal waveforms of a correction processing circuit according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating a memory map according to an embodiment of the present invention.
FIG. 5 is a diagram showing a logical connection relationship at the time of memory initialization according to an embodiment of the present invention.
FIG. 6 is a sequence diagram illustrating an initialization operation of a CPU according to an embodiment of the present invention.
[Explanation of symbols]
1 ... Subject
2. Static magnet generator
3. Gradient magnetic field generation system
4 ... Transmission system
5 ... Receiving system
6 ... Signal processing system
7 Sequencer
8 ... CPU (central processing unit)
9… Gradient magnetic field coil
10 ... Gradient magnetic field power supply
23 ... Eddy current correction circuit (correction means)
23a, 23b, 23c ... Correction processing circuit
24 ... Memory controller (memory control means)
29 ... Gradient magnetic field waveform controller (correction signal generation means)
26 ... Memory
30 ... Switch

Claims (1)

A plurality of gradient magnetic field coils for respectively applying gradient magnetic fields in the X-axis, Y-axis, and Z-axis directions to the subject; and a correction means for inputting signals for driving the plurality of gradient magnetic field coils and correcting the signal waveforms; A magnetic resonance imaging apparatus for obtaining a tomographic image of a subject using a nuclear magnetic resonance phenomenon,
Said correction means Bei example a memory for temporarily storing the signal waveform as digital data for each of said tilting swash magnetic field coil,
Memory control means for controlling writing of data to the plurality of memories;
Switching means for switching between writing to each memory and writing to all memories by the output of the memory control means;
In a magnetic resonance imaging apparatus, comprising: a correction signal generation means for generating and outputting a correction waveform using a signal waveform stored in the memory,
The magnetic resonance imaging apparatus, wherein the memory control means comprises means for writing 0 to all addresses of the plurality of memories.

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