JP3110147B2 - FDDI connection time monitoring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an FDDI (fibe
r distributed data interface) related to the FDDI connection time monitoring method used for networks, etc.
In particular, the present invention relates to an FDDI connection time monitoring system provided with a technique for confirming whether or not data can be sequentially transferred properly between adjacent stations when the power of the FDDI ring is turned on.

[0002]

2. Description of the Related Art A large number of stations are provided in an FDDI ring network of this kind. Even if each of these stations simply transfers data, the ring constituting the network must be properly established. This would be a wasteful transfer of data, and the network would be confused.

Therefore, conventionally, when the power of a FDDI station is turned on, the FDDI station establishes a ring by a handshake method using a line symbol other than data with an adjacent station, that is, a so-called FDD.
Adopts an I-connection management (hereinafter abbreviated as CMT) method, and allows mutual connection management between adjacent stations (PCM: Physical Connection Management).
= Physical connection management), and when the state of the receiving line (hereinafter referred to as line status) changes, the CPU is notified by an interrupt.

Accordingly, the CPU determines whether or not the change in the line status received by the interruption is in a predetermined state. If the change is appropriate, the line status is similarly changed using another line symbol. CP for each
U, and similarly determines whether the state change is appropriate.

When it is determined that the connection between the two adjacent stations is proper, a line symbol is successively transmitted between one of the two adjacent stations and another adjacent station. Then, similarly, it is determined whether or not the connection state is proper. When it is determined that the connection state is proper between all the stations in this way, a complete ring is established for the first time, and data transfer becomes possible.

[0006]

However, in the above-described method of establishing a ring, the CPU is notified by an interrupt every time the line status changes.
When the DI ring is in an unstable state, interrupts occur frequently due to frequent changes in the line status. Therefore, the CPU has to concentrate on interrupt processing. There is a problem that does not proceed smoothly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has been made in consideration of the above-mentioned problems. It is intended to provide a time monitoring method.

[0008]

According to a first aspect of the present invention, a plurality of stations are connected on an FDDI network, and two adjacent stations transmit both line symbols while sequentially transmitting line symbols. In an FDDI network that establishes lines between stations,

Each of the stations has a state machine that changes the state to the current line status when the current line status input from the partner station through the line is a prescribed line status, and a current predetermined state input through the line. measuring means for measuring the line status of the continuous reception time of the from the state transition before La <br/> in status which is the output of the current line status the state machine when has changed between the two line status state by sending a first latch signal when it is determined
The transition previous line status is held in the register, also exceeded the specified time continuous reception time of the current line status by said measuring means is determined from the connection management, and, provided that the line status is the state transition FDDI connection time monitoring system provided with a state transition judging means for transmitting the second latch signal and holding the current line status which has transitioned to the state in the register.

[0010]

According to the first aspect of the present invention, by taking the above means, the state transitions when the current line status coming from the line is a predetermined line status. When the current predetermined line status is a predetermined continuous reception time, the current line status that has undergone a state transition is stored in the storage means, so that the current state transition using the CPU or internal appropriate judgment means without interruption is performed. , And stable connection management can always be performed without imposing a load on the CPU even when the line is in an unstable state.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an overall block diagram for realizing the CMT function of each station connected to the FDDI ring.

[0012] 1 in the figure is a 5B / 4B decoder with the generate function of converting Surura in status to be the example 5-bit data received from the FDDI ring (symbols) in 4-bit data, the decoder
The current line status output from 1 is sent to the line status detection circuit 2. Although not directly related to the gist of the present invention, this decoder 1 converts, for example, 5-bit serial transmission frame data on the FDDI ring into 4-bit frame data after the ring is established, and, if necessary, For example, it has a function of converting it into 8-bit parallel frame data and outputting it to the A bus.

The line status detection circuit 2 detects only a line status necessary for connection management of an adjacent station, It has a function to measure time to determine whether MIN is satisfied. Where L
S The MIN means a previously required time length of a predetermined line status used in FDDI connection management. This length of time is determined by the time required to confirm the establishment of a reliable line between adjacent stations.

3 is a CPU bus interface,
This is to give a shift command, a register read, and the like sent from the external CPU 11 to the line status detection circuit 2.

Reference numeral 4 denotes a media access controller, which is a timed token passing protocol (timed token passing protocol) defined in the FDDI standard.
l) The function is to copy the frame data on the A bus and store it in the buffer memory 5 and send the frame data as it is on the B bus, or Although not transmitted, the transmission frame data of the lower LAN station connected to this station is fetched and output to the B bus. Reference numeral 6 denotes a 4B / 5B encoder which converts parallel frame data on the B bus into serial frame data and sends the serial frame data to the FDDI ring, and transmits line symbols in accordance with a command from the CPU.

FIG. 2 shows a line status detection circuit 2
FIG. 3 is a diagram showing a specific example of the configuration. In other words, this detection circuit 2 is a state machine 21 that makes a state transition in response only to a predetermined line status on the PCM.
And the current line status and the state machine 21
When it is determined that both line statuses have changed from the line status before the state transition, which is the output of, a latch signal for holding the line status before the state transition is output, and the line status changes. State determination means for outputting a latch signal for holding the current line status that has undergone state transition when a shift command is received from the CPU 11, and receiving a latch signal from the state transition determination means 22. And a register 23 for holding a state output of the state machine 21 when the time has elapsed, and for monitoring whether or not, for example, a later-described line status ILS of the current line status has exceeded a prescribed time length used in the PCM. LS that measures the continuous reception time of the line status A MIN measurement circuit 24 is provided.

FIG. 3 is a state transition diagram of the state machine 21 which changes according to the line status. As described above, the state machine 21 makes a state transition in response to only the line status determined on the PCM, but does not make a state transition to an unnecessary line status and is synchronized with the clock of the A bus. , The state transitions later than the change of the line status input to the L.L.
S). Here, MLS is MasterLine State
The contents of the register at this time are “010”, QLS is the abbreviation of Quiet Line State, the contents of the register at this time are “101”, and HLS is Halt Line St.
The content of the register at this time is “100” as an abbreviation of “ate”, and the content of the register at this time is “011” as an abbreviation of Idle Line State.

That is, the state machine 21 is currently operating at the line status L (ML) shown at the uppermost position in FIG.
S) When the line status ILS is input from the decoder 1 while being at “010”, L (ILS) “01” on the right side in the figure is displayed.
1 and the L (ILS) “01” on the right side of the figure.
1), and when the line status MLS is input from the decoder 1, L (MLS) “010” at the uppermost position in the drawing
State transition. Hereinafter, a state transition is made on condition that the illustrated line status is input. Next, the operation of the line status detection circuit in the above configuration will be described.

In the PCM, it is specified that a line between the adjacent stations passes through six states of PC0 to PC5 in order to establish a line. PC3 to do
-PC4 will be described.

Therefore, in the state machine 21, when the line status shown in FIG. 3 is input, the state transition is performed. At this time, the state transition determining means 22 determines whether the current line status directly from the decoder 1 is the same as the state machine 21.
Is compared with the previous line status, which is the output of, so that it can be easily determined whether both line statuses have changed. Therefore, when the state transition determining means 22 determines that both line statuses have changed, it sends a latch signal to the register 23 to hold the previous line status already output from the state machine 21.

On the other hand, LS In the MIN measuring circuit 24, for example, when a predetermined line status ILS is input from the line, a timer operates and measures the continuous reception time of the status.

In this state, the CPU 11 reads the continuous time of reception of the current status from the measurement circuit 24, and a condition that the time exceeds a predetermined time set on the PCM and that the content of the register 23 differs from the current line status. The shift command is sent to the state transition determining means 22. Therefore, upon receiving the shift command, the state transition determining means 22 sends a latch signal to the register 23 again, and holds the current line status whose state has been transitioned by the state machine 21.

That is, in this time monitoring method, when the line status becomes ILS, LS The MIN measuring circuit 24 starts a timer, and the CPU 11 reads out the timer time and When the value of MIN is satisfied, the current line status that has undergone a state transition is held in the register 23, and the process proceeds to the next action.

Therefore, in the conventional case, for example, the line status of the adjacent station is set to MLS-ILS-M in a short time.
When the state transitions to LS, after detecting the MLS, the ILS may not be detected if the MLS is detected after the state of the ILS. However, in the present invention, the reception time of a predetermined line status is monitored and the LS is monitored. When the MIN is satisfied, the current line status that has undergone the state transition is retained, so that the next line state transition is determined under the initiative of the CPU, for example, without being notified by an interrupt every time the line state changes. Can move to action.

In the above embodiment, the description has been given of the case where the bus width is 3 bits or 8 bits. However, the bus width is not limited to these bits. Further, the CPU 11 reads out the continuous reception time and the readout time is LS. It is determined whether or not the MIN is satisfied, and the shift command is output. However, if a circuit for comparing the predetermined time signal with the continuous reception measurement time is used, the determination can be easily performed without the CPU 11. A shift instruction can be output. In addition, the present invention can be implemented with various modifications without departing from the scope of the invention.

[0026]

As described above, according to the present invention, F
It is possible to provide an FDDI connection time monitoring method capable of performing ring establishment work without imposing a large burden on the CPU even when the DDI ring is in an unstable state.

[Brief description of the drawings]

FIG. 1 is a hardware configuration diagram of each station connected to an FDDI ring.

FIG. 2 is a diagram showing a specific configuration of the line status detection circuit of FIG. 1 to which the FDDI connection time monitoring method according to the present invention is applied.

FIG. 3 is a state transition diagram of the state machine of FIG. 2;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Decoder, 2 ... Line status detection circuit, 4 ... Media access controller, 6 ... Encoder, 11 ...
CPU, 21 state machine, 22 state transition determining means, 23 register, 24 LS MIN measurement circuit.

Continuation of the front page (56) References JP-A-3-178239 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/437

Claims (1)

(57) [Claims] 1. In a FDDI network in which a plurality of stations are connected on an FDDI network and two adjacent stations establish a line between the two stations while sequentially transmitting line symbols, each station is a partner station. a state machine current line status input through line state transition to the current line status when a defined line status from measured continuous reception time of the current predetermined line status input through the line measuring means for said sending the first latch signal when it is determined that the change between the two line states and a state transition previous line status, which is the output of the current line status said state machine state transition Regis the previous line status Is held, also continuous reception time of the current line <br/> down status due to the measuring means from the connection management in
State transition judging means for sending a second latch signal on condition that the state transition of the line status exceeds a prescribed time period and retaining the current line status of the state transition in the register. FDDI connection time monitoring method.