JP3107091B2 - Digital broadcast signal receiving apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital broadcast signal receiving apparatus and method, and more particularly to a frame in which a main signal is transmitted in a payload portion of a transport packet (TS packet) and formed by a predetermined number of transport packets. The present invention relates to a digital broadcast signal receiving apparatus and method for receiving a digital broadcast signal transmitted by replacing at least a part of a synchronization unit of a transport packet in the digital broadcast signal with a frame synchronization signal.

[0002]

2. Description of the Related Art Digital multi-channel broadcasting using a communication satellite (hereinafter abbreviated as CS) has begun in earnest, and various services have been started. In the future, it is considered that a broadcasting satellite (hereinafter abbreviated as BS) will provide a digital broadcasting service.

[0003] Since the power of the BS is larger than that of the CS, it has been studied to use a modulation scheme having higher transmission efficiency than the QPSK modulation scheme used in the CS.
In addition, the bit stream to be transmitted is MPEG2 from the viewpoint of compatibility with other media such as CS, terrestrial broadcasting, and cable.
It has been proposed to be based on a so-called transport stream (hereinafter abbreviated as TS) defined by Systems. This TS is composed of a 188-byte TS packet including a 1-byte synchronization byte.
In S digital multi-channel broadcasting, terrestrial digital broadcasting, cable digital broadcasting, etc.
Since a Reed-Solomon code (hereinafter abbreviated as an RS code) to which a 6-byte parity is added is used,
Even in S digital broadcasting, TS (RS, 204, 18)
It has been proposed to perform the coding of 8).

In this BS digital broadcasting, RS (20
4,188), a convolution-encoded BPSK (Binary Phase Shift Keying) signal, a QPSK (Quadrature Phase Shift Keying) signal, Alternatively, trellis-coded 8PSK (Phase Shift Keying) (hereinafter abbreviated as TC (Trellis-Coded) 8PSK) is used, and transmission information such as a modulation method and a coding rate is transmitted by BPSK using a TS packet synchronization unit. Transmission schemes have been proposed.

In particular, when a so-called pragmatic TC8PSK is used as the TC8PSK, an encoding circuit and a decoding circuit similar to the conventional convolutional code can be used. In the case of demodulation by a device, the same Viterbi decoder can be used when demodulating any signal, which is advantageous in terms of hardware configuration.

FIG. 1 shows such a currently proposed B
1 illustrates a configuration example of an S digital broadcast transmitting apparatus. 18
For an 8-byte TS packet, RS (204, 188)
The encoding adds a parity of 16 bytes. Forty-eight packets are collected to form one frame.

The first 1 of 48 packets in each frame
The byte synchronization bytes are sequentially and successively read and input to the frame synchronization and TMCC generation circuit 81. The frame synchronization and TMCC generation circuit 81
Replaces the sync byte of the packet with a frame sync signal. Further, the frame synchronization and TMCC generation circuit 81 converts the synchronization bytes of the third and subsequent TS packets into TMCC (Transm
ission Multiplexing Configuration Control) signal. The TMCC signal includes transmission control information such as a modulation method and a coding rate of a main signal described later. As a result, two synchronization bytes of the first two packets of the 48 packets constituting one frame are switched to the frame synchronization signal, and the synchronization bytes of the third and subsequent packets are switched to the TMCC signal. Will be done. The frame synchronization signal and the TMCC signal generated by the frame synchronization and TMCC generation circuit 81 are input to a BPSK mapping circuit 82 and are mapped to predetermined signal points.

The main signal of the first two TS packets in one frame is the image signal LQ for the lower hierarchy, and this signal is interleaved by the interleave circuit 83 within the range of the two TS packets. Is further input to a convolutional encoding circuit 84, which performs convolutional encoding at a coding rate of 1/2. Then, the convolutionally coded signal is subjected to a puncturing process to have a coding rate of 3/4 and QPSK
It is supplied to a mapping circuit 85. In the QPSK mapping circuit 85, the signal is mapped to a predetermined signal point by the QPSK method.

On the other hand, the main signal of the remaining 46 TS packets out of the 48 packets constituting one frame is:
An image signal HQ for a high hierarchy is input to an interleave circuit 86, and after being interleaved,
3 trellis encoding circuit 87 encodes
In the 8PSK mapping circuit 88, it is mapped to a signal point. In the 2/3 trellis encoding circuit 87,
If so-called pragmatic trellis coding is performed, the convolutional coding circuit 84 and the 2/3 trellis coding circuit 87 can be a common circuit.

The multiplexing circuit 89 includes a BPSK mapping circuit 8
2. The outputs of the QPSK mapping circuit 85 and the 8PSK mapping circuit 88 are multiplexed in frame units and output.
Therefore, the signal of each frame output from the multiplexing circuit 89 is firstly a frame synchronizing signal modulated by BPSK.
The format is such that a TMCC signal is arranged, a QPSK-modulated main signal LQ for a lower layer is arranged, and finally a 8PSK-modulated main signal HQ for a higher layer is arranged.

On the receiving side, after establishing the synchronization of the carrier and the clock, the received signal sequence is monitored to detect the BPSK-modulated frame synchronization signal, and establish the frame synchronization.
This frame synchronization signal is followed by a BPSK-modulated TMCC, so if frame synchronization is established, the next signal of the frame synchronization signal is received and demodulated as a BPSK signal.
CC signal can be obtained. By interpreting the contents of the TMCC signal, transmission control information such as a modulation scheme and a coding rate of a symbol of a main signal portion for transmitting payload information transmitted after the TMCC signal can be known. , The main signal can be received and the inner code can be decoded.

Then, the frame synchronization signal in the demodulated signal and the
The TMCC signal is replaced by a TS synchronization signal as before, and is returned to an RS (204, 188) -encoded TS including a 1-byte synchronization signal and a 203-byte main signal. Can be transmitted to obtain the transmitted TS.

FIG. 2 shows an example of such a synchronization process. First, in step S1, the process waits until the first frame synchronization signal is detected, and when it is detected, it is determined in step S2 whether the second frame synchronization signal is detected. If the second frame synchronization signal has been detected, the process proceeds to step S3, and it is determined whether the third frame synchronization signal has been detected. If the third frame synchronization signal has been detected, the process proceeds to step S4, and it is determined whether the fourth frame synchronization signal has been detected. As described above, when the frame synchronization signal is continuously detected for the four frames, the frame synchronization establishment processing is executed in step S5 assuming that the frame synchronization has been established.

After the first frame synchronization signal is detected, if it is determined in step S2 that the second frame synchronization signal has not been detected, the process proceeds to step S6, where the third frame synchronization signal is detected. It is determined whether a signal has been detected. If it is determined that the third frame synchronization signal has been detected, the process proceeds to step S7, and it is determined whether the fourth frame synchronization signal has been detected. If the fourth frame synchronization signal has been detected, the process proceeds to step S8, and it is determined whether the fifth frame synchronization signal has been detected. As described above, even if the second frame synchronization signal is not detected after the first frame synchronization signal is detected, if the frame synchronization signal is continuously detected three times thereafter, Proceeds to step S5, where frame synchronization establishment processing is executed.

If it is determined in step S6 that the frame synchronization signal has not been detected twice consecutively after the detection of the first frame synchronization signal, the flow returns to step S1 and the subsequent processing is repeated. Be executed.

After the first frame synchronization signal is detected, the second frame synchronization signal cannot be detected, but the third frame synchronization signal can be detected. If it is determined in step S7 that the fourth frame synchronization signal has not been detected, the process proceeds to step S9, and it is determined whether the fifth frame synchronization signal has been detected. Therefore, when it is determined that the fifth frame synchronization signal has been detected, the process further proceeds to step S10, and it is determined whether the sixth frame synchronization signal has been detected.
Here, when it is determined that the sixth frame synchronization signal has been detected, the process proceeds to step S5, and a frame synchronization establishment process is performed. Step S9 or Step S
If it is determined in step 10 that the frame synchronization signal has not been detected, the process returns to step S1, and the subsequent processing is repeatedly executed.

If it is determined in step S3 that the third frame synchronization signal has not been detected after it has been determined that the frame synchronization signal has been detected twice consecutively, then step S7 is performed. And the subsequent processing is executed. After the frame synchronization signal can be detected three times in a row, if it is determined in step S4 that the fourth frame synchronization signal cannot be detected, the process proceeds to step S8. Is performed.

If it is determined in step S8 that the fifth frame synchronization signal has not been detected,
Proceeding to step S10, the subsequent processing is executed.

As described above, in a state where the frame synchronization has been established, with reference to this frame synchronization signal,
The TMCC signal and the main signal can be accurately demodulated.

The processing up to the establishment of the frame synchronization is called backward protection.

When it is determined that frame synchronization has been established by the backward protection described above, it is confirmed in step S11 that the frame synchronization signal has been continuously detected, and in step S11, a predetermined frame has been detected. If it is determined that the frame synchronization signal (assumed to be n-th) cannot be detected, the process proceeds to step S
Proceeding to 12, it is determined whether the (n + 1) th frame synchronization signal has been detected. Step S12
In step S13, if it is determined that the (n + 1) th frame synchronization signal cannot be detected, it is further determined in step S13 whether the (n + 2) th frame synchronization signal has been detected. If not, in step S14, (n + 3)
It is determined whether or not the frame synchronization signal is detected. As described above, when it is determined that the frame synchronization signal cannot be detected for four consecutive frames, the process proceeds to step S15, and it is determined that the frame synchronization has been lost, and the out-of-synchronization processing is executed. Thereafter, the process returns to step S1, and the subsequent processing is executed.

After it is determined that the nth frame synchronization signal has not been detected, in step S12, (n +
If it is determined that the 1) th frame synchronization signal has been detected, the process proceeds to step S16, and it is determined whether the (n + 2) th frame synchronization signal has been detected. (N
When the (+2) th frame synchronization signal is detected,
Since the frame synchronization signal cannot be detected only for one frame, step S11 is performed.
And the subsequent processing is executed.

If it is determined in step S16 that the (n + 2) th frame synchronization signal could not be detected, it is determined in step S17 whether the (n + 3) th frame synchronization signal has been detected. . If it is determined that the (n + 3) th frame synchronization signal has not been detected, in step S18,
It is determined whether the (n + 4) th frame synchronization signal has been detected. If it is determined that the (n + 4) th frame synchronization signal has not been detected, it means that the frame synchronization signal could not be detected three times in a row, so the process proceeds to step S15, and the out-of-sync processing is performed. Be executed.

If it is determined in step S17 that the (n + 3) th frame synchronization signal has been detected, it is determined in step S19 whether the (n + 4) th frame synchronization signal has been detected. (N +
If the 4) th frame synchronization signal cannot be detected, the process proceeds to step S20, and it is determined whether the (n + 5) th frame synchronization signal has been detected.
If it is determined that the (n + 5) th frame synchronization signal could not be detected, the process proceeds to step S15, and the out-of-synchronization processing is performed.

If it is determined in step S19 or S20 that a frame synchronization signal has been detected, the process returns to step S11.

After the frame synchronization signal cannot be detected twice consecutively, in step S13, (n
If it is determined that the (+2) th frame synchronization signal has been detected, the process proceeds to step S17, and the subsequent processes are executed. After it is determined that the frame synchronization signal cannot be detected three times in a row, if it is determined in step S14 that the (n + 3) th frame synchronization signal has been detected, the process proceeds to step S18. Then, the subsequent processing is executed.

If it is determined in step S18 that the (n + 4) th frame synchronization signal has been detected, the process proceeds to step S20, and the subsequent processing is executed.

The protection operation after the frame synchronization is established until the detection of the loss of the frame synchronization is referred to as forward protection.

[0029]

As described above, 188
The byte TS packet is subjected to RS (204, 188) encoding, and convolutional encoding or trellis encoding is performed as an inner code, so that error correction for a transmission path error can be performed. . On the other hand, the TMCC signal
In order to transmit the transmission control information to the receiving side, resistance to transmission path errors is required more than the main signal. In the above proposed scheme, this demand is met by using BPSK, which is the most advantageous modulation scheme for transmission line errors, among various modulation schemes.

However, BPSK modulation alone cannot provide sufficient error resilience, and a stronger error correction process is required for TMCC signals.

Further, no countermeasures are taken against error correction for the frame synchronization signal, and the receiver only performs synchronization protection processing by the state machine circuit as described with reference to FIG. .

Therefore, there is a problem that it is difficult to detect a frame synchronization signal stably and at high speed especially in a state where the C / N is low.

The present invention has been made in view of such a situation, and it is an object of the present invention to improve the robustness of a frame synchronization signal against a transmission line error and to detect a frame synchronization signal stably and at high speed. It is an object of the present invention to provide a digital broadcast signal receiving apparatus and method capable of performing the following.

[0034]

According to the digital broadcast signal receiving apparatus and method of the present invention, a main signal is transmitted in a payload section of a transport packet, a frame is formed by a predetermined number of transport packets, and the At least a part of the synchronization unit of the transport packet is replaced with a control signal related to the transmission system and n-bit first and second synchronization signals transmitted before and after the control signal, and the second synchronization The signal has bit patterns different from each other between the first frame of a superframe composed of a plurality of frames and another frame, and the constraint length is m (n> m).
By applying convolutional coding at a coding rate of 1/2 to the control signal and the first and second synchronization signals,
When receiving a digital broadcast signal transmitted as 2n-bit first and second coded bits, the second synchronizing signal receives the first and second coded bits of the received 2n-bit coded bits. By detecting at least one of the predetermined unique bit patterns among the bits, frame synchronization is detected, and a bit sequence of the received 2n-bit second coded bits is detected to form a plurality of frames. The above-mentioned problem is solved by identifying the head frame of a super frame to be demodulated and performing demodulation according to the output signal of the frame synchronization detecting step.

The signal obtained by demodulation is Viterbi-decoded, and it is determined whether or not frame synchronization is established based on the first or second synchronization signal obtained from the Viterbi-decoded output. No.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a digital broadcast signal receiving apparatus and method according to the present invention will be described.
This will be described with reference to the drawings.

FIG. 3 shows a configuration example of a digital broadcast signal transmitting apparatus for transmitting a digital broadcast signal to a digital broadcast signal receiving side to which the present invention is applied. In memory 1,
A TMCC signal including transmission control information is stored. The synchronization register 2 stores a frame synchronization signal. The multiplexing circuit 3 outputs a frame synchronization signal or a TMCC
The signals are read, multiplexed, and output to the Reed-Solomon encoding circuit 4.

The Reed-Solomon encoding circuit 4 converts the frame synchronization signal and the TMCC signal input from the
(48, 38) encoded and output to the interleave circuit 5. The interleave circuit 5 interleaves the signal input from the Reed-Solomon encoding circuit 4 and outputs the signal to the multiplexing circuit 9. The interleave circuit 5 disperses errors in the convolutional coding circuit 10 at the subsequent stage, and performs RS decoding on the receiving side to improve error correction capability.

On the other hand, TSs including the main signals of the low-layer image signal LQ and the high-layer image signal HQ are input to Reed-Solomon encoding circuits 6 and 13, respectively. In the Reed-Solomon encoding circuits 6 and 13, the TS is subjected to Reed-Solomon encoding, output to the memories 7 and 14, respectively, and stored. At this time, the memory 7,
No. 14 is not written with the TS synchronization byte. The TS read from the memories 7 and 14 is
After being subjected to interleaving processing by the interleaving circuits 8 and 15, respectively, the signals are input to the multiplexing circuit 9.

The multiplexing circuit 9 multiplexes the frame synchronization signal and the TMCC signal input from the interleaving circuit 5 with the main signals input from the interleaving circuits 8 and 15 so as to form a frame, and outputs the multiplexed signal. It has been done.
As for the frame structure, the frame synchronization signal and the TMCC signal are arranged first, the main signal LQ for the lower hierarchy is arranged next, and the main signal HQ for the higher hierarchy is arranged last. You.

The convolutional encoding circuit 10 performs a convolutional encoding process suitable for each signal in the frame supplied from the multiplexing circuit 9 and outputs the result to the mapping circuit 11 as described later. The mapping circuit 11 converts the multiplexed signal supplied from the convolutional encoding circuit 10 into BPSK modulation, QPSK
A process of mapping to a signal point of modulation or a modulation method such as 8PSK modulation is performed.

FIGS. 4 to 6 show how signal points are mapped. FIG. 4 shows the case of the BPSK modulation scheme.
Shows the signal points of the mapping in the case of the QPSK modulation method, and FIG. 6 shows the signal points of the mapping in the case of the 8PSK modulation method. As shown in FIG. 4, in the case of the BPSK modulation scheme, mapping is performed on two signal points having a phase difference of 180 degrees. In the case of the QPSK modulation method, as shown in FIG. 5, mapping is performed on four signal points each having a phase difference of 90 degrees. Also,
In the case of the 8PSK modulation method, as shown in FIG.
The mapping is performed on eight signal points having a phase difference of degrees.

The controller 12 controls the operations of the multiplexing circuit 3, multiplexing circuit 9, convolutional coding circuit 10, and mapping circuit 11.

Next, the operation will be described. As shown in FIG. 7, the signals input to the Reed-Solomon encoding circuits 6 and 13 are TS packets in which the first byte is used as a synchronization signal and the following 187 bytes are composed of image data. This image data is the image data L for the lower hierarchy.
Q or high-level image data HQ. The low hierarchy image data LQ is image data necessary for reproducing a minimum low quality image, and the high hierarchy image data HQ is required for reproducing a higher resolution image. Image data. The Reed-Solomon encoding circuit 6 is supplied with two layers of image data LQ for one frame, and the Reed-Solomon encoding circuit 13 is supplied with 46 packets of image data for high hierarchy for one frame. HQ is supplied.

The Reed-Solomon encoding circuits 6 and 13 perform an RS (204, 188) encoding process on each packet, add a 16-byte parity, supply them to the memories 7 and 14, and store them. Let it. However, at this time, the 1-byte synchronization signal of each packet is not written in the memories 7 and 14. The image signals written in the memories 7 and 14 are read out by the interleave circuits 8 and 15, subjected to a predetermined interleave process, and supplied to the multiplexing circuit 9.

On the other hand, the memory 1 contains transmission control information.
A TMCC signal is provided and stored. The multiplexing circuit 3 reads out the frame synchronization signal stored in the synchronization register 2 and the TMCC signal stored in the memory 1 at a predetermined timing under the control of the controller 12, multiplexes and reads out the frame synchronization signal. Output to the Solomon encoding circuit 4. The multiplexing circuit 3 reads the 2-byte frame synchronization signal, reads a 10-byte TMCC signal from the memory 1, and outputs the TMCC signal to the Reed-Solomon encoding circuit 4 after reading the 2-byte frame synchronization signal. The process is repeatedly executed for each frame. That is, in this configuration example, a 2-byte frame synchronization signal and a 10-byte TMCC signal are transmitted in one frame. The Reed-Solomon encoding circuit 4 outputs RS (48,
38), a parity for one frame is added to the data for three frames supplied from the multiplexing circuit 3.

By the way, in the case of the configuration example of FIG. 1 described above,
BPSK of 192 symbols (192 bits) per frame
Symbols are assigned to the frame synchronization signal and the TMCC signal. That is, the number of symbols per frame at the output stage of the BPSK mapping circuit 82 in FIG. 1 is 192 symbols. The number of symbols per frame allocated to the frame synchronization signal and the TMCC signal does not change even when the present invention is implemented. That is, in the convolutional encoding circuit 10, the frame synchronization signal and the TM
Since the convolutional coding process with a coding rate of 1/2 is performed on both of the CC signals, the amount of information that can be allocated to the frame synchronization signal and the TMCC signal per frame before performing the convolutional coding process is as follows. , 96 (= 192/2) bits, that is, 12 bytes (more specifically, the frame synchronization signal is 2 bytes and the TMCC signal is 10 bytes as described above). The Reed-Solomon encoding circuit 4 adds a parity for one frame to the data for three frames supplied from the multiplexing circuit 3, and a total of four frames of data (48
Byte data) is used to form a Reed-Solomon code.

That is, a signal consisting of a 2-byte frame synchronization signal and a 10-byte TMCC signal per frame is
Frames (36 bytes) are collected, and a 2-byte frame synchronization signal of the fourth frame is added to the collected data.
A parity of 10 bytes is added to information of (= 36 + 2) bytes, and RS (48, 38) is encoded.
Thus, the output of the Reed-Solomon encoding circuit 4 is as shown in FIG. As a result, a TMCC signal of 30 bytes (240 bits) can be transmitted in four frames.

In this configuration example, Reed-Solomon coding is performed on both the frame synchronization signal and the TMCC signal. However, Reed-Solomon coding may be performed only on the TMCC signal. . In this case, RS (4
(0, 30) encoding.

The interleave circuit 5 performs a predetermined interleave process on the signal ((A) in FIG. 8) supplied from the Reed-Solomon encoding circuit 4 and outputs it to the multiplexing circuit 9. As shown in FIG. 8B, this signal does not change the position of the 2-byte synchronization signal, but is a signal in which the TMCC signal and parity are interleaved at a predetermined position.

FIG. 9 shows a configuration example of the interleave circuit 5. The interleave circuit 5 is a convolution type. In this configuration example, an input signal is input to one of the contacts 31-1 to 31-6 by the switch 31, and is output from the contacts 32-1 to 32-6. , Switch 3
2 is output. Contact 31-
1 and 32-1 are directly connected, and contact 31-2 and contact 3
The delay unit 33-1 is inserted between 2-2. Delay units 33-2 and 33-3 are inserted between the contacts 31-3 and 32-3, and the delay units 33-4 to 33-6 are provided between the contacts 31-4 and 32-4.
Is inserted between the contacts 31-5 and 32-5, and delay units 33-7 to 33-10 are inserted between the contacts 31-5 and 32-5.
1-6 and a contact 32-6, a delay unit 33-1
1 to 33-15 are inserted. Each delay unit is configured to give a delay of 8 bytes.

The switches 31 and 32 are
The contacts are switched in synchronization with each other every two bytes.

At the timing when a 2-byte frame synchronization signal is input from the Reed-Solomon encoding circuit 4,
The switches 31 and 32 are connected to the uppermost contact 3 in FIG.
1-1 and 32-1. Therefore, the frame synchronization signal is output as it is without delay (without interleaving).

On the other hand, 1 following the frame synchronization signal
When a 0-byte TMCC signal is input, the switch 31,
Reference numeral 32 in FIG. 9 is sequentially switched to the second to lowest contacts from the top every two bytes. as a result,
Of the 10-byte TMCC signal, the first two-byte signal is delayed by one delay unit (eight bytes),
The second 2-byte TMCC signal is delayed by two delay units (16 bytes). Similarly, the third to fifth TMCC signals of 2 bytes are respectively 3 delay units (24 bytes), 4 delay units (32 bytes),
Alternatively, it is output with a delay of 5 (40 bytes).

The frame synchronization signal is supplied to the interleave circuit 5
It is necessary to prevent the position from being changed by the interleave processing. When the interleave circuit 5 is a convolutional interleave circuit, not only is it easy to save the position of the synchronization signal, but also the circuit scale can be reduced as compared with the case where a block type interleave circuit is used.

Switches 31 and 32 of interleave circuit 5
Is switched in units of bytes, it is possible to more efficiently disperse burst errors. However, doing so increases the hardware. Therefore, in order to perform interleaving with smaller hardware without changing the position of the synchronization signal, it is preferable to perform interleaving in units of 2 bytes.

The multiplexing circuit 9 is for one frame (48 packets) supplied from the interleaving circuits 8 and 15.
At the beginning of the main signal of FIG. 1, the frame synchronization signal for one frame supplied from the interleave circuit 5 and the TMCC signal are shown in FIG.
The signal is multiplexed as shown in FIG.

Under the control of the controller 12, when a frame synchronization signal or a TMCC signal is input from the multiplexing circuit 9, the convolutional coding circuit 10 converts the signal into a coding rate of 1/2.
BPSK, convolutional coding processing at a coding rate of 1/2 is performed. When the main signal supplied from the multiplexing circuit 9 is an image signal HQ for a higher hierarchy, the convolutional coding circuit 10 trellis-codes the main signal at a coding rate of 2/3. In this case, when transmitting with the Pragmatic TC8PSK, the input from the multiplexing circuit 9 is converted into two bits in parallel, one bit of which is left as it is, and the other one bit is a convolutional code at a coding rate of 1/2. To obtain a 2-bit code. Then, the outputs of a total of 3 bits are output in parallel to the mapping circuit 11.

When the main signal is an image signal LQ for a low hierarchy, the convolutional encoding circuit 10 performs a convolutional encoding process at an encoding rate of 1/2 in order to transmit the image signal LQ at a coding rate of 3/4 QPSK. After that, the coding rate is changed to 3/4 by puncturing processing, and the data is output to the mapping circuit 11.

FIG. 11 shows an example of the configuration of the convolutional encoding circuit 10 when the frame synchronization signal and the TMCC signal are convolutionally encoded. In this configuration example, the shift registers 61 to 66 sequentially output the data input from the multiplexing circuit 9 to the subsequent stage. The exclusive OR circuit 67 calculates the exclusive OR of the input and the output to the shift register 61, and the exclusive OR circuit 68 excludes the output of the exclusive OR circuit 67 and the output of the shift register 62. The exclusive OR circuit 69 calculates the exclusive OR of the output of the exclusive OR circuit 68 and the output of the shift register 63. The exclusive OR circuit 70 outputs the output of the exclusive OR circuit 69,
The exclusive OR of the output of the shift register 66 is calculated and output.

The exclusive OR circuit 71 calculates the exclusive OR of the input to the shift register 61 and the output of the shift register 62, and the exclusive OR circuit 72 calculates the exclusive OR of the output of the exclusive OR circuit 71. , The exclusive OR circuit 73 calculates the exclusive OR of the output of the shift register 63, and the exclusive OR circuit 73 calculates the exclusive OR of the output of the exclusive OR circuit 72 and the output of the shift register 65. Logical OR circuit 74
An exclusive OR of the output of the exclusive OR circuit 73 and the output of the shift register 66 is calculated.

In this convolutional encoding circuit 10,
When the input data is sequentially transferred one bit at a time to the subsequent stage by the shift registers 61 to 66, the exclusive OR circuits 67 to 74 calculate the exclusive OR at each timing. As a result, two-bit data is output from the exclusive OR circuit 70 and the exclusive OR circuit 74 for one input bit (the coding rate 1 /
2).

Assuming that the frame synchronization signal is composed of 16 bits, when the first 6 bits of the 16 bits are held in the shift registers 61 to 66, the exclusive OR circuit 67 , 71 have the seventh
Since the data of the bit is input, the frame synchronization signal is unique data and is not data that changes arbitrarily. At this time, the data output from the exclusive OR circuits 70 and 74 are unique. Is determined. The data output from the exclusive OR circuits 70 and 74 are uniquely determined because the shift registers 61 to 66 store the seventh to last second to last bits of the 16-bit frame synchronization signal. Is held until the last bit is input to the exclusive OR circuits 67 and 71.

In the mapping circuit 11, the controller 1
In the case of performing BPSK modulation under the control of 2 (when the input is a frame synchronization signal and a TMCC signal), the signal points are
And QPSK modulation (when the input is the low-layer image signal LQ), signal points are mapped as shown in FIG. 5, and when 8PSK modulation is performed (input In the case where the image signal HQ is for a higher hierarchy), the signal points are mapped as shown in FIG.

As a result of the convolutional encoding process of the convolutional encoding circuit 10, the 2-byte frame synchronization signal and the 10-byte TMCC signal are converted into 32-bit (4 byte) frame synchronization as shown in FIG. Signal and 160 bits (2
0 byte) TMCC signal. FIG. 8C shows a convolutional code in which the constraint length is 7 and the coding rate is 1/2.

As described above, the interleaving circuit 5 allows the error to be sufficiently dispersed and the TMCC signal subjected to the concatenation coding of the convolutional code and the RS code is converted to the BP code.
By performing modulation using the SK modulation method, it is possible to provide a stronger resistance to transmission errors.

Incidentally, the contents of the transmission control signal of the main signal included in the TMCC signal are not frequently changed. However, the receiving apparatus can know the modulation scheme and coding rate of the main signal from the transmission control signal obtained by decoding the TMCC signal. It is necessary to receive and demodulate. That is, on the transmitting device side, the TMCC signal does not need to be transmitted so frequently, but on the receiving device side, the main signal cannot be received until the TMCC signal is received. It is preferable to be able to receive relatively frequently so that it can be as short as possible. Therefore, it is preferable to reduce the frequency of transmission of the TMCC signal as long as the waiting time of the receiving device does not become long.

FIG. 12 shows a configuration example of a receiving apparatus according to an embodiment of the present invention.

In FIG. 12, a modulated signal transmitted through a predetermined transmission line is
1 is input to the demapping circuit 43. The frame synchronization detection circuit 41 detects a frame synchronization signal from the input signal, and outputs the detection result to the demapping circuit 43 and the Viterbi decoding circuit 44. The phase detection circuit 42 detects the phase information of the signal point from the output of the frame synchronization detection circuit 41, and outputs the detection result to the demapping circuit 43. The demapping circuit 43 detects a signal point based on the output of the TMCC decoder 47 or the frame synchronization detection circuit 41, generates a metric corresponding to the signal point, and outputs the metric to the Viterbi decoding circuit 44. The TMCC decoder 47 demodulates (decodes) the input TMCC signal, and outputs the demodulated result (modulation method and coding rate) to the demapping circuit 43 and the Viterbi decoding circuit 44.
Output to

The Viterbi decoding circuit 44 performs Viterbi decoding of the signal from the demapping circuit 43 based on the output of the TMCC decoder 47 or the frame synchronization detection circuit 41. The Viterbi decoding circuit 44 converts a demodulated signal of a BPSK signal (frame synchronization signal and TMCC signal) following the frame synchronization signal into
The convolution decoding process is performed, and the result is output to the deinterleave circuit 45. The deinterleave circuit 45 is a circuit that performs a deinterleave process corresponding to the convolutional interleave of the interleave circuit 5 in FIG. The Reed-Solomon decoding circuit 46 decodes the RS (48, 38) code input from the deinterleave circuit 45, and outputs the decoding result to the TMCC decoder 47 and the frame synchronization determination circuit 54.

The deinterleave circuit 48 and the deinterleave circuit 51 convert the low-layer image signal LQ or the high-layer image signal HQ supplied from the Viterbi decoding circuit 44 into the interleave circuits 8 and 15 shown in FIG. De-interleave according to the interleave processing. The Reed-Solomon decoding circuits 49 and 52 decode the outputs of the deinterleaving circuits 48 and 51, respectively, into RS (204, 188) codes corresponding to the Reed-Solomon coding circuits 6 and 13 in FIG. The TS synchronization byte register 53 stores a synchronization byte to be added to each packet of the TS, and the multiplexing circuit 50 controls the Reed-Solomon decoding circuit 49 or 52.
The synchronization byte read from the TS synchronization byte register 53 is added to the TS packet output from the.

In the receiving apparatus shown in FIG. 12, not only the frame synchronization signal but also the main signal is input to the frame synchronization detection circuit 41. As described above, assuming that the frame synchronization signal is 16 bits, the convolutional encoding circuit 10 of the transmitting apparatus converts the frame synchronization signal into 32 bits.
It has been converted to bit data. The length (the number of bits) of the frame synchronization signal is the constraint length of the convolutional coding circuit 10 (the minimum number of bits required for the convolution operation).
In the case of the example, the constraint length is set to 7). Since the number of bits is set to be longer, unique bits of the frame synchronization signal are held in all of the registers 61 to 66 of the convolutional encoding circuit 10. Exclusive OR circuits 67 and 7
A state occurs where the input to 1 is also a bit constituting the frame synchronization signal. In this state, since all data used for the convolutional encoding is composed of bits of the frame synchronization signal, data obtained as a result of the convolution operation is also
It becomes unique data.

That is, as shown in FIG. 13, even if the first bit of the frame synchronizing signal is input to the shift register 61 of the convolutional coding circuit 10 in FIG. 11 (timing t1), in that state, The previous data (data A to E other than the frame synchronization signal) is held in the shift registers 62 to 66, so that the data output from the exclusive OR circuits 70 and 74 cannot be uniquely determined. Absent. The first bit of the frame synchronization signal is held in the shift register 66, the sixth bit is held in the shift register 61, and the seventh bit is supplied to the exclusive OR circuits 67 and 71 (timing t6).
For the first time, the data output from the exclusive OR circuits 70 and 74 have a unique value corresponding to the frame synchronization signal.

Hereinafter, similarly, exclusive OR circuits 70, 7
In the output of No. 4, the tenth bit of the frame synchronization signal is held in the shift register 66 and the shift register 61 outputs the fifteenth bit.
The bit is held and becomes a unique value until the 16th bit of the frame synchronization signal is input to the exclusive OR circuits 67 and 71 (timing t15). When the 16th bit of the frame synchronizing signal is held in the shift register 61 (timing t16), the next data a following the frame synchronizing signal is input to the exclusive OR circuits 67 and 71. Logical OR circuits 70 and 7
The data output from No. 4 is not uniquely determined.

The frame synchronization detection circuit 41 changes the state of the exclusive OR circuits 67 and 71 from the state where the seventh bit of the frame synchronization signal is input to the exclusive OR circuits 67 and 71 and outputs the 16th bit of the frame synchronization signal to the exclusive OR circuits 67 and 71. Until the input state is reached, the frame synchronization signal is detected by detecting a unique pattern (specific pattern) generated by the exclusive OR circuits 70 and 74.

If the position of the frame synchronization signal is known, the absolute phase of the signal point can be detected. Therefore, the phase detection circuit 42 detects the absolute phase of the signal point from the detection result output from the frame synchronization detection circuit 41. This removes the uncertainty in the phase of the recovered carrier.

The demapping circuit 43 sets a signal following the frame synchronization signal as a BPSK-modulated signal based on the detection signal input from the frame synchronization detection circuit 41.
The demapping process is performed according to the principle shown in FIG. 4, and the corresponding metric is output to the Viterbi decoding circuit 44. Based on the detection signal input from the frame synchronization detection circuit 41, the Viterbi decoding circuit 44 determines that a signal following the frame synchronization signal has been subjected to 畳 convolutional encoding.
This is Viterbi decoded.

The convolutionally decoded signal including the frame synchronization signal and the TMCC signal output from the Viterbi decoding circuit 44 is input to a deinterleave circuit 45 and deinterleaved. The output of the deinterleave circuit 45 is input to a Reed-Solomon decoding circuit 46, where it is subjected to Reed-Solomon decoding, and transmission errors are corrected. The output of the Reed-Solomon decoding circuit 46 is output to a TMCC decoder 47 and a frame synchronization determination circuit 54.
Supplied to

The TMCC decoder 47 decodes the TMCC signal from the input signal, and extracts transmission control information such as the modulation method and coding rate of the subsequent main signal. The extracted result is output to the demapping circuit 43 and the Viterbi decoding circuit 44. Demapping circuit 43 and Viterbi decoding circuit 44
Processes the input main signal according to the transmission control information from the TMCC decoder 47.

The demapping circuit 43 performs a demapping process on the main signal supplied next to the TMCC signal in accordance with the transmission control information from the TMCC decoder 47. That is, when the input main signal is QPSK modulated, the demapping process is performed according to the principle shown in FIG. 5, and when the input main signal is TC8PSK modulated, the demapping process is performed according to the principle shown in FIG. Do.

For example, the demapping circuit 43 performs a demapping process in the QPSK modulation method on the image signal LQ for the lower hierarchy, and performs a demapping process of TC8PSK on the image signal HQ for the higher hierarchy. I do.

The metric output from the demapping circuit 43 is input to a Viterbi decoding circuit 44. The Viterbi decoding circuit 44 performs a convolution decoding process according to the transmission control signal output from the TMCC decoder 47. For example, a depuncturing process and a decoding process for a convolution process at a coding rate of 行 い are performed on the image signal LQ for the lower hierarchy, and the coding rate of 2 is obtained for the image signal HQ for the higher hierarchy. /
3 trellis decoding processing.

The demodulated signal of the main signal output from the Viterbi decoding circuit 44 is input to deinterleaving circuits 48 and 51 and deinterleaved. Deinterleave circuit 48,
The output of 51 is input to Reed-Solomon decoding circuits 49 and 52. The Reed-Solomon decoding circuits 49 and 52
The RS (204, 188) code is decoded. The multiplexing circuit 50 reads the first TMCC of each packet of each frame read from the Reed-Solomon decoding circuit 49 or 52.
The synchronization byte held in the TS synchronization byte register 53 is multiplexed at the position where the signal is located. As a result, the original TS packet as shown in FIG. 7 is obtained.

Next, the protection processing of the frame synchronization signal will be described. The frame synchronization detection circuit 41 detects the frame synchronization signal, and performs the backward protection processing of the frame synchronization signal as shown in steps S31 to S40 in FIG. The processing in steps S31 to S40 is the same as the processing in steps S1 to S10 in FIG. 2, and a description thereof will be omitted.

After the synchronization establishment processing is performed in step S35, the frame synchronization determination circuit 54 detects the frame synchronization signal from the output of the Reed-Solomon decoding circuit 46 in step S41 and performs the frame synchronization determination processing. . Since the signal output from the Reed-Solomon decoding circuit 46 is a signal after the frame synchronization signal is convolutionally decoded by the Viterbi decoding circuit 44, the error on the transmission path has already been corrected. Therefore, the forward protection operation as shown in steps S11 to S15 in FIG. 2 becomes unnecessary in the embodiment of the present invention,
When the frame synchronization signal cannot be detected even once from the output of the Reed-Solomon decoding circuit 46, the frame synchronization determination circuit 54 determines that frame synchronization has been lost immediately.

Next, a second embodiment will be described. BS
In digital broadcasting, one channel is a high-definition television signal represented by so-called high-definition television.
TC8PSK (r = 2/2 /) as a main signal transmission method, in order to be able to transmit one program and to perform reliable transmission even when the electric field intensity is attenuated. 3) (r represents the coding rate), QPSK (r = ３), QPSK (r = １ ／), BPSK
A transmission method such as (r = 1/2) can be selected by a business operator. For this reason, it is possible to transmit which method is adopted as a TMCC signal to the receiving device side as described above.

As described above, the TMCC signal is BPSK (r =
The main signal is TC8PSK (r = 2), assuming that a high-definition television signal is transmitted.
/ 3) is likely to be transmitted. Due to the nature of satellite broadcasting,
Since the weather conditions are different for each area, the reception C / N may be extremely low in a predetermined area. Even in such a situation, it is necessary to reliably transmit and receive the TMCC signal.

Generally, when the transmission system is switched, the branch metric defined by the Viterbi decoding circuit 44 becomes different. In the Viterbi decoding circuit 44, path control is performed according to the value of the state metric obtained by accumulating the branch metrics, and when the transmission method is switched,
The branch metrics after the switching are accumulated with respect to the state metrics that have been accumulated up to that point, and if path control is performed based on the state metrics, an error may propagate. In particular, 8P from BPSK
When the number of multilevel levels changes abruptly, as in the case of a change to SK, such an effect will appear significantly.

Therefore, in order to cut off the propagation of the error, a so-called termination process may be performed. This termination processing means to insert a specific (known) pattern into transmission data. Since the specific pattern for the termination processing does not carry information, even if that part is erroneous, information is not lost, and this is when switching from a predetermined transmission method to another transmission method. As a buffer bit sequence.

Therefore, as shown in FIGS. 15A to 15B, the frame synchronization signal (TAB1) is placed at the head of the TMCC signal (between the main signal (payload) and the TMCC signal).
Is inserted, and a signal (TAB2) of a predetermined pattern for termination processing is inserted after the TMCC signal (between the TMCC signal and the next main signal). The rear signal TAB in this case
The length of 2, for example, is 2 bytes corresponding to the frame synchronization signal (TAB1). This signal is stored in advance in the synchronization register 2 (FIG. 3) together with the frame synchronization signal.
It is read from there as appropriate.

It should be noted that FIG. 15A to FIG.
In FIG. 15A, the input bit sequence shown in FIG. 15A is input to the convolution encoding circuit 10 shown in FIG. The output bit sequence to be output is output.

To terminate the convolutional code, a known bit sequence smaller by one than its constraint length may be inserted.
That is, in the case of the configuration example of FIG.
Since 0 has a constraint length of 7, a known 6-bit code string may be inserted as a code for the termination processing, but if a longer known bit sequence is inserted,
The encoded output having the constraint length or more has a specific pattern as described above. For example, as shown in FIG.
Assuming that a 2-byte frame synchronization signal is inserted before the signal, as shown in FIG. 15C, 12 bits (12 symbols) of the output bit sequence of the convolutional encoding circuit 10
Is an undefined pattern, but the subsequent 20-bit (20 symbols) pattern is a specific pattern. In the configuration example of FIG. 3, in the frame synchronization detection circuit 41,
This specific pattern was detected as a frame synchronization signal.

As shown in FIG. 15 (A), when a signal for the termination processing of, for example, 2 bytes is added to the rear of the TMCC signal, the corresponding 4 bits of the output of the convolutional coding circuit 10 are output. 12 bits (12 bits) of the byte signal
Symbol) becomes an undefined pattern, and the subsequent 20 bits (20 symbols) become a specific pattern. As this specific pattern, the frame number of the superframe can be transmitted. The super frame is composed of eight frames, and indicates the order of the eight frames (represents the position).
The frame number can be transmitted as a signal of a specific pattern behind the TMCC signal.

In this case, the frame synchronization detection circuit 41 may detect the 4-byte signal on the front side of the TMCC signal as a frame synchronization signal, as in the above-described case. A signal, or both, may be detected as a frame synchronization signal.

In this way, not only can a termination process for mitigating error propagation be performed, but also these signals can be used as a frame synchronization signal or a frame number.

Further, in the case of this example, 4 bits before the TMCC signal are output.
Both the byte signal and the subsequent 4-byte signal are subjected to BPSK modulation by the mapping circuit 11. From the viewpoint of the termination processing of the convolutional code, the termination processing is generally performed by the same modulation scheme as that of the signal to be terminated. For example, as shown in FIGS. 15A to 15C, a 4-byte signal added before the TMCC signal is:
Since the convolutional code of the main signal (payload) is terminated, for example, 8PSK modulation is generally performed similarly to the main signal.

However, when C / N is the same,
Compared to the branch metric of 8PSK (r = 2/3), BP
The branch metric of SK (r = １ ／) has higher reliability. Also, from the viewpoint of improving the reliability of the TMCC signal transmitted by BPSK (r =）), it is necessary to improve the reliability of the state metric that performs path control at least a little. Even so, it is more advantageous to perform the convolutional code termination processing by BPSK (r = 1/2). Therefore,
In the present embodiment, TMCC signal termination processing is performed by TMCC
Rear 4 modulated with the same BPSK (r = 1/2) as the signal
In addition to performing byte signal processing, the termination processing of the main signal (payload) is also performed using 8PSK (r =
BPSK (r), which is the modulation method of the TMCC signal,
= 1/2), and is performed using a 4-byte signal behind (a 4-byte signal in front of the TMCC signal).

Therefore, in the receiving apparatus, the TMCC signal and the 4-byte signals before and after the TMCC signal are BPSK-demodulated by the demapping circuit 43.

As shown in FIGS. 15A to 15C, an input sequence I1 is arranged in TAB1 in front of the TMCC signal, and an input sequence I1, I
2 or I3 are arranged.

At this time, the convolutional encoding circuit 10
The specific pattern W1 is output in TAB1 before the CC signal, and W1, W2 or W3 is output in TAB2 after the TMCC signal.

When detecting the frame synchronization signal in the frame synchronization detection circuit 41 of the receiving apparatus shown in FIG. 12, it is preferable that the autocorrelation function of the specific pattern (frame synchronization signal) is impulsive.
The autocorrelation function is defined by the following equation.

[0102]

(Equation 1)

In the above equation, C (t) is a specific pattern (specific pattern after convolutional encoding by the convolutional encoding circuit 10) W1 of the code output sequence, and C (0) is the MSB of W1 and C (19). ) Is the LSB of W1. Also, t
Is any value from 0 to 19, and t and t−τ are 0
When it exceeds the range from 19 to 19, (2 × C
The value of (t) -1) × (2 × C (t−τ) −1) is 0.

As the specific pattern W1, 0xD439B
And Wx can be 0x0B677, and W3 can be 0x578DB.

As the specific pattern W1, 0xD439B
Is used, R (0) = 20 and | R (τ) | ≦ 3
(Τ ≠ 0), and an impulse-like autocorrelation characteristic is realized. Each of the specific patterns W2 and W3 is 0x
Similarly, even when 0B677 or 0x578DB is used, an impulse-like autocorrelation characteristic can be realized.

When the specific patterns output from the convolutional encoding circuit 10 are W1, W2, and W3, the autocorrelation characteristics of the input sequence patterns I1, I2, and I3 input thereto are also impulse-like. Is preferred. In this case, the autocorrelation function is defined by the following equation.

[0107]

(Equation 2)

Here, I (t) is an input sequence corresponding to W1, I (0) is the MSB of I1, and I (15) is I1
LSB. t takes a value from 0 to 15. t and t-
When τ exceeds the range of 0 to 15, (2 × I
The value of (t) −1) × (2 × I (t−τ) −1) is 0.

Input sequence I1 corresponding to specific pattern W1
, R (0) = 16 and | R (τ)
| ≦ 3 (τ ≠ 0), and an impulse-like autocorrelation characteristic is realized.

Input sequence I2 corresponding to specific pattern W2
, R (0) = 16 and | R (τ)
| ≦ 5 (τ ≠ 0). Further, with respect to the input sequence I3 corresponding to the specific pattern W3, R (0) = 16 and | R (τ) | ≦ 7 (τ ≠ 0), which also realizes good autocorrelation characteristics. Can be.

When the specific pattern W1 is 0xD439B, the frame synchronization detecting circuit 41 of the receiving apparatus, for example, uses the specific pattern 0xD439B (= 110100100).
001110011011) as a detection window,
An exclusive OR operation is performed on the value and the input 20-bit data for each bit. If the corresponding bits of the 20 bits are the same, the computed value of the exclusive OR for each bit is 0, and if different, it is 1. The sum of the calculated values of the exclusive OR of 20 bits becomes the correlation value. When the same data as the detection window is input, the correlation value becomes 0.
When other data is input, the value is sufficiently larger than 0. Thereby, the frame synchronization signal (specific pattern W1 (0xD439B)) can be detected.

The input sequence I1 (0x032E) (= 000000) corresponding to the specific pattern W1 (0xD439B)
1100101110), the leading 6 bits are 0, which allows the convolution encoding circuit 10 to be initialized. That is, this 6-bit 0 is held in the shift registers 61 to 66 (FIG. 11), and the previous code sequence can be terminated. This also means that the input code sequence is terminated with 0. As a result, the configurations of the transmitting device and the receiving device can be simplified.

Also, the specific pattern W2 (0x0B67)
7) Input sequence 0xA340 (= 101000)
110100000) and the specific pattern W3 (0x5
78DB), the input sequence 0x78C0 (= 011)
11000110000000), the last 6 bits are all 0, and in this case also, the convolutional encoding circuit 10 can terminate the previous code sequence. This also means terminating the TMCC signal and initializing the next code. Therefore, this also simplifies the configuration of the transmitting device and the receiving device.

FIG. 16 shows the specific patterns W1 to W3,
An example in which the frames are periodically arranged based on a superframe is shown. In this example, in frame 1, W1 is arranged in front of the TMCC signal, and W2 is arranged in the rear. In subsequent frames 2 to 8, W1 is arranged in front of the TMCC signal, and W3 is arranged in the rear. Are located. With this arrangement, a super frame can be detected. The flowchart in FIG. 17 shows the processing in this case.

That is, first, in step S61, the frequency adjustment for tuning of the receiving apparatus is performed using the correlation of the specific pattern W1 arranged before the TMCC signal of each frame. That is, the specific pattern W1
Is controlled such that the clock is generated and the frame synchronization is obtained so that the correlation value of becomes the best.

Next, in step S62, a signal located at a position behind the position where the specific pattern W1 is detected by the length of the TMCC signal is detected as the specific pattern W2. As shown in FIG. 16, the specific pattern W2
Are arranged only in the first frame of the superframe, and the specific pattern W3 is arranged in the remaining seven frames. Therefore, the frame in which the specific pattern W2 is detected is detected as the first frame of the super frame.

Next, in step S63, frame synchronization protection is performed. If the frame is in the synchronized state, the frame synchronization protection processing is repeatedly executed. If the frame synchronization protection is released, the process returns to step S61, and thereafter. Is repeatedly executed.

As described above, the last 6 bits of the input sequence I2 or I3 of the specific pattern W2 or W3 after the TMCC signal are all 0s. Therefore, as shown in FIG. 18A and FIG. 18B in which a part of FIG. 18A is enlarged,
The convolutional encoding circuit 10 for the main signal (payload) is TM
Regardless of the content of the CC signal, the main signal can be encoded from the state initialized to 000000. After the encoding of the main signal (payload) is completed, the input sequence I1 of the specific pattern W1 input prior to the TMCC signal is performed.
, The convolutional encoding circuit 10 can encode the signal up to 000000 as the code of the main signal (payload).

FIG. 19 shows another configuration example for convolutional coding in the transmitting apparatus. In this configuration example, the multiplexing circuit 101 supplies data of the seventh and subsequent bits of the input sequence I1 corresponding to the specific pattern W1, a TMCC signal,
Alternatively, input sequences I2 and I3 corresponding to the specific pattern W2 or W3 are supplied. The multiplexing circuit 101 selects one of them and supplies it to the encoder 102 as the convolutional encoding circuit 10. The encoder 102 is initialized with 6 bits of 0 before the seventh bit of the input sequence I1 corresponding to the input specific pattern W1 is input.

On the other hand, the main signal (payload) and 6-bit data 000000 are supplied to the multiplexing circuit 104, and the multiplexing circuit 104 selects one of them.
This is supplied to an encoder 105 as the convolutional encoding circuit 10. The encoder 105 is initialized with 6 bits of 0 before the first data of the payload is input.

The output of the encoder 102 and the output of the encoder 105 are supplied to a multiplexing circuit 103, multiplexed, and output.

As described above, in the case of the configuration example of FIG.
Since the encoder 102 for encoding a signal can be configured independently of the encoder 105 for encoding a payload, the encoder 10 normally provided as an existing transmission device is used.
By simply adding a new encoder 102 to FIG. 5, a transmission apparatus to which the present invention can be applied can be easily realized.

As shown in FIG. 19, the code sequence is TMCC
It can be considered that the signal and the main signal (payload) are independent. Therefore, also in the receiving apparatus, decoding can be performed independently for each corresponding code sequence. FIG. 20 shows a configuration example in this case.

That is, in this configuration example, the separation circuit 121 separates the input code into a code sequence corresponding to the TMCC signal and a code sequence corresponding to the payload,
The former is supplied to the decoder 122, and the latter is supplied to the decoder 124. The decoder 122 decodes a code sequence corresponding to the input TMCC signal, and supplies the decoded code sequence to the separation circuit 123.
Separating circuit 123 separates the decoding result from decoder 122 into data of the seventh bit and subsequent bits of input sequence I1 corresponding to specific pattern W1, a TMCC signal, or input sequences I2 and I3 corresponding to specific pattern W2 or W3. And output.

[0125] The decoder 124 decodes the main signal (payload) from the separation circuit 121 and outputs it to the separation circuit 125. The separation circuit 125 separates the data supplied from the decoder 124 into a payload and a 6-bit 0 code.
Output. Since the 6-bit 0 is not actually used, only the main signal (payload) may be extracted.

The decoder 122 and the decoder correspond to the Viterbi decoding circuit 44 of the receiving apparatus shown in FIG. 12, respectively.

Also in this case. Normally, a new decoder 12 is provided for the decoder 124 provided in the receiving apparatus.
By simply adding 2, it is possible to easily configure a receiving apparatus to which the present invention can be applied.

It is needless to say that, as shown in FIG.
The decoder 122 and the decoder 124 shown in FIG.
It can also be common as. In this case, the separation circuit 1
32, from the output of the decoder 131, data of the seventh and subsequent bits of the input sequence I1 corresponding to the specific pattern W1, TMCC
The signal, the input sequences I2 and I3 corresponding to the specific pattern W2 or W3, and the main signal (payload) are separated and output.

Next, a third embodiment will be described. TMCC
When the robustness of the signal to the transmission path error increases, it is not necessary to frequently transmit the TMCC signal from that viewpoint. Therefore, when the TMCC signal is not transmitted, other data may be transmitted instead of the TMCC signal. FIG.
Represents a configuration example of the transmission device in this case. In addition,
In FIG. 22, portions corresponding to those in FIG. 3 are denoted by the same reference numerals. In the configuration example of FIG. 22, data (sub-signal) transmitted in place of the TMCC signal is supplied to the memory 21 and stored.
The multiplexing circuit 3 stores the TM stored in the memory 1
A CC signal or data stored in the memory 21 is selected, multiplexed with a frame synchronization signal supplied from the synchronization register 2, and output. Other configurations are the same as those in FIG.

However, in the case of this configuration example, the controller 12 controls the multiplexing circuit 9, and the header added to each frame transmits the header in that frame.
An identifier indicating whether the signal is a TMCC signal or other data is included.

Next, a fourth embodiment will be described. The interleave circuit 5 of the transmission device is roughly classified into a block type and a convolution type. However, the interleave circuit 5 has a small circuit size and a corresponding portion of the preceding and succeeding RS codes is stored in the same position. From the nature, as described above, a convolutional interleave circuit is used as the interleave circuit 5.

FIGS. 23 (A) to 23 (C) show how the TMCC signals are dispersed in the convolutional interleave circuit 5 shown in FIG. 23 (B). As shown in the drawing, the RS code of the number N is composed of 48 bytes, the first 38 bytes of which are data, and the second 10 bytes are parity. As described above, the first two bytes of the 38-byte data are used as a frame synchronization signal. This means that the numbers N + 1 through N
The same applies to the +4 RS code. This RS code is generated by the Reed-Solomon encoding circuit 4.

As shown in FIG. 23, the convolutional interleave circuit 5 shown in FIG. 23 (B) converts the first two data to the input data shown in FIG. 23 (A).
Although the byte frame synchronization signal is output as it is, the output is delayed by one to five delay units in units of two bytes. As a result, as shown in FIG. 23C, the RS codes are distributed in units of 2 bytes over the five RS codes. For example, the first two bytes (frame synchronization signal) of the RS code of the number N + 4 are the interleaved RS code arranged at the head, and then the data of the third and fourth bytes of the number N + 3 are After that, the data of the bytes of No. 5 and No. 6 of No. N + 2 are arranged. Similarly, the position of each byte of the RS code before interleaving is arranged at the same position in the RS code after interleaving.

Therefore, assuming that the TMCC signals of numbers N to N + 4 are equal, the RS codes of numbers N to N + 4 are equal before and after interleaving, respectively. As described above, the TMCC signal changes only infrequently due to the nature of the transmission control signal, and in most cases,
It is the same data. Therefore, the receiving apparatus can correct the error of the TMCC signal by the so-called majority decision processing without RS decoding the Viterbi-decoded RS code.

FIGS. 24 and 25 show examples of the configuration of each embodiment of the receiving apparatus in this case. In the embodiment of FIG. 24, the output of the deinterleave circuit 45 is input to the majority decision circuit 71,
1 is supplied to the TMCC recorder 47 and the frame synchronization determination circuit 54. That is, the configuration is such that the Reed-Solomon decoding circuit 46 in FIG. 12 is omitted. Other configurations are the same as those in FIG.

In this configuration example, majority decision circuit 7
1 performs error correction on the RS code deinterleaved by the deinterleave circuit 45 based on the principle of majority decision. That is, for example, when five RS codes are input, the data having the largest content is regarded as correct data.

With this configuration, the configuration can be simplified and the device can be downsized as compared with the case where a Reed-Solomon decoding circuit 46 is provided as shown in FIG.

In the embodiment of FIG. 25, the deinterleave circuit 45 and the Reed-Solomon decoding circuit 46 in FIG. 12 are omitted, and instead, the majority decision circuit 71
Is provided. That is, the output of the Viterbi decoding circuit 44 is directly input to the majority decision circuit 71, and the output of the majority decision circuit 71 is supplied to the TMCC decoder 47 and the frame synchronization decision circuit 54.

As described above, assuming that the TMCC signals are the same, the interleaving circuit 5 makes the interleaved RS code the same as the pre-interleaved RS code. That is, this is substantially the same as the case where interleaving is not performed. Therefore, the deinterleave circuit 45 in FIG. 24 can be omitted, and the output of the Viterbi decoding circuit 44 can be directly decoded by the majority decision circuit 71. With this configuration, it is possible to further simplify the configuration and reduce the size of the device as compared with the case shown in FIG.

However, in the case of the embodiment of FIG. 24, since the deinterleave circuit 45 is provided, the input of the majority decision circuit 71 (the output of the deinterleave circuit 45) is shown in FIG.
As shown in FIG. On the other hand, in the embodiment of FIG. 25, since the deinterleave circuit 45 is not provided, the input of the majority decision circuit 71 (the output of the deinterleave circuit 45) is as shown in FIG. In any case, if the TMCC signal is the same, the RS
Since the signs are substantially the same, it is possible to make a decision by majority decision.

That is, in FIG. 26 when deinterleaving is performed on the receiving side and in FIG. 27 when deinterleaving is not performed on the receiving side, majority determination is performed on the Data portion.

In the case of the embodiment shown in FIGS. 24 and 25, it is necessary to repeatedly transmit the same TMCC signal.
Compared with the embodiment of FIG. 12, the amount of data that can be transmitted other than the TMCC signal is reduced.

As a transmission medium for transmitting a program for performing the above-described processing to a user, a recording medium such as a magnetic disk, a CD-ROM, and a solid-state memory, as well as a communication medium such as a network and a satellite may be used. Can be.

[0144]

According to the digital broadcast signal receiving apparatus and method according to the present invention, a predetermined unique bit pattern (specific pattern) is detected from among the coded bits of the digital broadcast signal transmitted by being convolutionally coded. Therefore, the frame synchronization signal can be detected stably and at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a conventional transmission device.

FIG. 2 is a flowchart illustrating a synchronization process of a conventional receiving device.

FIG. 3 is a block diagram illustrating a configuration example of a transmission device for transmitting a digital broadcast signal to a reception device to which the present invention has been applied.

FIG. 4 is a diagram illustrating symbol mapping of a BPSK modulation scheme.

FIG. 5 is a diagram illustrating mapping of symbols of the QPSK modulation scheme.

FIG. 6 is a diagram illustrating mapping of symbols of the 8PSK modulation scheme.

FIG. 7 is a diagram illustrating packets of a transport stream.

FIG. 8 is a diagram for explaining a change in a TMCC signal.

FIG. 9 is a diagram showing a more detailed configuration example of the interleave circuit 5 of FIG. 3;

FIG. 10 is a diagram illustrating a format of a signal obtained by a multiplexing process in the multiplexing circuit 9 of FIG. 3;

11 is a block diagram illustrating a configuration example of a convolution decoding circuit 10 in FIG.

FIG. 12 is a block diagram illustrating a configuration example of an embodiment of a receiving device to which the present invention has been applied.

FIG. 13 is a diagram illustrating an operation of the frame synchronization detection circuit 41 of FIG. 11;

FIG. 14 is a flowchart illustrating a synchronization process in the receiving device of FIG. 11;

FIG. 15 is a diagram for explaining the operation of the convolutional encoding circuit 10;

FIG. 16 is a diagram illustrating an arrangement of a specific pattern in a super frame.

FIG. 17 is a flowchart illustrating a process of detecting a specific pattern in the format of FIG. 16;

FIG. 18 is a diagram showing formats of a TMCC signal and a main signal (payload).

FIG. 19 is a diagram illustrating a configuration example when a TMCC signal and a main signal (payload) are independently encoded.

FIG. 20 is a diagram illustrating a configuration example when a TMCC signal and a main signal (payload) are independently decoded.

FIG. 21 is a block diagram illustrating a configuration example when a TMCC signal and a main signal (payload) are commonly decoded.

FIG. 22 is a block diagram illustrating another configuration example of a transmission device for transmitting a digital broadcast signal to a reception device to which the present invention has been applied.

FIG. 23 is a diagram for explaining processing of the interleave circuit 5;

FIG. 24 is a block diagram illustrating a configuration example of another embodiment of a receiving device to which the present invention has been applied.

FIG. 25 is a block diagram illustrating a configuration example of still another embodiment of a receiving device to which the present invention has been applied.

FIG. 26 is a diagram illustrating an input of the majority decision circuit 71 of FIG. 24;

27 is a diagram illustrating an input of the majority decision circuit 71 of FIG.

[Explanation of symbols]

1, 7, 14 memories, 2 synchronization registers, 3, 9
Multiplexing circuit, 4,6,13 Reed-Solomon encoding circuit, 5,8,15 interleaving circuit, 10 convolutional encoding circuit, 11 mapping circuit, 12
Controller, 41 frame synchronization detection circuit, 42
Phase detection circuit, 43 demapping circuit, 44
Viterbi decoding circuit, 45, 48, 51 deinterleaving circuit, 46, 49, 52 Reed-Solomon decoding circuit, 50 multiplexing circuit, 53TS synchronous byte register, 54 frame synchronization determining circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI H04L 27/18 H04L 27/18 B H04N 7/24 H04N 7/13 A (31) Priority claim number Japanese Patent Application No. 9-226056 ( 32) Priority date August 22, 1997 (August 22, 1997) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 9-239771 (32) Priority date 1997 September 4, 1997 (September 9, 1997) (33) Countries claiming priority Japan (JP) Application for accelerated examination (56) References JP-A-9-23214 (JP, A) JP-A-61-2529 (JP JP-A-7-236126 (JP, A) JP-A-7-170201 (JP, A) JP-A-9-266471 (JP, A) JP-A-9-321813 (JP, A) Kato, et al. "Application of hierarchical transmission to the BCS96-14 12GHz z-band satellite ISDB", Technical Report of the Institute of Television Engineers of Japan, Vol. 20, No. 22, March 15, 1996, p. 11-16 1. H. Katoh, et al., "A Flexible Transmission Technology for the Satellite ISDB System", IEEE TRANSAC TIONS ON BROADCAST ING, Vol. 42, No. 3, September 1996, p. 159-166 (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 1/00 H03M 13/00 H04J 3/00 H04L 7/00 H04L 27/18 H04N 7/24

Claims (4)

(57) [Claims] 1. A main signal is transmitted in a payload portion of a transport packet, a frame is formed by a predetermined number of transport packets, and at least a part of a synchronization portion of the transport packet in the frame is related to a transmission system.
And the n-bit first and second synchronization signals transmitted before and after the control signal .
The signal is a superframe composed of multiple frames.
Different bit patterns are used for the first frame and other frames.
With turns, constraint length m (n> m) and coding rate 1/2
Control signal and the first and second convolutional coding circuits
By the synchronization signal is convolutionally encoded, the first
The first and second synchronization signals are 2n-bit first and second synchronization signals, respectively .
First, of the second coded bit, at least one of a predetermined unique bit of a digital broadcasting signal receiving apparatus for receiving a digital broadcast signal transmitted as a coded bit, the 2n bits received A frame synchronization detecting circuit for performing frame synchronization detection by detecting a pattern, and a bit of the received 2n second coded bits
It consists of multiple frames by detecting the sequence
Identification circuit that identifies the first frame of a superframe
And a demodulation circuit that performs demodulation in accordance with an output signal of the frame synchronization detection circuit. 2. A Viterbi decoding circuit for Viterbi decoding an output signal of the demodulation circuit, and the first or second signal obtained from the output of the Viterbi decoding circuit .
2. The digital broadcast signal receiving apparatus according to claim 1, further comprising a frame synchronization protection circuit that determines whether or not frame synchronization is established based on the second synchronization signal . 3. A main signal is transmitted in a payload portion of a transport packet, a frame is formed by a predetermined number of transport packets, and at least a part of a synchronization portion of the transport packet in the frame is related to a transmission system.
And the n-bit first and second synchronization signals transmitted before and after the control signal .
The signal is a superframe composed of multiple frames.
Different bit patterns are used for the first frame and other frames.
With turns, constraint length m (n> m) and coding rate 1/2
Of the control signal and the first and second convolutional codes.
By applying the first and second synchronization signals to the
Of 2n bits each first, a digital broadcasting signal receiving method for receiving a digital broadcast signal transmitted as the second coded bits, the first encoded bits of the 2n bits received, the second <br By detecting at least one predetermined unique bit pattern among the coded bits , frame synchronization detection is performed.
Frame synchronization detecting step of performing the above-mentioned, and the bits of the received 2n-bit second encoded bits
It consists of multiple frames by detecting the sequence
Identification process for identifying the first frame of a superframe
And a demodulation step of demodulating according to an output signal of the frame synchronization detection step. 4. A Viterbi decoding step of Viterbi decoding the output signal of the demodulation step, and the first or second signal obtained from the output of the Viterbi decoding step .
4. The digital broadcast signal receiving method according to claim 3, further comprising a frame synchronization protection step of determining whether or not frame synchronization is established based on the second synchronization signal .