JP3103262B2 - Circuit breaker test circuit for switchgear - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a composite cutoff test circuit that verifies the cutoff performance of a high-speed ground switch (HSGS) used in a substation or switchyard of a 0 kV power system.

[0002]

2. Description of the Related Art To compensate for power shortages caused by difficulties in constructing power plants in urban areas, power plants are constructed in remote and sparsely populated areas, and power is transmitted to large cities by long-distance transmission lines of high voltage.
UHV transmission of 0 kV class is planned. With this, U
Development research on substation switchgear for HV systems is under way. In order to ensure the insulation of UHV voltage, a closed gas insulated switchgear (GIS) using the excellent insulation performance of sulfur hexafluoride gas (SF6 gas) is employed. This GIS is composed of many devices such as a circuit breaker, a disconnecting switch, a grounding switch, a high-speed grounding switch (HSGS). Meanwhile, in the UHV system, a phenomenon occurs in which the secondary arc of the arc horn does not extinguish naturally due to induction from another healthy phase even after the fault is eliminated by the circuit breaker at the time of the transmission line fault. Therefore, in the UHV system, HSGS is adopted as shown in phase c of FIG. 6, and the HSGS is forcibly supplied in the open state of the circuit breaker to extinguish the secondary arc. HSGS is opened approximately 0.5 seconds after the disappearance of the secondary arc, and the electromagnetic or electrostatic induction current flowing through the line is cut off. After that, the circuit breakers at both ends of the line are re-input at high speed to continue power transmission.

However, a follow-up failure may occur in another phase (for example, phase a in FIG. 6) during the opening of the HSGS, and depending on the occurrence condition, the induced current has no zero point, that is, a graph of phase c in FIG. A zero point transition phenomenon (zero miss phenomenon) as shown by may occur. The zero-miss state is eliminated if the follow-up failure is removed after 70 ms, for example, in the a-phase.
ms or more. Therefore, in HSGS, it is necessary to interrupt a current of several thousand A under such worst conditions and to endure a high voltage of electrode induction or electrostatic induction applied between the electrodes after the current interruption. Therefore, it is particularly important to verify the shut-off performance in the zero-miss state in the verification tests of various performances required for HSGS, and it is difficult to cope with the conventional test methods and test equipments. , New solutions are needed.

FIG. 7 shows an example of a conventional combined cutoff test circuit for verifying the cutoff performance in a zero-miss state. A short-circuit generator 26 serving as a current of the current source circuit 100 that supplies the zero-miss current is connected to a three-phase transformer 29 via a closing switch 27 and a primary-side reactor 28 for current adjustment. The three-phase transformer 29 has a primary / secondary delta / star configuration and a secondary neutral point connected to the grounding reactor 3 for adjusting the grounding current.
3 is grounded. On the secondary side wiring of the transformer 29, a secondary side A-phase reactor 30 for current adjustment, an auxiliary circuit breaker 35, and a test switch 4 are connected in series to a phase (referred to as an A phase) for generating a zero-miss current. Is short-circuited to the other two phases and grounded. The voltage source circuit 3 is connected between the auxiliary circuit breaker 35 and the test switch 4. One of the other two phases that does not cause a zero error (referred to as phase B) is short-circuited to the other two phases through a secondary B-phase reactor 31 for current adjustment. The remaining one phase (referred to as phase C) has two current adjustments.
An auxiliary input device 34 is connected in series with the secondary C-phase reactor 32, and is short-circuited to the other two phases.

The voltage source circuit 3 includes a main capacitor 21 used for charging, a reactor 23 for adjusting a voltage source circuit current Iv and a transient recovery voltage, a transient recovery voltage adjusting resistor 24, and a transient recovery voltage capacitor. 25, a starting gap 22 for starting a voltage source circuit.

[0006]

By the way, in order to realize the zero-miss state in the short-circuit test circuit, some test circuit systems other than the configuration of FIG. 7 have been proposed. Generally, it is not difficult to realize a test circuit if the circuit is in an ideal state with no loss. In particular, when the HSGS 4 being tested does not generate an interruption arc, the zero miss current determined by the test circuit characteristics other than the arc continues. However, as described above, the HSGS4 is required to interrupt a wide range of arc time close to several ms to 100 ms, and may require a long arc time for interruption. In such a case, the circuit loss due to the arc resistance increases. Then, when the arc voltage is generated by the opening of the contact and the loss due to the resistance increases, the zero-miss state of the current is eliminated and the zero point of the current is reached in a short time, and the zero-miss state required for the test is maintained. Can not.

For example, the current source of the conventional synthesis test shown in FIG. 7 will be described in detail. The current source voltage for supplying the zero-miss current is obtained by switching the test switch from the current source circuit 100 having three phases. 4 is applied. The tap of the transformer 29 of the current source circuit 100 is set to 30 k which can be realized in a general short-circuit test site.
Even if the voltage is selected to be about V, a substantial voltage (back voltage) for maintaining the current arc of the switch under test 4 is determined by circuit analysis.
When the switch 4 under test generated an arc voltage of several kV, the zero-miss current was immediately cut off across the zero line and the arc could not be continued.

[0008] The present invention has been proposed to solve the above-mentioned conventional problems, and the object of the present invention is to provide a UH.
An object of the present invention is to provide a combined switch-off test circuit for implementing a switch-off test equivalent to an actual system in order to perform a performance verification test of various conditions of the HSGS for V in a zero-miss state. That is, the main object of the present invention is to provide a switch having a sufficient back voltage and a small current attenuation even when an arc voltage is generated in the switch under test, thereby obtaining a required zero-miss current. An object of the present invention is to provide a composite cutoff test circuit.

A second object of the present invention is to provide a composite circuit breaker test circuit for a switch having a current source circuit capable of generating the above-mentioned zero-miss current with a simple circuit configuration. It is a third object of the present invention to provide a composite switching test circuit for a switch having a voltage source circuit capable of applying a recovery voltage when the test switch having a simple circuit configuration is opened. A fourth object of the present invention is to provide a switch for a composite cutoff test in which a current is not attenuated due to the arc voltage as described above, and a switch capable of applying a transient recovery voltage generated in an actual system line to the switch under test. It is to provide a circuit. A fifth object of the present invention is to apply a transient recovery voltage generated in an actual system line to a switch under test with a simple configuration by using a part of a current source circuit also as a voltage source circuit. It is an object of the present invention to provide a composite circuit breaker test circuit for a switch.

[0010]

In order to achieve the above-mentioned object, according to the present invention, a first current source circuit and a second current source circuit that generate zero miss current when both circuits are turned on are provided. The first current source circuit and the second current source circuit are connected to both terminals of the switch under test in parallel and with voltages of opposite polarities, and connected to both terminals of the switch under test. A voltage source circuit is connected, and the first current source circuit and the second current source circuit are provided with first and second switching means for turning on and off the test current source to the test switch at different timings. It is characterized by.

[0011] The invention of claim 2 is the same as the invention of claim 1 described above.
The first current source circuit includes a first generator and a first current source circuit.
The closing switch, the first current regulating reactor and the first transformer
Connected in series and one of the secondary sides of the first transformer
One of the test switches is connected to the secondary switch through the auxiliary switch.
One to the other of the test switch, and the first closing switch and
Forming the first opening / closing means with the first auxiliary switch
And a second generator and a second input as the second current source circuit.
Switch, second current regulating reactor, and second transformer in series
And one of the secondary sides of the second transformer
The other of the secondary side is connected to one of the test switches via a switch.
Connected to the other switch under test, the second closing switch and the
The second opening / closing means is formed by the second auxiliary switch.
It is characterized by the following.

According to a third aspect of the present invention, in the second aspect of the invention, as the voltage source circuit, a third transformer is connected to both terminals of a first generator and a first closing switch connected in series,
One terminal on the secondary side of the third transformer is connected to one of the test switches via a capacitor, and the other terminal is connected to the other of the test switches.

According to a fourth aspect of the present invention, in the second aspect of the present invention, as the voltage source circuit, both terminals of a main capacitor, a starting gap, and a reactor connected in series are provided with a waveform adjusting resistor and a waveform adjusting capacitor. It is characterized in that it is connected to both terminals connected in series, and both terminals are connected to both terminals of the switch under test.

According to a fifth aspect of the present invention, in the second aspect of the present invention, the first current source circuit also serves as the voltage source circuit,
The two terminals of the first transformer in which a waveform adjusting resistor and a waveform adjusting capacitor are connected in series to the secondary terminal are connected in parallel, and this connecting terminal is connected to both terminals of the switch under test. Features.

[0015]

According to the first aspect of the present invention having the above-described configuration, by turning on the first and second switching means, the switch under test contains a large amount of DC current from the first current source circuit. It supplies a current of several kA at a relatively high voltage of several tens kV,
The current source circuit also contains a direct current component,
A few kA at a relatively low voltage of several tens kV with a phase delayed by °
And the two are added. In this case, by appropriately setting the voltage and current values supplied from the respective current source circuits, a back voltage of several tens of kV can be obtained, and even if the switch under test generates an arc voltage of several tens of kV, the current is reduced. And the required zero-miss current can be obtained. In order to obtain the zero point of the current, when the current of the second current source circuit is cut off by the second switching means, only the current from the first current source circuit is obtained, and the current zero point can be easily obtained.

According to the second aspect of the present invention, the electric power generated by the first generator is generated.
The mains load is the first current regulating reactor and
And the reactance of the first transformer, etc., the generated voltage
Generates reactive power with a delay of 90 °. No.
1 By properly controlling the closing time of the closing switch,
A current including a transiently large DC component is obtained. Similarly ,
The AC power generated by the second generator is also
By appropriately controlling the input time, the second current adjustment reactor
Transient and large DC component flowing through the
The resulting current is obtained. These two currents are added
Zero miss current flows to the switch under test.

According to the third aspect of the present invention, when a zero-miss current from the first and second current source circuits is flowing through the switch under test, the third transformer constituting the voltage source circuit is connected via the capacitor. Small current flows through the switch under test. When the switch under test cuts off the zero-miss current, the minute current is also cut off, and the recovery voltage from the voltage source circuit is applied to the switch under test.

According to the fourth aspect of the present invention, the transient recovery voltage waveform determined by the transient recovery voltage waveform adjusting resistor and the waveform adjusting capacitor is applied to the switch under test by discharging the electric charge of the main capacitor by the trigger of the starting gap. can do.

According to the fifth aspect of the present invention, the voltage of the first transformer of the first current source circuit is a transient recovery voltage waveform determined by the transient recovery voltage waveform adjusting resistor and the waveform adjusting capacitor is applied to the switch under test. You.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) First Embodiment FIG. 1 Configuration of First Embodiment A first embodiment of the present invention will be described below with reference to the combined cutoff test circuit diagram of FIG. The test circuit of the present embodiment is roughly composed of a first current source circuit 1 as two current sources, a second current source circuit 2, a voltage source circuit 3, and a test switch 4. The first current source circuit 1 has a first generator 5 serving as a power supply, a first switching switch 6, a first current regulating reactor 7, and a first transformer 8 connected in series so as to form one loop. Circuit. A secondary terminal 8a connected to the first transformer 8 so as to increase its secondary voltage.
Is connected to the terminal 9a of the first auxiliary circuit breaker 9 for synthesis test, and the terminal 9b of the first auxiliary circuit breaker 9 is connected to the terminal 14a of the second current source circuit 2. The secondary side terminal 8b of the first transformer 8 is connected to the terminal 13 of the second current source circuit 2.
b.

The second current source circuit 2 includes a second generator 10, a second closing switch 11, a second current regulating reactor 12, and a second transformer, which are separate power sources from the first current source circuit 1. This is a circuit in which devices 13 are connected in series so as to form one loop. A second auxiliary circuit breaker 14 is connected to a secondary terminal 13a which is connected to the second transformer 13 so that the secondary voltage thereof increases. The terminal 14 of the second auxiliary circuit breaker 14 is connected to the second terminal 13a.
a and a terminal 9b on the first auxiliary circuit breaker 9 side of the first current source circuit 2 are connected. On the other hand, the terminal 13b of the second transformer 13 is connected to the terminal 8b of the first transformer 8.

The terminal 9b of the first current source circuit 1 and the terminal 14a of the second current source circuit 2 are connected to the terminal 4a of the switch 4 under test, and the terminal 8b of the first current source circuit 1 and the second current source The terminal 13b of the circuit is connected to the terminal 4b of the switch under test. Further, both terminals 4 a and 4 b of the switch under test are connected to terminals 3 a and 3 b of the voltage source circuit 3. At this time, the primary or secondary side of one of the transformers is set so that the voltages on the primary side of the first transformer 8 and the second transformer 13 are the same and the generated voltages on the secondary side have opposite polarities. Connected with opposite polarity. In the first and second current source circuits 1 and 2, the first closing switch 6 and the first auxiliary circuit breaker 9 serve as first switching means, and the second closing switch 11 and the second auxiliary switching circuit The container 14 corresponds to a second opening / closing means.

In the voltage source circuit 3, a connection point 6a between the first switching switch 6 and the current regulating reactor 7 constituting the first current source circuit 1 and a terminal 5b of the first generator 5 are provided.
Are connected to the terminals 15a and 15b of the third transformer 15, respectively. A third terminal 15c is connected to the third transformer 15 so that the voltage on the secondary side is gradually increased.
The secondary terminal 15c is connected to the terminal 16a of the capacitor 16, and the terminal 16b of the capacitor 16 is connected to the terminal 4a of the switch 4 under test. The terminal 15d on the secondary side of the third transformer 15 is connected to the terminal 4b of the switch under test 4 and grounded. In this case, taps are selected for the secondary side voltage of the third transformer 15 so that a required recovery voltage can be supplied.

Operation of the First Embodiment The operation of the composite cutoff test circuit of the present embodiment configured as described above will be described with reference to FIG.

When the AC voltage of each of the generators 5 and 10 in the first and second current source circuits 1 and 2 reaches a zero point, the first switch 6 is turned on. At this time, on the secondary side of the first transformer 8, a current i1 including a DC component of nearly 100%
Flows, and this also flows to the test HGSG4. Next, the first
When the voltage generated by the generator 5 and the second generator 10 reaches the next zero point after the closing of the first closing switch 6, the second closing switch 1
Input 1. When the second closing switch 11 is turned on, the second
Similarly, a current i2 including a DC component near 100% flows from the current source circuit 2. From this time, a zero-miss current i0 obtained by combining the currents i1 and i2 and a minute current from the voltage source circuit 3 flow through the switch 4 under test. After the zero miss current i0 starts to flow, a cutoff command is given so that the contact of the switch under test 4 is opened. The zero miss current i0 continues to flow for a while,
At a time such that the arc time becomes equal to or longer than a predetermined 80 ms, the second auxiliary circuit breaker 14 is opened to create a zero point in the zero miss current i0, and then the first auxiliary circuit breaker 9 is opened to open the test switch 4
At the same current zero point. At this time, the minute current supplied from the voltage source circuit 3 connected to the test switch 4 is also cut off at the same time, and the recovery voltage V
R is applied to the test switch 4 to complete the test.

As described above, by using this embodiment,
Special test and verification equivalent to the actual system can be performed.

(2) Second Embodiment--FIG. 3 Configuration of the Second Embodiment The second embodiment is directed to the interruption of electromagnetic induction current in the combined cutoff test circuit of the present invention. That is, as shown in FIG. 3, the second embodiment has a voltage source circuit 3 in which the transformer and the capacitor of the first embodiment are combined.
Instead of this, a voltage source circuit 20 mainly composed of a capacitor applied to a conventional synthetic test method for interrupting a large current is employed. In this voltage source circuit 20, a main capacitor 21, a starting gap 22, and a reactor 23 are connected in series, and the other terminal 23b of the reactor 23 is connected to a terminal 4a of the switch 4 under test. The terminal 23b of the reactor 23 is also connected to a series circuit of a transient recovery voltage waveform adjusting resistor 24 and a waveform adjusting capacitor 25. The terminal 25b of the capacitor 25 for waveform adjustment, the terminal 21b of the main capacitor 21, and the terminal 4b of the switch under test 4 are connected to each other and are grounded.

Operation of the Second Embodiment The operation of the second embodiment will be described with reference to FIG. The difference from the first embodiment is that the time immediately before the zero miss current i0 reaches the zero point is detected, and the charge of the main capacitor 21 that has been charged in advance is discharged by the trigger of the starting gap 22. As a result, mainly the transient recovery voltage waveform adjusting resistor 24 and the waveform adjusting capacitor 2
A transient recovery voltage waveform equivalent to that of the system determined by 5 is applied to the switch under test 4 to perform test verification. In this case, in the second embodiment, the recovery voltage region is a DC voltage different from the AC voltage of the actual system, but it is said that there is no problem with the equivalence in a combined test of a circuit breaker or the like. However, if a vibrating recovery voltage is required, an AC voltage can be applied by connecting a commercial frequency resonance reactor in parallel with the main capacitor 21.

In the second embodiment having the above-described structure, the capacitor can be charged independently of the generator, and the starting gap can be started immediately before the zero-miss current reaches the zero point.

(3) Third Embodiment--FIG. 5 The third embodiment is a composite cutoff test circuit for interrupting electromagnetic induction current as in the second embodiment of the present invention. The difference between the third embodiment and the second embodiment is that, as shown in FIG. 5, after the switch under test 4 interrupts the zero-miss current i0, the voltage source circuit 20 for applying the recovery voltage VR is switched to the first current. This is the point shared with the source circuit 1. That is, in the third embodiment, both terminals of the transient recovery voltage waveform adjusting resistor 24 and the waveform adjusting capacitor 25 connected in series are connected in parallel with both terminals of the first transformer 8.

Since the third embodiment having such a configuration can be regarded as a modification of the direct test circuit realized by the combination of the transformers, the performance of the test is extremely easy as compared with the second embodiment. However, it has a characteristic that the condition of the voltage source circuit is limited by the output of the transformer. Since the operation of the third embodiment is similar to that of the second embodiment, detailed description is omitted. However, the voltage determined by the elements of the voltage source circuit 20 after the interruption of the zero-miss current i0 is automatically adjusted. The test is applied in the same way and a test equivalent to the actual system is possible.

[0032]

As described above, according to the present invention, the first and second current sources are connected in parallel so that they have voltages of opposite polarities. It is possible to provide a composite switchgear test circuit capable of realizing the performance verification of various conditions in the zero-miss state by a cutoff test equivalent to an actual system.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a test circuit for shutting down a zero-miss synthesis in a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of operation phenomena of the zero-miss synthesis cutoff test circuit in the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a test circuit for shutting down a combination of zero errors according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of operation phenomena of a zero-miss synthesis cutoff test circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a test circuit for shutting down synthesis of zero errors according to a third embodiment of the present invention.

FIG. 6 is an explanatory diagram showing an example of a zero point transition phenomenon occurring in a UHV system.

FIG. 7 is a conventional circuit diagram of a composite cutoff test for verifying the cutoff performance of a zero-miss state.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st current source circuit 2 ... 2nd current source circuit 3 ... Voltage source circuit 4 ... Test switch 5 ... 1st generator 6 ... 1st closing switch 7 ... 1st current adjustment reactor 8 ... 1st Transformer 9 ... First auxiliary breaker 10 ... Second generator 11 ... Second closing switch 12 ... Second current regulating reactor 13 ... Second transformer 14 ... Second auxiliary breaker 15 ... Third transformer 16 ... Capacitor 20 ... Voltage source circuit 21 ... Main capacitor 22 ... Start gap 23 ... Reactor 24 ... Waveform adjustment resistor 25 ... Waveform adjustment capacitor

──────────────────────────────────────────────────続 き Continued on the front page (72) Katsumi Suzuki 2-1 Ukishima-cho, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Hamakawasaki Plant, Toshiba Corporation (72) Inventor Shoji Yamashita 2-4, Suehirocho, Tsurumi-ku, Yokohama-shi, Kanagawa (56) References JP-A-58-102176 (JP, A) JP-B-56-47510 (JP, B2) JP-B-60-10267 (JP, B2) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G01R 31/00, 31/327, 31/333 H01H 9/54, 33/00

Claims (5)

(57) [Claims] 1. A first current source circuit and a second current source circuit that generate a zero-miss current when both circuits are turned on are connected in parallel and have voltages of opposite polarities. And a second current source circuit are connected to both terminals of the switch under test, and a voltage source circuit is connected to both terminals of the switch under test, and are connected to the first current source circuit and the second current source circuit. A first test circuit comprising a first switch and a second switch for turning on and off a test current source to a test switch at different timings. 2. The first current source circuit includes a first generator, a first closing switch, a first current regulating reactor, and a first transformer connected in series, and a secondary side of the first transformer. One of
On one of the test switch via a first auxiliary switch, the other of the secondary side connected to the other of the test switch, the first turned open
The first switching means by means of a closing device and the first auxiliary switch;
A second generator, a second closing switch, a second current regulating reactor, and a second transformer are connected in series as the second current source circuit, and a second side of the second transformer is connected to the second transformer. One is connected to one of the test switches via a second auxiliary switch, and the other of the secondary side is connected to the other of the test switches, and the second closing switch and the second switch are connected to each other .
The circuit according to claim 1, wherein said second switching means is formed by an auxiliary switch . 3. A terminal connected to both terminals of a first generator and a first closing switch connected in series and a third transformer as the voltage source circuit, and one terminal on a secondary side of the third transformer. 3. The circuit of claim 2, wherein one of the test switches is connected to one of the test switches via a capacitor, and the other terminal is connected to the other of the test switches. 4. As the voltage source circuit, both terminals of a main capacitor, a starting gap, and a reactor connected in series are connected to both terminals of a waveform adjusting resistor and a waveform adjusting capacitor connected in series, and 3. The circuit of claim 2, wherein said switch is connected to both terminals of said switch under test. 5. The first current source circuit also serves as the voltage source circuit, and two terminals in which a waveform adjusting resistor and a waveform adjusting capacitor are connected in series to a secondary terminal of the first transformer are connected in parallel. 3. The circuit according to claim 2, wherein said connection terminal is connected to both terminals of the switch under test.