JP3096556B2 - DRAM refresh clock generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM refresh clock generation circuit, and more particularly to a refresh clock selection.

[0002]

2. Description of the Related Art A DRAM (Dynamic Randum Access Memory) has been widely used as a large-capacity semiconductor memory. In this DRAM, it must be refreshed every predetermined time in order to maintain the storage state. For this reason, a refresh clock for determining the refresh timing is required.

On the other hand, a DRAM is often formed as a single semiconductor chip by itself, and in such a case, the DRAM is externally used for a semiconductor integrated circuit (LSI) containing a processing circuit. If the refresh circuit is not built in the semiconductor chip of the DRAM, a refresh circuit for refreshing the DRAM is also built in the LSI.

On the other hand, since low power consumption is required in many electronic circuits, a normal operation mode in which normal operation is performed and power consumption is minimized without performing any operation other than maintenance of memory contents. Power down mode. In the power down mode, only the refresh circuit is operated and the operation of other circuits is stopped. Further, in order to reduce power consumption, the refresh cycle is made as long as possible in the power down mode.

Therefore, in the refresh circuit, it is necessary to generate a refresh clock in the power down mode in addition to the refresh clock in the normal operation mode. The refresh clock in the normal operation mode is
In order to achieve a speed sufficient to execute various processes which are the main purpose of the LSI, the clock is generated using a clock of a main oscillator (usually a crystal oscillator) having a relatively high frequency which is the same as the operation clock of the CPU. On the other hand, the refresh clock at power down has a relatively low frequency,
A refresh clock is generated using a sub-oscillator using a resistor (for example, a CR relaxation oscillator). As described above, when the sub oscillator is used, the operation of the main oscillator can be stopped in the power down mode, and the power consumption can be reduced.

Here, in the power down operation mode, there is a case where it is desired to use the refresh clock from the main oscillator without using the refresh clock from the sub oscillator. For example, in a low-priced DRAM such as an audio grade DRAM, the guaranteed value of the refresh cycle is not satisfied in a long cycle such as the refresh clock from the sub-oscillator, and the refresh clock from the main oscillator must be used. It is conceivable that the required refresh clock is generated by the sub-oscillator.
Since the R relaxation type oscillator has high harmonic energy, an excessively high oscillation frequency is not preferable in terms of unnecessary radiation.

Therefore, in an LSI incorporating a DRAM refresh circuit, it is possible to select whether to output a clock from a main oscillator or a clock from a sub-oscillator as a refresh clock in a power down mode. There is a need to.

[0008]

In order to set the refresh clock in the power down mode in the LSI, a switching signal must be input from the outside. For this reason, it is necessary to provide a dedicated terminal for inputting the switching signal in the LSI. LSI
In, the number of terminals is an important factor in determining the size of the LSI and the like, and there is a strong demand to reduce the number of terminals as much as possible.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a DRAM refresh clock generating circuit capable of switching a refresh clock during power saving without increasing the number of terminals.

[0010]

SUMMARY OF THE INVENTION The present invention relates to a circuit for generating a refresh clock for DRAM refresh which is built in a semiconductor integrated circuit, and which generates a main clock signal of a relatively high frequency. When a capacitor is connected to a sub-clock generation circuit that generates a sub-clock signal of a relatively low frequency using an external capacitor, a capacitor connection terminal for connecting the external capacitor, and a capacitor connection terminal Decision switching means for selecting a sub clock signal from a CR oscillation circuit including this capacitor, and selecting only the main clock when the voltage of the capacitor connection terminal is fixed to one of a high level and a low level. Select the refresh clock according to the connection state to the capacitor output terminal And wherein the door.

Further, when selecting the sub clock, an external capacitor and a resistor are connected to the capacitor connection terminal.

Further, the determination switching means is arranged such that when the level of the capacitor connection terminal does not change, the output level is fixed to one side, and when the level of the capacitor connection terminal repeats a high level and a low level, the output changes to the other side. , And a main clock or a sub clock is selected according to the output of the latch circuit.

[0013]

As described above, the judgment switching means detects whether or not a capacitor is connected to the capacitor connection terminal, and accordingly selects whether to use only the main clock or the main clock and the sub clock. I do. Therefore,
There is no need to input a signal for this setting, and the number of terminals of the semiconductor integrated circuit can be reduced.

The sub-clock generating circuit generates a clock by using charging and discharging of a capacitor. When this circuit operates, the voltage of the capacitor connecting terminal fluctuates. Therefore, by detecting this variation, the connection of the capacitor can be easily detected.

With such a circuit, it is possible to set whether or not to use a sub clock as a refresh clock without providing a dedicated input terminal when the semiconductor integrated circuit is powered down.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a functional configuration of the present invention. A refresh clock generating circuit according to the present embodiment includes a crystal oscillator (main clock generating circuit) 10, a CR oscillator (sub clock generating circuit) 12, a judgment switching circuit. (Judgment switching means) 14.

An external crystal oscillator Xtal is connected to the crystal oscillator 10 and outputs a signal B.
This signal B is a main clock having a relatively high frequency in the operation state of the crystal oscillator 10. On the other hand, the CR oscillator 12 has
The capacitor C and the resistor R or the power supply voltage VDD are connected via the CR terminal, and the signal D is output. This signal B
Is an auxiliary clock of a relatively low frequency when the CR oscillator 12 is operating.

At the time of power down, the CR oscillator 1
When the sub-clock from 2 is used as the refresh clock C which is the output of this circuit, the capacitor C and the resistor R are connected to the CR terminal CR. On the other hand, when the sub clock from the CR oscillator 12 is not used as the refresh clock, the power supply VDD is connected to the CR terminal CR.

The signals B and D are input to a decision switching circuit 14. In addition, a signal A indicating whether or not the power down mode is set is also input to the determination switching circuit 14. Then, the determination switching circuit 14 selects either the signal B or D and outputs it as the refresh clock C. Further, the determination switching circuit 14 feeds back a signal E regarding the determination result to the crystal oscillator 10 and the CR oscillator 12.

Next, the determination operation in the determination switching circuit 14 will be described with reference to the flowchart of FIG.
The determination switching circuit 14 first determines whether the signal A is "H" (S1). If it is not "H", since it is in the normal operation mode, the signal B from the crystal oscillator 10 is adopted, this is output as the refresh clock C, and "H" is output to the signal E (S2), and the signal E is output to S1. Return. Further, upon receiving "H" of the signal E, the CR oscillator 12 stops its oscillating operation.

When the signal A is "H" in S1, the power down mode is set. Therefore, the determination switching circuit 14 detects whether the signal D becomes "L" (S3). That is, when the capacitor C and the resistor R are connected to the CR oscillator 12,
Is operable, and the output signal D from the CR oscillator 12 is
Repeats "H" and "L". On the other hand, CR oscillator 12
Power supply potential V without connecting capacitor C and resistance R
When DD is input, the CR oscillator 12 is inoperable, and the output signal D from the CR oscillator 12 is “H”.
, And “L” is not output from here. Therefore,
By the determination in S3, it can be determined whether or not to use the signal from the CR oscillator 12.

In S3, if "L" is not detected in the signal D, the process proceeds to S2 and the signal B is adopted as the refresh clock C. On the other hand, in S3, the signal D
When "L" is detected at the step S4, the signal D from the CR oscillator 12 is output as the refresh clock C, and the signal E is output "L" (S4). Crystal oscillator 1
0 receives the “L” of the signal E and stops the oscillation.

Then, it is determined whether or not the signal A is "H" (power down mode) (S5). If the signal A is "H", the process returns to S4.
Is output as the refresh clock C. If the signal A becomes "L" in S5, the process returns to S1 and the operation is repeated.

As described above, according to the present embodiment, the capacitor C and the resistor R are connected to the CR terminal CR or the power supply V
Whether to use the CR oscillator 12 can be determined by connecting to the DD. Therefore, there is no need to input a signal as to whether or not to use the CR oscillator, and a terminal for this is not required.

FIGS. 3 and 4 show specific circuits of the DRAM refresh clock generation circuit. FIG. 3 shows a circuit in which a capacitor C and a resistor R are connected to a CR terminal CR, and a sub-oscillator (CR oscillator 12) is used at the time of power-down. On the other hand, FIG. 4 shows a circuit in which the CR terminal CR is connected to VDD, and the main oscillator (crystal oscillator 10) is used even at the time of power down.

This LSI has three terminals PDWN, X
IN, XOUT, and CR are provided. The crystal oscillator Xtal is connected between the terminals XIN and XOUT. Note that both terminals XIN and XOUT are connected to ground by predetermined capacitors C1 and C2. The terminal XIN is connected to one input terminal of the NAND gate ND1, and the output terminal of the NAND gate ND1 is connected to the terminal XO.
Connected to UT. Therefore, if the input signal to the other input terminal of the NAND gate ND1 is “H”, the NAND gate ND1 functions as an inverter. Therefore, both ends of the crystal oscillator Xtal are connected by an inverter, and this circuit oscillates at a frequency determined by the crystal oscillator Xtal. The output terminal of the NAND gate ND1 is connected to an inverter INV1. The output of the NAND gate ND1 is inverted and output as a signal B.

The source of a P-channel FET is connected to the CR terminal CR, and the drain of this FET is connected to a power supply VDD. The CR terminal CR is connected to an FET
And three other inverters INV2, INV3, INV4
And is connected to one input terminal of the NAND gate ND2. The output terminal of the NAND gate ND2 is connected to the gate of the FET. If the input to the other input terminal of the NAND gate ND2 is “H”, the NAND gate ND2 functions as an inverter. Therefore, the level of the CR terminal CR is directly applied to the gate of the FET. Since the FET is turned on when its gate potential is at L, when the CR terminal is at "L", the FET is turned on and the CR is turned on.
Current is supplied to the terminal. And CR terminal CR
Is "H", the FET is turned off.

Therefore, in the configuration of FIG. 3, when the CR terminal CR is "L", the FET is turned on, the external capacitor C is charged, and the potential of the CR terminal CR rises. And C
When the potential of the R terminal CR rises sufficiently and the gate input of the FET becomes “H”, the FET is turned off, and the charge stored in the external capacitor C is discharged by the external resistor R.
The potential of the CR terminal CR decreases. In this way, CR
The potential of the terminal CR repeatedly rises and falls, and oscillation occurs. The output from the inverter INV3 is the output signal D of the CR oscillation circuit 12.

On the other hand, in the configuration of FIG. 4, the CR terminal CR is raised to the power supply voltage VDD. Thus, the gate terminal of the FET is fixed at "H", the FET remains off, and the output signal D is fixed at "H".

The output signal D of the CR oscillator 12 is input to one input terminal of a NAND gate ND3, and the output of the NAND gate ND3 is input to one input terminal of a NAND gate ND4. Further, the output of the NAND gate ND4 is input to the other input terminal of the NAND gate ND3, and the signal A is input to the other input terminal of the NAND gate ND4. Then, the signal E is output from the output terminal of the NAND gate ND4. Therefore, these two NAND gates ND3,
The ND4 functions as a latch circuit that receives the signal A and the signal D.

When the signal A is at L, the output of the NAND gate ND4, that is, the signal E is fixed at "H" regardless of the state of the signal D. On the other hand, when the signal A is “L”,
When the signal D becomes "L", the output of the NAND gate ND4, that is, the signal E becomes "L", and even if the signal D changes thereafter, the signal E does not change. When the signal D is fixed at “H”, the signal E maintains the previous state. For example, when the signal D is fixed at “H” and the signal A changes from “L” to “H”, the signal E remains at “H”.

The signal E is supplied to the NAND gate ND
1 is input to the other input terminal. Therefore, when the signal E is “H”, the crystal oscillator 10 operates, and when the signal E is “L”, the operation of the crystal oscillator 10 stops.

Further, the signal E is input to the other input terminal of the NAND gate ND2 via the inverter INV5. Therefore, the output of the NAND gate ND2 is fixed to "H" when the signal E is "H", and the oscillation of the CR oscillator 12 is stopped.

The circuit further includes a NAND gate N
D5, ND6, and ND7 are provided, so that either the signal B or D is selected and output as the refresh clock C. That is,
The signal B is input to the NAND gate ND5, and the signal E is also input to the NAND gate ND5. Therefore, the NAND gate ND5 outputs the signal B when the signal E is "H", and the output is fixed at "H" when the signal E is "L". On the other hand, the signal D is input to the NAND gate ND6,
The signal E is inverted and input to the NAND gate ND6. Therefore, the NAND gate ND6 outputs the signal D when the signal E is "L", and the output is fixed at "H" when the signal E is "H". And the NAND gate ND
5 and ND6 are output as the refresh clock C via the NAND gate ND7.

Therefore, when the signal E is "H", the signal B is output as the refresh clock C, and when the signal E is "L", the signal D is output as the refresh clock C.

As described above, in the circuits of FIGS. 3 and 4, when signal A is at "L", that is, in the normal operation mode, signal E is fixed at "H" and NAND gate ND
Since the input to the other input terminal of “1” is “H”, the crystal oscillator 10 operates, and the output signal B from the crystal oscillator 10 is output as the refresh clock C. At this time, the input to the other input terminal of the NAND gate ND2 becomes “L”, and the operation of the CR oscillator 12 is stopped.

Next, in the circuit of FIG. 3, when the signal A becomes "H", "L" of the CR terminal CR is detected, and the signal E becomes "L". Therefore, the input to the other input terminal of the NAND gate ND1 becomes “L”, and the operation of the crystal oscillator 10 is stopped. Then, the input to the other input terminal of the NAND gate ND2 becomes “H”, the CR oscillator 12 operates, the signal D is selected and output as the refresh clock C. As described above, in the circuit of FIG. 3, the output from the CR oscillator 12 in the power down mode is selected and output as the refresh clock C.

Next, in the circuit of FIG.
R is fixed at "H". Then, the signal A becomes "L"
The signal E remains "H" even when the signal E changes to "H". Therefore, as in the case where the signal A is “L”, the crystal oscillator 10
Is output as the refresh clock C.

As described above, according to the present embodiment, by connecting the capacitor C and the resistor R to the CR terminal CR, or by raising this to the power supply potential VDD, the CR oscillator 12 (sub-oscillator) at power down. Is used or not. Therefore, a signal input for this determination is unnecessary, and a terminal therefor is not required.

The above-described circuit is an example of one configuration, and various modifications are possible. For example, "H" and "L" of the signal can be appropriately inverted, so that the type of the gate can be changed. Some of the inverters (for example, INV2 and INV3) are for power amplification and are not logically necessary. Further, when the sub-oscillator is not used, the CR terminal CR may be fixed to the ground potential, or a resistor R may be built in.

[0041]

As described above, according to the present invention,
The determination switching means detects whether or not a capacitor is connected to the capacitor connection terminal, and selects whether to use only the main clock or to use the main clock and the sub clock in accordance with the detection. Therefore, there is no need to input a signal for this setting, and the number of terminals of the semiconductor integrated circuit can be reduced.

The sub-clock generating circuit generates a clock by using charging and discharging of a capacitor. When this circuit operates, the voltage of the capacitor connecting terminal fluctuates. Therefore, by detecting this variation, the connection of the capacitor can be easily detected.

With such a circuit, it is possible to set whether or not to use a sub clock as a refresh clock without providing a dedicated input terminal when the semiconductor integrated circuit is powered down.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a functional configuration of an embodiment.

FIG. 2 is a flowchart for explaining the operation of the embodiment.

FIG. 3 is a circuit diagram when a CR oscillator is used.

FIG. 4 is a circuit diagram when a CR oscillator is not used.

[Explanation of symbols]

 10 Crystal oscillator 12 CR oscillator 14 Judgment switching circuit C External capacitor R External resistor

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-45072 (JP, A) JP-A-5-307882 (JP, A) JP-A-64-52292 (JP, A) JP-A-5-52292 291915 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 11/34 350-381

Claims (3)

(57) [Claims] 1. A circuit which is built in a semiconductor integrated circuit and generates a refresh clock for DRAM refresh, wherein a main clock generating circuit for generating a main clock signal of a relatively high frequency and an external capacitor are used. Then, when a sub-clock generation circuit for generating a sub-clock signal of a relatively low frequency, a capacitor connection terminal for connecting the external capacitor, and a capacitor connected to the capacitor connection terminal,
Judgment switching means for enabling selection of a sub-clock signal from a CR oscillation circuit including this capacitor, and selecting only the main clock signal when the voltage of the capacitor connection terminal is fixed to one of a high level and a low level And a refresh clock selection circuit for selecting a refresh clock according to a connection state to a capacitor output terminal. 2. The DRAM refresh clock generating circuit according to claim 1, wherein an external capacitor and a resistor are connected to the capacitor connection terminal when the sub clock is selected. 3. The circuit according to claim 2, wherein the determination switching means fixes the output level to one side when the level of the capacitor connection terminal does not change,
A DRAM characterized in that it includes a latch circuit whose output is fixed to the other side when the level of the capacitor connection terminal repeats high level and low level, and selects a main clock or a sub-clock according to the output of this latch circuit. Refresh clock generation circuit.