JP3094314B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an A / D converter that uses an internal A / D converter with a smaller number of bits to perform D conversion.

[0002]

2. Description of the Related Art At present, successive approximation type A / D converters of 20 bits, 18 bits, etc. are expensive. Therefore, it is conceivable that an A / D converter having a smaller number of bits, for example, 8 bits, performs its function. . FIG. 5 shows a circuit of this type, in which a 4-bit A / D converter 1
When a 4-bit D / A converter 2, a differential amplifier 3 for amplification degree 2 ^4, an A / D converter 4, is configured more output register 5 of 8 bits, MS of output register 5
The conversion signal of the A / D converter 1 is loaded into the 4 bits on the B side, the conversion signal of the A / D converter 4 is loaded on the 4 bits on the LSB side, and an A / D conversion output of 8 bits is obtained.

As shown in FIG. 6, a 4-bit A / A
The A / D converted signal from the D converter 1a is loaded into the 4 bits on the MSB side of the output register 5a and held in the register 6, and the 4 bit D / A converted signal from the D / A converter 2a is sent to the differential amplifier 3a. feedback to amplifies a difference voltage between the input signals to the 2 ⁴ times a / D conversion to LS
It is also known to load the four bits on the B side to generate an 8-bit A / D conversion output. A similar conversion method is well known for a signed A / D converter for converting an input signal that fluctuates between positive and negative.

[0004]

[SUMMARY OF THE INVENTION However, in these cases, in order to convert further 4 bits amplified output of 2 ⁴ of the differential amplifier 3, 3a, 8 bits or more accurate as overall accuracy of the circuit, i.e., about Accuracy of ± 0.2% is required. That is, the 8-bit resolution is 0.125 V for a 4 V input signal, and the error is 0.08 V if the accuracy is ± 0.2% with respect to 4 V, which is an allowable error range for 0.125 V. Inside. Otherwise, the LSB side 4-bit input signal mixed with noise at a non-negligible level will be A / D converted. Therefore, the noise mixing, the power supply circuit or the amplifier (especially the resistance value of the resistance element)
A high-precision circuit corresponding to the bit is required.

In view of the above, the present invention uses an A / D converter having a smaller number of bits to perform A / D conversion of a desired number of bits without excessively increasing the requirement for the overall accuracy of the circuit. It is an object of the present invention to provide an A / D converter that can be performed by using the A / D converter.

[0006]

SUMMARY OF THE INVENTION The present invention achieves this object by providing a positive voltage input signal according to claim 1 to n.
In an A / D converter that performs A / D conversion with bits, X
Bit internal A / D converter and (X <n), amplified input signal and n-bit D / A converter N-1 stage while 2 ^XY multiplied by one multiplication from 2 ^XY double the voltage difference between the output signal A differential amplifier circuit for amplifying by switching degrees and (Y is the number of bits defining the amplitude that can be A / D converted with respect to the X-bit internal A / D converter ignoring the effect of the error voltage generated in the differential amplifier circuit) , N is n / (X−Y) rounded-up integers), the input signal is supplied to the internal A / D converter with the amplification factor of 1 and the amplification factor of the N−1 stages of the differential amplifier circuit is switched. A / D switching to N stages sequentially with supply of amplified output
A conversion input selection circuit for supplying a conversion input signal; and an A / D conversion input signal
A subtraction circuit for subtracting an amplitude almost half of an amplitude corresponding to a bit, an X-bit shift register into which an output signal of an internal A / D converter is loaded, and a D / A conversion input to an n-bit D / A converter An n-bit shift register for supplying a signal and an output signal of the X-bit shift register are directly loaded from the MSB side into the n-bit shift register when the first stage of the conversion input selection circuit is selected,
Each time the second and subsequent stages are selected, the output signal of the n-bit shift register and the output signal of the X-bit shift register are changed by n
The shift amount of the bit shift register from the MSB side is X
An adder for adding while increasing by Y bits and loading the result into an n-bit shift register, and after selecting N stages, an output signal of the n-bit shift register is used as an A / D conversion output. I do.

When the A / D conversion is performed with a sign, the internal A / D converter with a sign of X bits and (X
<N), the D / A conversion input signal having the sign bit is
/ A D / A converter n bits A conversion, amplification degree N-1 stage while 2 ^XY multiplied by one multiplication from 2 ^XY double the voltage difference between the input signal and the n-bit D / A converter output signal (Y is an X-bit internal A / D converter, the number of bits defining an amplitude that can be A / D converted while ignoring the influence of an error voltage generated in the differential amplifier, N is n / (X−Y) rounded-up integer), supply of the input signal to the internal A / D converter with the amplification factor of 1 and amplification by switching the amplification factor of N−1 stages of the differential amplifier circuit A / D that sequentially switches to N stages with output supply
A conversion input selection circuit for supplying a conversion input signal;
An X-bit signed shift register loaded as a complement with the logical value of the sign bit set to 0 when the output signal of the / D converter is positive and the logical value of the sign bit set to 1 when the output signal is negative, and D / A conversion When the input signal is positive, the logical value of the sign bit is 0, and when the input signal is negative, the n-bit signed shift register is loaded as a complement with the logical value of the sign bit being 0, and the output of the X-bit shift register At the time of selecting the first stage of the conversion input selection circuit, the signal is directly loaded into the n-bit shift register from the MSB side, and the output signal of the n-bit shift register is selected every time the second and subsequent stages are selected,
The output signal of the X-bit shift register is shifted while increasing the shift amount from the MSB side of the n-bit shift register by XY bits by XY bits, and all of the shifted bits are the logical values of the sign bits. While adding n
And an adder for loading the shift register of bits, and after selecting N stages, an output signal of the shift register of n bits is used as an A / D conversion output.

[0008]

In the case of the first aspect of the present invention, in the first A / D conversion, the conversion input selection circuit supplies the input signal to the subtraction circuit directly or with an amplification degree of 1, and subtracts half of the amplitude corresponding to Y bits. Then, A / D conversion is performed by the internal A / D converter. This A / D conversion signal is loaded into an X-bit shift register, and then loaded into an n-bit shift register via an adding means. This loaded signal is D /
Is D / A converted by the A converter, is supplied to the differential amplifier circuit as the second A / D for converting the difference voltage between the input signal is amplified by 2 ^XY magnification.

At this time, Y bits are re-converted by being shifted by Y bits less than X and added to an n-bit shift register. The first A /
Due to the amplitude subtraction at the time of D conversion, even a small-level A / D conversion input signal that may cause an error is amplified by ^2XY times and converted again at the time of the second A / D conversion. Hereinafter, the amplification degree of the differential amplifier circuit is set to 2 ^XY so that the amplitude corresponding to XY bits becomes the full range of the internal A / D converter each time.
A / D by XY bits within a positive dynamic range by amplitude subtraction each time.
After the conversion and the N-th A / D conversion, an n-bit A / D conversion output is obtained in the n-bit shift register.

In the case of the invention of claim 3, first, the first A / A
In the D conversion, the A / D conversion is performed by the internal A / D converter while the conversion input selection circuit keeps the input signal. This A / D conversion signal is loaded into an X-bit shift register, and then loaded into an n-bit shift register via an adding means. This loaded signal is converted by the D / A converter to D / A
A converted is supplied to the differential amplifier circuit as the second A / D for converting the difference voltage between the input signal is amplified by 2 ^XY magnification. At this time, even if a negative voltage error occurs, a signed A / D
By the conversion, an A / D conversion output is reliably obtained.

At this time, n bits are shifted by XY bits.
By being added to the bit shift register, the Y bits are reconverted. M of n-bit shift register
Since all bits shifted from the SB side are added while being assigned with the logical value of the sign bit, the output signal as the negative complement of the internal A / D converter is assigned with the logical value of 1 and added. For this reason, a subtraction is performed. Hereinafter, the amplification degree of the differential amplifier circuit is multiplied by 2 ^XY times, and A / D conversion is performed for each XY bit. After the Nth A / D conversion, the n-bit shift register stores the n-bit A / D A converted output is obtained.

[0012]

1 shows an A / D converter of n = 20 bits for a positive voltage input signal according to an embodiment of the present invention. A1 is 2 ^XY = 2 ⁴ times the amplification degree of the differential amplifier, A2
~A4 are cascade-connected, respectively 2 ⁴ times the amplifier, two ^quadruple differential output by the amplifiers (2
⁴⁾ the amplification of up to ⁴ times to 2 ⁴ times by one multiplication by N-1 = 4
A differential amplifier circuit that switches the degree of amplification is configured in stages. 1
Reference numeral 8 denotes a conversion input selection circuit that directly selects an input signal and outputs an A / D conversion input signal that is amplified by switching the amplification degree to N-1 stages and sequentially switching to N stages. The differential amplifier A1 is
A difference signal between an input signal that changes in the range of 0 to 4 V around +2 V and an output signal of the D / A converter 10 of 20 bits is amplified.

Reference numeral 11 denotes a high-speed internal A / D converter such as a flash type and a successive approximation type of X = 8 bits. 12
Is a subtraction circuit for converting the A / D conversion input signal into a maximum input signal corresponding to 8 bits and subtracting half of the amplitude corresponding to Y = 4 bits. 13 is the internal A /
This is an 8-bit shift register to which an output signal of the D converter 11 is loaded. Reference numeral 14 denotes a D / A converter 10 which is loaded with an A / D conversion signal and converts the input signal for D / A conversion into a signal.
To be supplied serially or in parallel for speeding up
It is a bit shift register. Reference numeral 15 denotes a 1-bit full adder type addition circuit which has an internal carry processing function and has an addition control circuit 15a. The addition control circuit sequentially takes out the output signals from the LSB sides of the shift registers 13 and 14 and adds them to the addition circuit 15 one bit at a time.
The data is sequentially input one bit at a time from the SB side. At this time, the output signal of the shift register 13 is applied to the amplification degree selection circuit 1
8 is not shifted when the first stage is selected, and when the second and subsequent stages are selected, the XY is sequentially selected from the MSB side for each selection.
= Addition by increasing the shift amount by 4 bits.

Reference numeral 16 denotes a 20-bit output shift register which sequentially receives the added outputs and outputs an A / D conversion signal at the time of final A / D conversion. Reference numeral 17 denotes a controller for controlling these components. The controller 17 causes the conversion input selection circuit 18 to sequentially perform a selection operation, causes the internal A / D converter 11 to perform a conversion operation each time, and further adds to the addition control circuit 15a. A control operation or the like is performed.

As described above, the internal A / D converter 1
1 is set to X = 8 bits in consideration of the price, and the error of the differential amplifier circuits A1 to A4 due to the resistance or drift or noise (especially the error due to the resistance error) is 1%.
If it can be set to the degree, ± 0.02V for 4V
Error may occur. On the other hand, the maximum input signal 4V
, The resolution of the 8-bit internal A / D converter 11 is 4V / 2 ⁸ = 0.015V. Therefore, if Y = 4 bits is set as the number of bits defining the input signal amplitude that can ignore the influence of the error amplitude, the amplitude becomes 0.01
5V × 2 ⁴ = 0.25V, which can be made sufficiently large with respect to the error of ± 0.02V by taking into account the conversion error of the internal A / D converter. As a result, the A / D conversion is performed with high precision at an 8-bit resolution, and the A / D conversion signal for the fourth bit from the fifth bit onward, which may cause an error, is amplified and re-converted. Further, the subtraction circuit 12 subtracts the amplitude corresponding to の of 0.25 V for the four bits, thereby re-converting the A / D conversion input signal which has become negative in the range of −0.125 V. As a result, the occurrence of errors is avoided. Correspondingly, N is set to 5 from n / (XY),
The number of amplifiers is N-1 = 4.

The operation of the A / D converter thus configured will be described with reference to FIG. 2V is applied to the differential amplifier A1.
Are sequentially input. First, in the first A / D conversion, the conversion input selection circuit 18 directly supplies the input signal to the subtraction circuit 12, subtracts half the amplitude corresponding to 4 bits, and sets the A / D conversion in the internal A / D converter 11.
D conversion is performed. The A / D conversion signal is loaded into the shift register 13 and then the all zero signal shift register 14
Is input one bit at a time from the MSB side via an adder circuit 15.

The loaded signal is D / A converted by the D / A converter 10, and the D / A conversion value is subtracted from the input signal by the differential amplifier A1 as a second A / D conversion, and the output is output. There is amplified to 2 ⁴ times, similarly subtraction and a /
The data is D-converted and loaded into the shift register 13. At this time, the signal of the shift register 14 and the 8 bits that should be originally shifted from the MSB side are added with a shift of only 4 bits and loaded into the shift register 14 again. 4-bit A / D
I do.

As the third A / D conversion, the difference voltage between the D / A conversion data and the input signal is obtained by differential amplifiers A1 and A2.
In is amplified to 2 ⁸ times, loaded is subtracted and A / D conversion to the shift register 13, it is loaded into the shift register 14 again are added by shifting 8 bits from the load signal and the MSB of the shift register 14.

As the fourth A / D conversion, the difference voltage between the D / A conversion data and the input signal is obtained by the differential amplifiers A1 and A1.
2, A3 in is amplified to 2 ¹² times, loaded is subtracted and A / D conversion to the shift register 13 is 12 bits staggered loaded into the shift register 14 again is added.

As the fifth A / D conversion, the difference voltage between the D / A conversion signal and the input signal is obtained by differential amplifiers A1, A2,
A3, A4 in the amplified 2 ¹⁶ times, loaded is subtracted and A / D conversion to the shift register 13, is loaded into the shift register 14 again are added by shifting 16-bit. In this case, the output data of the shift register 13 is MS
Only the 4 bits from the B side are added input signals. During this time,
The addition signal is also loaded into the output register 16 each time, and is output as a final 20-bit parallel A / D conversion signal after the fifth A / D conversion.

FIG. 3 shows an A / D of n = 20 bits for an input signal of a voltage that changes to positive and negative according to another embodiment of the present invention.
It is a converter. Differential amplifier circuit, and more configuration as a differential amplifier A11 which functions as a differential amplifier or amplification of the first amplifier of the amplification degree 2 ^4, a switching switched amplifier A12~A14 the amplification degree 1 or 2 ^XY = 2 ⁴ by the switching Have been. Each amplifier, amplification degree 1, 2 ^4, 2 ^8, 2 ^12, 2 ¹⁶ switches the amplification degree five stages of conversion input selection circuit 28 is included. Reference numeral 21 denotes an internal A / D converter having a sign of X = 8 bits, for example, a 2 ^s C (tooth complementary) type. For example, if the input signal for A / D conversion is positive, MS
The sign bit of B is set to the logical value 0, and the complement is output as the logical value 1 when the sign bit is negative.

Reference numeral 23 denotes an 8-bit shift register into which the output signal of the internal A / D converter 21 is loaded.
SB is a sign bit. Reference numeral 24 denotes a 20-bit shift register that supplies an A / D conversion signal to the D / A converter 20, and the MSB is a sign bit.

Reference numeral 25 denotes a 1-bit full-adder type addition circuit, which is provided with an addition control circuit 25a. The addition control circuit sequentially takes out the output signals one bit at a time from the LSB side of the shift registers 23 and 24 and adds them, and inputs the added signal from the MSB side of the shift register 24.
At this time, when the conversion input of the second and subsequent stages is selected, the output signal of the shift register 23 is sequentially shifted downward by X-
MS of shift register 24 is increased by Y = 4 bits.
The bits shifted from the B side and all of the shifted bits are added while being assigned with the logical value 0 or 1 of the sign bit of the shift register 23.

Reference numeral 26 denotes a 20-bit output shift register which sequentially receives the added outputs and outputs an A / D conversion signal as a final added output. Reference numeral 27 denotes a controller for controlling these components. The controller 27 causes the conversion input selection circuit 28 to sequentially perform a selection operation, causes the internal A / D converter 21 to perform a comparison operation each time, and further adds to the addition control circuit 25a. Control operation is performed.

As in the previous embodiment, the 8-bit internal A /
The D converter 11 sets X = 8 in consideration of the price, and sets the error of the differential amplifier circuits A11 to A14 to about 1%.
4, N is set to 5 from n / (XY). The internal A / D converter 21 does not need the above-described subtraction circuit corresponding to the Y bit in order to convert the positive / negative input signal.

The operation of the A / D converter thus configured will be described with reference to FIG. The differential amplifier A11 has 0
Sampling signals fluctuating positively and negatively around V are sequentially input. First, in the first A / D conversion, the differential amplifiers A11 to A14 all have an amplification factor of 1 under the control of the conversion input selection circuit 28. For example, a positive input signal is directly supplied to the internal A / D converter 21. / D conversion. The A / D conversion signal is loaded into the shift register 23, and is then added to the shift register 24 for all 0 signals from the MSB side.
5 is loaded.

The loaded signal is D / A converted by the D / A converter 20, and the D / A converted signal is subtracted from the input signal by the differential amplifier A11 as the second A / D conversion, and the output is output. is amplified to 2 ⁴ times the negative amplified output is loaded is a / D converted into the shift register 23. At this time, the load signal of the shift register 24 and the MSB
The data is shifted by 4 bits from the side and added to the output signal of the shift register 23 with the shifted 4 bits being all 1s, and loaded into the shift register 24 again.

The third A / D conversion as an amplifier A12 is further switched to the amplification degree 2 ^4, the second D / A conversion signal is amplified to 2 ^eight times is subtracted from the input signal, the positive amplified output Are A / D converted and loaded into the shift register 23. At this time, the output signal of the shift register 24 and M
The data is shifted by 8 bits from the SB side, added to the output signal of the shift register 23 where the 8 bits are all 0, and loaded into the shift register 24 again.

As the fourth A / D conversion, an amplifier A
13 is switched to amplify the difference signal by a factor of 2 ¹² , and the negative amplified output is A / D-converted, 12-bit shifted and all-ones are placed, and added and loaded into the shift register 23. As fifth A / D converter, amplifier A14 is switched is amplified to 2 ¹⁶ times the difference signal by adding the shift and registered number parallel 16 bits, a final 20-bit A
The / D conversion signal is output from the output register 26.

[0030]

According to the first aspect of the present invention, the input signal of the positive voltage is supplied to the internal A / A having a smaller number of bits than the desired number of bits.
When A / D conversion is performed a plurality of times by the D converter, re-conversion is performed for the number of bits that may cause an error, thereby reducing the resistance value error and drift of the differential amplifier circuit, internal A / D conversion error or noise. The resulting error can be avoided, and it is not necessary to particularly increase the resistance value error of the differential amplifier circuit. Also, by slightly subtracting the input signal of the internal A / D converter, the input signal for the internal A / D converter at a very small level which may become negative due to an error in the amplifier resistance is reconverted without error. The / D conversion accuracy is further improved. When a high-speed type is used as the internal A / D converter, multi-channel processing is also possible.

According to the third aspect of the present invention, when an internal A / D converter having a smaller number of bits than the intended number of bits converts an input signal that fluctuates ± with respect to the 0 level a plurality of times, By performing re-conversion for the number of bits that may cause an error, it is possible to avoid the influence of the resistance value error and drift of the differential amplifier circuit, the internal A / D conversion error, or the error due to noise. In other words, It is not necessary to particularly increase the operation accuracy and the like of the differential amplifier circuit. When a high-speed type is used as the internal A / D converter, multi-channel processing is also possible.

According to the second or fourth aspect of the present invention, the addition is 1
By performing the operation serially bit by bit, a simple circuit configuration can be added.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a positive voltage A / D converter according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating the operation of the A / D converter.

FIG. 3 is a diagram illustrating a voltage change A according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a circuit configuration of a / D converter.

FIG. 4 is a diagram illustrating the operation of the A / D converter.

FIG. 5 is a diagram showing a circuit configuration of a conventional A / D converter.

FIG. 6 is a diagram showing a circuit configuration of a conventional A / D converter.

[Explanation of symbols]

 A1, A11 Differential amplifier A2 to A4, A12 to A14 Amplifier

Continuation of the front page (56) References JP-A-56-94832 (JP, A) JP-A-56-164628 (JP, A) JP-A-58-104524 (JP, A) JP-A-4-79614 (JP) JP-A-1-162420 (JP, A) JP-A-3-75638 (JP, U) JP-B-49-30384 (JP, B1) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H03M 1/00-1/88

Claims (4)

(57) [Claims] An A / D converter for A / D converting a positive voltage input signal with n bits, wherein an X-bit internal A / D converter, (X <n), an input signal and an n-bit D / A converter while the differential voltage between the output signal is 2 ^XY multiplied by one multiplication from 2 ^XY times N-1
A differential amplifier circuit for amplifying by switching the degree of amplification to a stage (Y is X
N is the number of bits defining the amplitude at which the A / D conversion can be performed ignoring the effect of the error voltage generated in the differential amplifier circuit on the internal A / D converter, and N is rounded up to n / (XY). Integer), the internal A / D converter has an amplification degree of the input signal of 1
A conversion input selection circuit that supplies an A / D conversion input signal that is sequentially switched to N stages together with the supply as it is and the supply of an amplified output with the amplification degree of the N-1 stages of the differential amplifier circuit switched. A subtraction circuit for subtracting substantially half of the amplitude corresponding to Y bits from the A / D conversion input signal output from the conversion input selection circuit; and X for loading the output signal of the internal A / D converter.
Bit shift register, an n-bit shift register that supplies a D / A conversion input signal to an n-bit D / A converter, and an output signal of the X-bit shift register in a first stage of a conversion input selection circuit. At the time of selection, the n-bit shift register is loaded from the MSB side as it is, and the output signal of the n-bit shift register and the output signal of the X-bit shift register are selected for each of the second and subsequent stages. Adding means for increasing the shift amount from the MSB side of the shift register by XY bits at a time and loading the shift register into the n-bit shift register; after selecting N stages, the output of the n-bit shift register An A / D converter wherein a signal is used as an A / D conversion output. 2. A full adder type adder for adding one bit at a time, and sequentially selecting an A / D conversion input signal at a first stage, sequentially taking out an output signal from the LSB side of an X-bit shift register and n MSB of bit shift register
Side, and when the second and subsequent stages are selected, n-bit and X-bit successively output signals are taken from the LSB side of the shift register, and the X-bit output signal of the shift register is shifted by XY bits. 2. The A / D converter according to claim 1, further comprising: an adder control circuit for performing an addition to the full adder type adder circuit and sequentially inputting the added signal from the MSB side of the n-bit shift register. converter. 3. An A / D converter for performing A / D conversion of an input signal of a voltage that changes to positive / negative with n bits, comprising: an X-bit signed internal A / D converter; An n-bit D / A converter for D / A converting an input signal for A / A conversion; and a differential voltage between the input signal and an output signal of the n-bit D / A converter multiplied by 2 ^XY times to 2 ^XY times. Letting N
A differential amplifier circuit for amplifying by switching the degree of amplification to one stage and (Y
Is the number of bits defining the amplitude at which A / D conversion can be performed on the X-bit internal A / D converter ignoring the effect of the error voltage generated in the differential amplifier circuit, and N is n / (XY)
The internal A / D converter supplies the input signal with an amplification factor of 1
A conversion input selection circuit that supplies an A / D conversion input signal that is sequentially switched to N stages together with the supply as it is and the supply of an amplified output with the amplification degree of the N-1 stages of the differential amplifier circuit switched. An X-bit signed shift register which is loaded as a complement with the logical value of the sign bit being 0 when the output signal of the internal A / D converter is positive and the logical value of the sign bit being 1 when the output signal is negative; An n-bit signed shift register loaded as a complement with the logical value of the sign bit set to 0 when the D / A conversion input signal is positive and the logical value of the sign bit set to 0 when negative, The output signal of the shift register is loaded from the MSB side into the n-bit shift register as it is when the first stage of the conversion input selection circuit is selected, and the n-bit output of the shift register is selected every time the second and subsequent stages are selected. No. and, an output signal of the shift register of the X bits n
The shift amount of the bits from the MSB side of the shift register is shifted while increasing by XY bits at a time, and all the shifted bits are added while being assigned with the logical value of the sign bit, and the n bits are shifted. An A / D converter comprising: an adder for loading a register, wherein after selecting N stages, an n-bit output signal of the shift register is used as an A / D conversion output. 4. A full adder type adding circuit for adding one bit at a time, and sequentially selecting an A / D conversion input signal at a first stage, sequentially taking out an output signal from the LSB side of a shift register of X bits and n MSB of bit shift register
Side, and when the second and subsequent stages are selected, n-bit and X-bit successively output signals are taken from the LSB side of the shift register, and the X-bit output signal of the shift register is shifted by XY bits. 4. An addition control circuit for performing addition to a full adder type adder circuit after performing a set number and sequentially inputting the added signal from the MSB side of the n-bit shift register. / D converter.