JP3092575B2 - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JP3092575B2 JP3092575B2 JP882298A JP882298A JP3092575B2 JP 3092575 B2 JP3092575 B2 JP 3092575B2 JP 882298 A JP882298 A JP 882298A JP 882298 A JP882298 A JP 882298A JP 3092575 B2 JP3092575 B2 JP 3092575B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- sealed
- wiring pattern
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Details Of Cutting Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、樹脂封止型半導体
装置に関する。The present invention relates to a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】ＴＡＢテープのような片面配線のサブス
トレートを用いた樹脂封止型半導体装置では、パッケー
ジを全面封止した後にダイシングカットが行なわれ、樹
脂封止された半導体チップを個々に切出すことが行なわ
れている。2. Description of the Related Art In a resin-encapsulated semiconductor device using a single-sided wiring substrate such as a TAB tape, dicing is cut after the package is entirely sealed, and the resin-encapsulated semiconductor chips are individually cut. Outing is being done.
【０００３】従来例の樹脂封止型半導体装置では図４に
示すように、ＴＡＢテープ１はポリイミドテープ１ａ
と、ポリイミドテープ１ａ上に接着剤３を介して接着さ
れたＣｕ配線２と、ポリイミドテープ１ａのランド部１
ｂに設けられたソルダーレジスト４とから構成されてい
る。In a conventional resin-encapsulated semiconductor device, as shown in FIG. 4, a TAB tape 1 is a polyimide tape 1a.
And a Cu wiring 2 adhered to the polyimide tape 1a via an adhesive 3, and a land portion 1 of the polyimide tape 1a.
b.
【０００４】そしてＴＡＢテープ１のソルダーレジスト
４上に半導体チップ１ｃがペースト５を介して接着さ
れ、半導体チップ１ｃの電極がＣｕ配線２にボンディン
グワイヤ６を介して電気的に接続されている。またＴＡ
Ｂテープ１のランド部１ｂの裏面側には、Ｃｕ配線２に
接続する半田ボール８が設けられている。[0004] A semiconductor chip 1 c is bonded on a solder resist 4 of the TAB tape 1 via a paste 5, and electrodes of the semiconductor chip 1 c are electrically connected to the Cu wiring 2 via bonding wires 6. Also TA
On the back side of the land portion 1b of the B tape 1, a solder ball 8 connected to the Cu wiring 2 is provided.
【０００５】さらにＴＡＢテープ１上に搭載された半導
体チップ１ｃ及びボンディングワイヤ６等は、樹脂７に
より被覆され外気から気密封止されている。Further, the semiconductor chip 1c and the bonding wires 6 mounted on the TAB tape 1 are covered with a resin 7 and hermetically sealed from the outside air.
【０００６】封止封止された半導体装置は、切断線１１
に沿ってダイシングカットされ、個々に切り出されるよ
うになっている。[0006] The sealed semiconductor device is provided with a cutting line 11.
Are cut along the dicing line and cut out individually.
【０００７】[0007]
【発明が解決しようとする課題】ところで、樹脂封止さ
れた半導体装置は、ダイシングカットされて個々に切り
出すため、ダイシングカットする際に、ＴＡＢテープ上
で切断線１１の位置が明確にされる必要がある。By the way, since the semiconductor devices sealed with resin are cut by dicing and cut out individually, it is necessary to clarify the positions of the cutting lines 11 on the TAB tape when dicing and cutting. There is.
【０００８】図４及び図５に示す従来の樹脂封止型半導
体装置では、ＴＡＢテープ１の裏面に形成された半田ボ
ール８を画像認識してダイシングカットを行っていた
が、半田ボール８は球状であるため、認識に必要な反射
光が散乱して認識しずらく、かつ半田ボール８は、リフ
ロー工程で溶融させてランド部１ｂに形成されるため、
その位置ずれが生じやすく、切断位置の位置ずれを招き
やすいという問題があった。In the conventional resin-encapsulated semiconductor device shown in FIGS. 4 and 5, dicing cutting is performed by recognizing an image of the solder ball 8 formed on the back surface of the TAB tape 1, but the solder ball 8 is spherical. Therefore, the reflected light necessary for recognition is scattered, making it difficult to recognize, and the solder ball 8 is melted in the reflow process and formed on the land portion 1b.
There has been a problem that the misalignment is likely to occur and the cutting position is likely to misalign.
【０００９】そこで、特開平４−７９２６１号公報に開
示された技術では、Ｃｕ配線２が設けられたＴＡＢテー
プ１の表面側にダイシングカットの位置を認識するカッ
ト認識部を設けている。Therefore, in the technique disclosed in Japanese Patent Application Laid-Open No. 4-79261, a cut recognition unit for recognizing the dicing cut position is provided on the front side of the TAB tape 1 on which the Cu wiring 2 is provided.
【００１０】しかしながら、この種の樹脂封止型半導体
装置では、ＴＡＢテープ１の半田ボール８が設けられた
裏面側を表向きにして、樹脂封止された半導体チップを
個々に切り出すため、切断箇所を指し示すカット認識部
がＴＡＢテープの下面側に隠れてしまい、ＴＡＢテープ
の切断位置を正確に認識することができなくなるという
問題がある。However, in this type of resin-sealed type semiconductor device, the resin-sealed semiconductor chips are cut out individually with the back surface of the TAB tape 1 on which the solder balls 8 are provided facing up. There is a problem in that the pointed cut recognition unit is hidden on the lower surface side of the TAB tape, and the cut position of the TAB tape cannot be accurately recognized.
【００１１】この問題を解決するためには、切断位置を
示すカット認識部をＴＡＢテープ１の裏面側に設けるこ
とも考えられるが、そのカット認識部がダイシングカッ
トするに至る製造過程で剥離しないように工夫する必要
がある。この点については、従来例では意図されていな
かった。In order to solve this problem, it is conceivable to provide a cut recognition portion indicating the cutting position on the back side of the TAB tape 1. However, the cut recognition portion is not peeled off during the manufacturing process leading to dicing cut. It is necessary to devise. This was not intended in the prior art.
【００１２】本発明の目的は、前記問題点を解決した樹
脂封止型半導体装置を提供することにある。An object of the present invention is to provide a resin-encapsulated semiconductor device which solves the above problems.
【００１３】[0013]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る樹脂封止型半導体装置は、テープ基体
と、半導体チップと、認識マークとを有する樹脂封止型
半導体装置であって、テープ基体は、ランド部の一面に
配線パターン部を有し、ランド部の他面に半田ボールを
形成されたものであり、半導体チップは、前記テープ基
体のランド部一面に搭載されて前記配線パターン部に電
気的に接続され、樹脂封止されたものであり、認識マー
クは、前記ランド部の外周領域に形成される前記配線パ
ターン部の一部により、樹脂封止された半導体チップの
ダイシングカット位置を指し示すものである。In order to achieve the above object, a resin-sealed semiconductor device according to the present invention is a resin-sealed semiconductor device having a tape base, a semiconductor chip, and a recognition mark. The tape base has a wiring pattern portion on one surface of the land portion and a solder ball formed on the other surface of the land portion, and the semiconductor chip is mounted on one surface of the land portion of the tape base and the wiring The identification mark is electrically connected to the pattern portion and is resin-sealed, and the recognition mark is formed by dicing the semiconductor chip resin-sealed by a part of the wiring pattern portion formed in the outer peripheral region of the land portion. It indicates the cutting position.
【００１４】また前記認識マークは、前記配線パターン
部での光反射によりダイシングカット位置を認識するも
のである。The recognition mark is for recognizing a dicing cut position by light reflection at the wiring pattern portion.
【００１５】また前記認識マークは、前記テープ基体の
他面側に貫通した貫通孔を通して光反射するものであ
る。The recognition mark reflects light through a through-hole penetrating the other surface of the tape base.
【００１６】また前記貫通孔の開口縁形状は、適宜整形
されたものである。The opening edge shape of the through-hole is appropriately shaped.
【００１７】本発明によれば、半導体チップの外周領域
に設けられる配線パターン部を一部残し、その配線パタ
ーンをダイシングカットの位置認識用標識として用い、
かつ、その配線パターン部をＴＡＢテープの裏面側に設
けた貫通孔を通して光学的に認識する。According to the present invention, a part of the wiring pattern provided in the outer peripheral area of the semiconductor chip is left, and the wiring pattern is used as a position recognition marker for dicing cut.
In addition, the wiring pattern portion is optically recognized through a through hole provided on the back side of the TAB tape.
【００１８】[0018]
【発明の実施の形態】以下、本発明の実施の形態を図に
より説明する。図１は、本発明の一実施形態に係る樹脂
封止型半導体装置を示す裏面図、図２は同断面図、図３
は、貫通孔の開口縁形状を示す図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a rear view showing a resin-sealed semiconductor device according to an embodiment of the present invention, FIG.
FIG. 4 is a view showing an opening edge shape of a through hole.
【００１９】図において、本発明の一実施形態に係る樹
脂封止型半導体装置は、テープ基体と、半導体チップ１
ｃと、認識マークとを有している。In FIG. 1, a resin-sealed semiconductor device according to one embodiment of the present invention includes a tape base, a semiconductor chip 1
c and a recognition mark.
【００２０】テープ基体は、ランド部１ｂの一面側に配
線パターン部を有し、ランド部１ｂの他面側に半田ボー
ル８を形成したものであり、実施形態ではテープ基体と
してＴＡＢテープ１を使用している。ＴＡＢテープ１
は、ポリイミドテープ１ａと、ポリイミドテープ１ａ上
に接着剤３を介して接着されたＣｕ配線（配線パターン
部に相当する）２と、ランド部１ｂの一面側に設けられ
たソルダーレジスト４と、ランド部１ｂの他面側に形成
された半田ボール８とを有している。The tape substrate has a wiring pattern portion on one surface side of the land portion 1b and a solder ball 8 formed on the other surface side of the land portion 1b. In the embodiment, the TAB tape 1 is used as the tape substrate. doing. TAB tape 1
A polyimide tape 1a, a Cu wiring (corresponding to a wiring pattern portion) 2 adhered on the polyimide tape 1a via an adhesive 3, a solder resist 4 provided on one surface side of the land portion 1b, And a solder ball 8 formed on the other surface side of the portion 1b.
【００２１】半導体チップ１ｃは、ランド部１ｃのソル
ダーレジスト４にペースト５を介して接着され、半導体
チップ１ｃの図示しない電極は、Ｃｕ配線２にボンディ
ングワイヤ６を介して電気的に接続され、樹脂７により
樹脂封止されている。The semiconductor chip 1c is bonded to the solder resist 4 of the land 1c via a paste 5, and an electrode (not shown) of the semiconductor chip 1c is electrically connected to the Cu wiring 2 via a bonding wire 6, and 7, resin sealing.
【００２２】認識マーク９は、ランド部１ｂの外周領域
に形成されるＣｕ配線２の一部を利用して、樹脂封止さ
れた半導体チップ１のダイシングカット位置１１ａを指
し示すようになっている。なお、認識マーク９をなすＣ
ｕ配線２は、半導体チップ１ｃの電極が接続されるＣｕ
配線２から電気的に切り離されている。The recognition mark 9 is designed to indicate the dicing cut position 11a of the resin-sealed semiconductor chip 1 by using a part of the Cu wiring 2 formed in the outer peripheral area of the land 1b. In addition, C which forms the recognition mark 9
The u wiring 2 is made of Cu connected to an electrode of the semiconductor chip 1c.
It is electrically disconnected from the wiring 2.
【００２３】認識マーク９は具体的には、ランド部１ｂ
の外周領域に形成されるＣｕ配線２のうちダイシングカ
ット位置１１ａに対応するＣｕ配線２を利用して光反射
によりダイシングカット位置１１ａを認識するものであ
り、さらにＴＡＢテープ１の他面側に貫通した認識マー
ク形成用貫通孔１０を通して光反射するようになってい
る。さらに貫通孔１０の開口縁形状は図３に示すよう
に、適宜整形されており、ダイシングカット位置１１ａ
明確に指し示すようになっている。The recognition mark 9 is specifically formed on the land 1b.
The dicing cut position 11a is recognized by light reflection using the Cu wiring 2 corresponding to the dicing cut position 11a of the Cu wiring 2 formed in the outer peripheral region of the TAB tape 1 and penetrates to the other surface side of the TAB tape 1. The light is reflected through the recognition mark forming through hole 10. Further, the opening edge shape of the through hole 10 is appropriately shaped as shown in FIG.
It is clearly pointed out.
【００２４】本発明の実施形態において、樹脂封止され
た半導体チップ１ｃを個々に切り出すには、まず、半導
体チップ１ｃが樹脂封止されたＴＡＢテープ１の裏面
側、すなわち半田バンプ８側を上向きにしてＴＡＢテー
プ１をセットする。In the embodiment of the present invention, in order to cut out the resin-sealed semiconductor chips 1c individually, first, the back surface side of the resin-sealed TAB tape 1, that is, the solder bump 8 side faces upward. Then, the TAB tape 1 is set.
【００２５】この場合、貫通孔１０は上向き、すなわち
半導体チップ１ｃをダイシングカットする側に位置する
ため、貫通孔１０を通してダイシングカット位置１１ａ
に対応するＣｕ配線２を光照射すると、貫通孔１０内の
Ｃｕ配線２で反射し、ダイシングカット位置１１ａを表
示する。In this case, since the through hole 10 is located upward, that is, on the side where the semiconductor chip 1c is diced and cut, the dicing cut position 11a is formed through the through hole 10.
When the Cu wiring 2 corresponding to (1) is irradiated with light, the light is reflected by the Cu wiring 2 in the through hole 10 and the dicing cut position 11a is displayed.
【００２６】光反射した貫通孔１０の位置を認識し、複
数のダイシングカット位置１１ａに存在する認識マーク
９を結ぶ切断線１１に沿って半導体チップ１ｃをダイシ
ングカットし、これを個々に切り出す。The positions of the through holes 10 where the light is reflected are recognized, and the semiconductor chips 1c are diced and cut along cutting lines 11 connecting the recognition marks 9 existing at a plurality of dicing cut positions 11a, and these are cut out individually.
【００２７】なお、実施形態では、テープ基体としてＴ
ＡＢテープを使用したが、そのＴＡＢテープは図１及び
図２に示す３層構造のものばかりでなく、２層構造のも
のでもよく、さらには、ＴＡＢテープ以外のテープ状の
ものをテープ基体として用いてもよい。In the embodiment, the tape base is T
Although the AB tape was used, the TAB tape may be not only of the three-layer structure shown in FIGS. 1 and 2 but also of a two-layer structure. May be used.
【００２８】[0028]
【発明の効果】以上説明したように本発明によれば、半
導体チップの電極がボンディングワイヤを介して電気的
に接続される配線パターンの一部を用いて光反射させ、
ダイシングカット位置を認識するようにしたため、半導
体チップのダイシングカット位置をテープ裏面側、すな
わち半導体チップをダイシングカットする側から明確に
確認することができる。As described above, according to the present invention, the electrode of the semiconductor chip reflects light using a part of the wiring pattern electrically connected through the bonding wire,
Since the dicing cut position is recognized, the dicing cut position of the semiconductor chip can be clearly confirmed from the back surface of the tape, that is, from the side where the dicing cut is performed on the semiconductor chip.
【００２９】さらに、光反射する配線パターンは、テー
プ基体に平面的に接着されるものであり、その平面で光
反射するため、従来例の半田バンプの球面での反射量よ
りも光量を十分に確保することができ、ダイシングカッ
ト位置を十分に認識することができる。Further, the light-reflecting wiring pattern is bonded to the tape base in a planar manner, and reflects light on the flat surface, so that the light amount is sufficiently smaller than the reflection amount of the conventional solder bump on the spherical surface. As a result, the dicing cut position can be sufficiently recognized.
【００２９】さらにダイシングカット位置を認識する認
識マークは、ランド部の外周領域の配線パターンの一部
を利用しているため、配線パターンを有効利用すること
ができる。Further, since the recognition mark for recognizing the dicing cut position uses a part of the wiring pattern in the outer peripheral area of the land portion, the wiring pattern can be effectively used.
【００３０】さらに、その配線パターンは、ダイシング
カットするに至る製造過程で樹脂に被覆されているた
め、剥離することがなく、確実に半導体チップのダイシ
ングカット位置を恒久的に表示することができ、しかも
半導体チップのダイシングカット位置を正確に表示する
ことができる。Further, since the wiring pattern is covered with the resin in the manufacturing process leading to the dicing cut, the dicing cut position of the semiconductor chip can be reliably and permanently displayed without peeling off. Moreover, the dicing cut position of the semiconductor chip can be accurately displayed.
【図１】本発明の一実施形態に係る樹脂封止型半導体装
置を示す裏面図である。FIG. 1 is a rear view showing a resin-sealed semiconductor device according to one embodiment of the present invention.
【図２】本発明の一実施形態に係る樹脂封止型半導体装
置を示す断面図である。FIG. 2 is a cross-sectional view showing a resin-sealed semiconductor device according to one embodiment of the present invention.
【図３】本発明の一実施形態に係る樹脂封止型半導体装
置に設けた貫通孔の開口縁形状を示す図である。FIG. 3 is a view showing an opening edge shape of a through hole provided in the resin-sealed semiconductor device according to one embodiment of the present invention.
【図４】従来例に係る樹脂封止型半導体装置を示す裏面
図である。FIG. 4 is a back view showing a resin-sealed semiconductor device according to a conventional example.
【図５】従来例に係る樹脂封止型半導体装置を示す縦断
面図である。FIG. 5 is a longitudinal sectional view showing a resin-sealed semiconductor device according to a conventional example.
１ ＴＡＢテープ（テープ基体） １ａ ポリイミドテープ １ｂ ランド部 １ｃ 半導体チップ ２ Ｃｕ配線（配線パターン） ７ 樹脂 ９ 認識マーク １０ 認識マーク形成用貫通孔 １１ 切断線 １１ａ ダイシングンカット位置 Reference Signs List 1 TAB tape (tape base) 1a Polyimide tape 1b Land 1c Semiconductor chip 2 Cu wiring (wiring pattern) 7 Resin 9 Recognition mark 10 Recognition mark formation through hole 11 Cutting line 11a Dicing cut position
Claims (4)
ークとを有する樹脂封止型半導体装置であって、 テープ基体は、ランド部の一面側に配線パターン部を有
し、ランド部の他面側に半田ボールを形成したものであ
り、 半導体チップは、前記テープ基体のランド部一面側に搭
載されて前記配線パターン部に電気的に接続され、樹脂
封止されたものであり、 認識マークは、前記ランド部の外周領域に形成される前
記配線パターン部の一部により、樹脂封止された半導体
チップのダイシングカット位置を指し示すものであるこ
とを特徴とする樹脂封止型半導体装置。1. A resin-encapsulated semiconductor device having a tape base, a semiconductor chip, and a recognition mark, wherein the tape base has a wiring pattern portion on one surface side of a land portion, and the other surface of the land portion. The semiconductor chip is mounted on one surface of the land portion of the tape base, is electrically connected to the wiring pattern portion, and is sealed with a resin. A resin-sealed semiconductor device, wherein a part of the wiring pattern portion formed in an outer peripheral region of the land portion indicates a dicing cut position of a resin-sealed semiconductor chip.
での光反射によりダイシングカット位置を認識するもの
であることを特徴とする請求項１に記載の樹脂封止型半
導体装置。2. The resin-encapsulated semiconductor device according to claim 1, wherein the recognition mark recognizes a dicing cut position by light reflection on the wiring pattern portion.
面側に貫通した貫通孔を通して光反射するものであるこ
とを特徴とする請求項２に記載の樹脂封止型半導体装
置。3. The resin-encapsulated semiconductor device according to claim 2, wherein the recognition mark reflects light through a through hole penetrating the other surface of the tape base.
れたものであることを特徴とする請求項３に記載の樹脂
封止型半導体装置。4. The resin-sealed semiconductor device according to claim 3, wherein an opening edge shape of said through hole is appropriately shaped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP882298A JP3092575B2 (en) | 1998-01-20 | 1998-01-20 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP882298A JP3092575B2 (en) | 1998-01-20 | 1998-01-20 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11214588A JPH11214588A (en) | 1999-08-06 |
| JP3092575B2 true JP3092575B2 (en) | 2000-09-25 |
Family
ID=11703506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP882298A Expired - Fee Related JP3092575B2 (en) | 1998-01-20 | 1998-01-20 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3092575B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3827497B2 (en) | 1999-11-29 | 2006-09-27 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
| JP2002118201A (en) | 2000-10-05 | 2002-04-19 | Hitachi Ltd | Semiconductor device and method for manufacturing the same |
| JP4212255B2 (en) | 2001-03-30 | 2009-01-21 | 株式会社東芝 | Semiconductor package |
| JP2002319841A (en) * | 2001-04-20 | 2002-10-31 | Murata Mfg Co Ltd | Surface acoustic wave device precursor, manufacturing method for surface acoustic wave device, communication unit |
| JP2010021288A (en) * | 2008-07-09 | 2010-01-28 | Elpida Memory Inc | Manufacturing method of semiconductor device and substrate matrix |
| JP5444382B2 (en) * | 2012-01-16 | 2014-03-19 | ルネサスエレクトロニクス株式会社 | Resin-sealed semiconductor device |
| US9704514B1 (en) | 2016-10-07 | 2017-07-11 | International Business Machines Corporation | High accuracy bearing surface slotting process for tape head fabrication |
| US9711170B1 (en) | 2016-10-07 | 2017-07-18 | International Business Machines Corporation | High accuracy bearing surface slotting process for tape head fabrication |
| US9799355B1 (en) | 2016-10-18 | 2017-10-24 | International Business Machines Corporation | High accuracy tape bearing surface length definition process for tape head fabrication |
| US9779766B1 (en) | 2016-10-24 | 2017-10-03 | International Business Machines Corporation | High accuracy tape bearing surface length definition process by closure lapping for tape head fabrication |
-
1998
- 1998-01-20 JP JP882298A patent/JP3092575B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11214588A (en) | 1999-08-06 |
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