JP3092187B2 - Pulse generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a pulse used to detect a tape position, for example, to form a bimorph drive signal.

[0002]

2. Description of the Related Art FIG. 21 shows a track pattern of a D-1 digital VTR format (525/60 system).

[0003] 1 is a magnetic tape, 2 is a cue track, 3 is a control track, and 4 is a time code track. In the control track 3, a servo reference signal is recorded every four tracks.

[0004] 5U and 5L are a video upper sector and a video lower sector which constitute a video track, respectively.
Here, a group of patterns on each track is called a "sector". FIG. 21 shows a track for one field.

The image signal for one field is 525/60.
The scheme consists of 20 sectors, each field starting with the upper sector 5U and ending with the lower sector 5L. One field is divided into five segments, and one segment of data is recorded in four hatched sectors. That is, the data of one segment is recorded in four sectors straddling four tracks A to D.

As a result, even if one of the four tracks becomes unusable due to head damage or the error rate extremely deteriorates, only one quarter of one segment is affected. . In addition, by sequentially allocating the video signal to four tracks (sectors) according to the time sequence, even if data of one track is lost, the error correcting function can be sufficiently exhibited.

Reference numeral 6 denotes an audio sector constituting an audio track, which is arranged substantially at the center of the tape 1. This is because the tape is less likely to be affected when the tape expands or contracts (cue).

FIG. 22 shows the arrangement of audio sectors. Four-channel audio data temporally associated with two-segment video data with diagonal lines is recorded in 16 sectors. By reducing the error correction block length, the danger of reading and rewriting sectors that are not related to editing is reduced. Also, by reducing the error correction block length, the ability to correct scratches in the longitudinal direction of the tape and dropout in the track direction decreases, but the same data is compensated for by writing twice.

FIG. 23 shows an example of a rotary magnetic head device. The rotary drum 7 has A-channel read magnetic heads Ha, Hb, Hc ', H with an angular interval of about 180 °.
d 'and the B-channel reproducing magnetic heads Hc, Hd, H
a 'and Hb' are provided. Here, when the head Ha scans the track A, the interval d between the heads is set corresponding to the track pitch so that the heads Hb, Hc ', Hd' scan the tracks B, C, D. (See FIG. 24). The same applies to the heads Hc, Hd, Ha ', Hb'.

At the time of reproduction, the heads Ha, Hb, Hc ',
Hd '(Hc, Hd, Ha', Hb ') is A
By scanning the four tracks 〜D, video data and audio data are reproduced. In FIG. 23, the illustration of the recording head is omitted.

At the time of 1 × speed reproduction, the head is
The angle to scan upward is equal to the angle of the track recorded on the tape. However, when performing different speed playback,
Since the angle scanned by the head does not match the angle of the track, a track shift (tilt error) occurs, resulting in guard band noise on the reproduction screen. FIG. 25 shows the head scanning trajectory at the time of −1 × speed, still time, + 1 × speed, and + 2.5 × speed.

In order to eliminate such track deviation, it has been proposed to fix the head to a bimorph and to control the head position using the bimorph.
In this case, in order to drive the bimorph, a track tilt waveform signal, a tracking waveform signal, a ringing waveform signal, a tracking error correction waveform signal, and the like are required.

At times other than +1 times speed, the head scans a track recorded on the tape obliquely at a constant angle corresponding to the tape speed. Therefore, it is necessary to change the head position so as to correct this angle. The track tilt waveform signal is responsible for this part.

Except at the time of +1 times speed, basically, the head and the track cannot satisfy the fixed relation. For this reason, it is necessary to change the head position according to the tape running position for correction. The tracking waveform signal is responsible for this part.

When the bimorph is moved, unnecessary vibration is generated due to hysteresis or mechanical resonance, which may disturb the tracking. The ringing waveform signal is added within blanking (time during which scanning is not performed) to correct the unnecessary vibration.

Another waveform signal for optimizing tracking is a tracking error correction waveform signal.

[0017]

Since the tracking waveform signal is formed in relation to the tape position, it is necessary to detect the tape position. The tape position can be detected by resetting the counter with a servo reference pulse reproduced from the control track 3 and driving the counter with a predetermined pulse.

Thus, the pulse for driving the counter is:
For example, it can be obtained by the following processing. That is,
Frequency signals FG (A), FG having a phase difference of 90 ° from a frequency generator (FG) attached to the capstan
(B) is regarded as a sine wave, and these signals FG (A), FG
(B) is passed through an arithmetic circuit to output signals f (θ) having different phases.
= U.FG (A) + v.FG (B). Then, a plurality of pulses are formed from the signals f (θ) having different phases by using a comparator, and finally, an equally-spaced pulse m times as large as the signal FG (A) is formed by logical operation processing.

In this case, it is necessary to construct a circuit in which the coefficient of u or v becomes negative depending on θ. In that case, if you try to add appropriate hysteresis to the comparator,
It cannot be processed by one stage of the differential amplifier, and the whole circuit becomes large and complicated, and the calculation for determining the values of the resistors constituting the circuit becomes complicated.

Further, the accuracy of the m-times equally-spaced pulse is greatly affected by the amplitude of the signals FG (A) and FG (B) and the accuracy of the phase difference. However, since the accuracy of the signals FG (A) and FG (B) is determined by the accuracy of the detection element, it is not possible to obtain a pulse of m times higher accuracy as it is. For example, the cycle may be irregular or the tooth may be missing.

Therefore, in the present invention, a simple circuit can be used to generate a pulse with high accuracy.

[0022]

According to a first aspect of the present invention, there is provided a pulse generating circuit comprising a plurality of first adding means for weighting and adding first and second sine wave signals having a predetermined phase difference; The output signal of the first adding means is compared with the reference value to obtain a plurality of first signals having different phase differences θ (0 ≦ θ ≦ π / 2) from the first sine wave signal. A plurality of first comparators, and a phase inversion means for inverting the phase of the first sine wave signal to form a third sine wave signal;
A plurality of second adding means for weighting and adding the third sine wave signal and the second sine wave signal; comparing the output signals of the plurality of second adding means with a reference value to each of the first sine wave signals; Phase difference θ (π / 2 <θ <π) different from wave signal
A plurality of second comparators for obtaining a plurality of second signals having the following formula: and a frequency which is a predetermined multiple of a frequency of a first sine wave signal based on the plurality of first signals and the plurality of second signals. And pulse generating means for generating a pulse having the following.

According to a second aspect of the present invention, there is provided a pulse generating circuit comprising: a plurality of adding means for weighting and adding first and second sine wave signals having a predetermined phase difference; output signals of the plurality of adding means and a reference value; And a plurality of comparators each of which obtains a plurality of signals having a phase difference different from each other with respect to the first sine wave signal, based on the output signals of the plurality of comparators, the frequency of the first sine wave signal Pulse generating means for generating a pulse having a predetermined frequency, amplitude correcting means for correcting the amplitude of the first or second sine wave signal, and phase correction for correcting the phase of the first or second sine wave signal Means.

[0024]

According to the first aspect of the present invention, a third sine wave signal is formed by inverting the phase of the first sine wave signal, and by using the third sine wave signal, the coefficients u and v are all positive or negative. 0 can be set. As a result, the operation can be performed only by weighting the resistors, so that a comparator with hysteresis can be configured with one differential amplifier, and the circuit scale can be reduced.

According to the second aspect, the amplitude and phase of the first or second sine wave signal can be corrected by the amplitude correction means or the phase correction means, and the accuracy of the first and second sine wave signals can be improved. Instead, a pulse having a frequency that is a predetermined multiple of the frequency of the first sine wave signal can be obtained with high accuracy.

[0026]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of the dynamic tracking circuit.

In the figure, 90 ° from a frequency generator (FG) attached to the rotating shaft of a capstan motor.
The phase-shifted frequency signals FG (A) and FG (B) are FG
The signal is supplied to the speed detection circuit 12 via the amplifier 11. The speed detection circuit 12 detects the tape speed s from the frequency signal FG (A), and the speed information is supplied to the track tilt waveform output unit 13. The waveform output section 13 outputs a track inclination waveform signal STT corresponding to the tape speed s, and the waveform signal STT is supplied to the adder 61.

Assuming that the gain relative to the tape speed is a (s) and the tape speed is s (s = n at n-times speed), the amplitude r of the gradient waveform signal STT is as follows.

## EQU1 ## It can be obtained by r = a (s). (S-1).

The servo reference signal SCL for every fourth track detected from the control track 3 is supplied to the position detection circuit 22 via the CTL amplifier 21. Output signals FG (A) and FG (B) of the FG amplifier 11 are supplied to the pulse generation circuit 23. The pulse generating circuit 23 outputs a pulse P32 having a frequency 32 times the frequency of the frequency signal FG (A).
Supplied to

In the position detecting circuit 22, the servo reference signal S
The tape position x is detected by using CL as a reset signal and counting the pulse P32, and the tape position information is supplied to the tracking waveform output unit 24. Tape speed information is supplied from the speed detection circuit 12 to the waveform output unit 24. Then, a tracking waveform signal STK corresponding to the tape position x is output from the waveform output section 24, and the waveform signal STK is supplied to the adder 61.

The amplitude h of the waveform signal STK is such that the gain of the track pitch is p (s), the delay time from the detection of the tape position x to the actual tracking with the data is q, and the unit time advances at +1 times speed. Assuming that the distance is xo, the tape speed is s (s = n at n times speed), and the amount corresponding to the track pitch is c,

H = p (s) · (mod (x + q · xo · s,
c) -0.5c). Here, mod (x + q · xo · s, c) is
The remainder is (x + q · xo · s) / c, which is a number between 0 and c.

The tracking waveform output section 24 is supplied with track ID information from a signal processing circuit (not shown). From this ID information, it is possible to know which track the head is scanning, and during playback, the heads Ha (Ha '), H
The tracking waveform signal STK is adjusted so that b (Hb '), Hc (Hc'), and Hd (Hd ') scan tracks A, B, C, and D, respectively.

An output signal SSG of a strain gauge (not shown) attached to the bimorph is supplied to a ringing waveform output section 32 via an SG amplifier 31. This signal SSG indicates the movement of the head, and this signal SSG
The size and position of the ringing can be known more. A ringing waveform signal SRN corresponding to the magnitude and position of the ringing is output from the waveform output unit 32, and the waveform signal SRN is supplied to the adder 61.

The reproduced RF signals Sa and Sb from the heads Ha and Hb are supplied to envelope detection circuits 41a and 41b, and output from the envelope signals S and Sb, respectively.
ae and Sbe are supplied to the track shift detecting circuit 42. In this track shift detecting circuit 42, the envelope signal Sa
The difference signal between e and Sbe is calculated, and this difference signal is supplied to the tracking error correction waveform output unit 43 as tracking error information. The waveform output section 43 sets the tracking error correction waveform signal STC so that the difference signal becomes zero.
And the waveform signal STC is supplied to the adder 61.

Further, the track tilt waveform signal STT and the tracking waveform signal STK are modified based on the difference signal between the envelope signals Sae and Sbe. Details regarding this modification will be described later.

In the adder 61, the signals STT, STK, STC and SRN are added, and the added signal is supplied as a drive signal to the bimorph via a high-pass filter 62 and a drive amplifier 63.

The dynamic tracking circuit shown in FIG. 1 is for the bimorph of the A channel on which the heads Ha, Hb, Hc 'and Hd' are mounted.
The configuration for the B-channel bimorph on which Ha 'and Hb' are mounted is similarly configured. In that case, the reproduced RF signals Sc and Sd from the heads Hc and Hd are used to detect the track deviation.

FIG. 2 shows a configuration example of the track tilt waveform output section 13, the tracking waveform output section 24, the tracking error correction waveform output section 43, and the ringing waveform output section 32.

In FIG. 1, reference numeral 101 denotes a PROM in which reference waveform data has been written. The PROM 101 has gradient waveform data for obtaining a track gradient waveform signal, joint waveform data for obtaining a joint waveform signal of a tracking waveform signal, constant data for obtaining a tracking error correction waveform signal, and ringing waveform signal. Is stored in advance. These waveform data are written for two channels A and B, respectively (FIGS. 3A to 3H show analog waveforms corresponding to eight types of waveform data).

A CPU bus 102 is connected to the dual port RAM 103. This RAM 103
Is written with coefficient data corresponding to the eight types of waveform data stored in the PROM 101. here,
The coefficient data corresponding to the gradient waveform data is determined by the CPU (not shown) from the tape speed information from the speed detection circuit 12 (see FIG. 1) (see Equation 1). The coefficient data corresponding to the joint waveform data has a constant value. The coefficient data corresponding to the ringing waveform data is determined by the CPU from the signal SSG from the strain gauge.
The coefficient data corresponding to the fixed data is determined by the CPU based on the tracking error information from the track shift detecting circuit 42.

A pulse signal SPG (one per head rotation) indicating the rotational phase of the head from a pulse generator (drum PG) attached to the rotary drum 7 (see FIG. 23).
Is supplied to the address counter 104 as a reset signal. As a clock of the address counter 104, a frequency signal SFG (shown in FIG. 4A) from a frequency generator (drum FG) attached to the rotating drum 7
Is supplied. Thus, the count output of the address counter 104 changes according to the rotational position of the head,
It is repeated with one rotation cycle.

The frequency signal SFG is supplied to the address counter 105 as a reset signal. The frequency signal S is used as a clock of the address counter 105.
A clock CK synchronized with FG is supplied. The clock CK may be at least eight times the frequency of the signal SFG.
B shows a tenfold magnification. Thus, the count output of the address counter 105 changes from “0” to “7” within each cycle of the frequency signal SFG (shown in FIG. 4C).

The count outputs of the address counters 104 and 105 are P and P, respectively, as upper and lower address signals.
It is supplied to the ROM 101. Then, eight types of waveform data are repeatedly read from the PROM 101 at one rotation cycle of the head. In this case, eight types of waveform data are read out in a time-division manner by using lower address signals.
That is, one sample data of eight types of waveform data is read out in each cycle of the frequency signal SFG.

The waveform data output from the PROM 101 is converted into an analog signal by the D / A converter 106 and supplied to the multiplier 107.

The count outputs of the address counters 104 and 105 are supplied to an address decoder 108.
The gradient waveform signal STT, the tracking waveform signal STK, and the ringing waveform signal SRN can be generated by multiplying the gradient waveform data, the joint waveform data, and the ringing waveform data by constant coefficient data, respectively. Equal over one rotation cycle. Therefore, the same address signal is output from the address decoder 108 at the timing when the gradient waveform data, the joint waveform data, and the ringing waveform data are read from the PROM 101.

On the other hand, the tracking error correction waveform signal STC
Can be generated by multiplying constant data by coefficient data that changes based on tracking error information,
The coefficient data changes as needed depending on the rotational position of the head. Therefore, at the timing when the constant data is output from the PROM 101, different address signals are sequentially output from the address decoder 108.

The address signal output from the address decoder 108 is supplied to the RAM 103. This RAM1
In 03, one coefficient data is written corresponding to each of the gradient waveform data, the joint waveform data and the ringing waveform data for two channels, and a plurality of coefficient data corresponding to the constant data for two channels. Is written.

From the RAM 103, the address decoder 10
According to the address signal from 8, coefficient data corresponding to eight types of waveform data is read out in a time-division manner. The coefficient data is converted into an analog signal by the D / A converter 109 and supplied to the multiplier 107. Here, dual port RA
As a characteristic of M103, when two sets of addresses match, only the access with the higher priority is made valid,
The other is ignored, but in this example the D / A converter 109
The priority is given to the address and data on the side to prevent interruption of the reading of the coefficient data.

The multiplier 107 multiplies the slope waveform data, the joint waveform data, the ringing waveform data, and the constant data from the PROM 101 by the corresponding coefficient data. Therefore, the multiplier 107 outputs the slope waveform signals STTA and STTB of the A and B channels, the joint waveform signals SCNA and SCNB, and the ringing waveform signal SR.
NA, SRNB and tracking error correction waveform signal STCA
, STCB are output in a time-division manner, and the output signals are supplied to a sample-and-hold circuit 110. FIG. 5 shows an output signal of the multiplier 107. However, illustration of the tracking error correction waveform signals STCA and STCB is omitted for simplification of the drawing.

The count output of the address counter 105 is supplied to the sample and hold circuit 110 as a sampling timing signal, and eight kinds of signals of the A and B channels are separately sampled and held.

The slope waveform signals STTA and STTB, the ringing waveform signals SRNA and SRNB, and the tracking error correction waveform signals STCA and STCB output from the sample and hold circuit 110 for the A and B channels are respectively added to an adder 61.
A, 61B.

The CPU bus 102 is connected to a data latch circuit 111. In this latch circuit 111, C
The pattern selection data of the PROM 101 from the PU is latched. As a result, the pattern of the ringing waveform data read from the PROM 101 is selected, and the adjustment is performed so that a ringing waveform signal corresponding to the ringing position is obtained.

The CPU bus 102 is connected to data latch circuits 121 and 122. This latch circuit 12
At steps 1 and 122, the amplitude data (see Equation 2) of the tracking waveform signal for two channels from the CPU is latched. In this case, the latch circuit 121 latches the next (N) amplitude data of the A and B channels, while the latch circuit 1
At 22, the (N-1) amplitude data before the A and B channels is similarly latched.

The output signals of the latch circuits 121 and 122 are
The signals are converted into analog signals by D / A converters 123 and 124 and supplied to sample and hold circuits 125 and 126, respectively. The pulse signal SPG is supplied to the sample and hold circuits 125 and 126 as a reference signal for sampling timing.

The sample and hold circuit 125 samples and holds the next amplitude signals of the A and B channels with a half-rotational phase difference.
The amplitude signal before the B channel is sampled and held with a phase difference of half a rotation.

The next amplitude signal and the previous amplitude signal of the A channel output from the sample hold circuits 125 and 126 are supplied to a subtractor 127A, and the next amplitude signal is subtracted from the previous amplitude signal. The difference signal (step signal) from the subtractor 127A is supplied to a multiplier 128A, and is multiplied by the A-channel joint waveform signal SCNA obtained from the sample-and-hold circuit 110. Then, the multiplier 128A
Outputs a joint waveform signal SCNA 'corresponding to the difference between the next amplitude signal and the previous amplitude signal.
A and is added to the next amplitude signal. As a result, a tracking waveform signal STKA (shown in FIG. 6) in which the previous amplitude signal and the next amplitude signal are naturally connected is output from the adder 129A, and supplied to the adder 61A.

The sample and hold circuits 125 and 12
The next amplitude signal and the previous amplitude signal of the B channel output from 6 are supplied to the subtractor 127B, and the next amplitude signal is subtracted from the previous amplitude signal. The difference signal (step signal) from the subtractor 127B is supplied to the multiplier 128B, and is multiplied by the B-channel joint waveform signal SCNB obtained from the sample-and-hold circuit 110. And the multiplier 12
8B outputs a joint waveform signal SCNB 'corresponding to the difference between the next amplitude signal and the previous amplitude signal.
29B and is added to the next amplitude signal. As a result, the adder 129B outputs a tracking waveform signal STKB in which the previous amplitude signal and the next amplitude signal are naturally connected and is supplied to the adder 61B.

In the adder 61A, the signals STTA, STKA,
SRNA and STCA are weighted and added, and the added signal SAB is output to the high-pass filter 62 and the drive amplifier 6.
3 is used as a drive signal for the A channel bimorph.

In the adder 61B, the signals STTB, STKB,
SRNB and STCB are weighted and added, and the added signal SBB is added to the high-pass filter 62 and the drive amplifier 6.
A drive signal for a B-channel bimorph is provided via the line 3.

Next, a specific configuration of the pulse generation circuit 23 will be described. 7, FG (A) and FG (B) are output from the FG amplifier 11 (see FIG. 1), respectively.
It is a substantially sinusoidal signal (frequency signal) having a phase difference of °.

The signal FG (A) is supplied to a circuit section 203 having a comparator with a resistor and a hysteresis via a series circuit of a buffer amplifier 201 and a subtractor 202.

The output signal of the subtracter 202 is supplied to an inverting amplifier 204 having a gain of 1, and the signal FG (A) 'from the inverting amplifier 204 is supplied to a circuit section 203.

The signal FG (B) is supplied to the buffer amplifier 205,
The signal is supplied to the circuit unit 203 via a series circuit of a subtractor 206, an adder 207, and a multiplier 208. Subtractor 202
Is supplied to the adder 207 via the multiplier 209.

The output signals of the subtracter 202 and the multiplier 208 are converted into digital signals by the A / D converter 210 and supplied to the CPU 100 via the CPU bus 102. The subtraction signal and the multiplication signal from the CPU 100 via the CPU bus 102 are converted into analog signals by the D / A converter 211 and supplied to the subtractors 202 and 206 and the multipliers 208 and 209.

The circuit section 203 includes one circuit including a resistor and a comparator with hysteresis as shown in FIG.
Six are provided. The input signals Si1 and Si2 are connected to the resistor R
1 and R2, and supplied to the negative input terminal of the comparator A1. The resistors R1 and R2 are connected to the signal Si1,
This is a resistor that determines the weight of Si2. The comparator A1 is a comparator whose output is inverted symmetrically to a positive voltage and a negative voltage.

The output terminal of the comparator A1 is a resistor R3
And R4 are grounded through a series circuit, and the connection point of these resistors R3 and R4 is connected to the positive input terminal of the comparator A1. The resistors R3 and R4 are resistors determined by the amplitude of Vin, the amplitude of Vout, and the amount of hysteresis H.

The output terminal of the comparator A1 is grounded via a series circuit of a diode D1 and a resistor R5, and an output signal So is obtained from a connection point between the diode D1 and the resistor R5. The diode D1 and the resistor R5 are limiters of the output amplitude.

The input signals Si1 and Si2 and the resistors R1 to R4 in the sixteen circuits provided in the circuit section 203 and having the configuration shown in FIG. 8 are set as shown in FIG. As a result, the πk / 16
A signal So having a phase difference of (k = 0, 1,..., 15)
0 to So15 are obtained. These signals So0 to So15 are rectangular wave signals with a duty of 50%.

The resistors R1 to R4 are obtained as follows.

It is assumed that Vin = a · sin (t + θ). θ is the phase difference from FG (A), where 0 ≦ θ <π. Here, Vin = a (cos θ · sint + sin θ · cos
t) and FG (A) = a · sint, FG (B) = a · cost, that is, if it is considered that the amplitudes of FG (A) and FG (B) are equal and there is no offset, Vin = cos θ FG (A) + sinθ · FG (B) For π / 2 <θ <π, F instead of FG (A)
If G (A) ′ = − FG (A) is used, Vin = | cos θ | · FG (A) + sin θ · FG (B) (0 ≦ θ ≦ π / 2) Vin = | cos θ | · FG (A) ′ + sin θ · FG (B) (π / 2 <θ <π), and R1 and R2 are obtained as R1: R2 = sin θ: | cos θ |. At this time, R1 = {Z · (sin θ + | cos θ |)} / | cos
θ | R2 = {Z · (sin θ + | cos θ |)} / sin θ Z is a combined (parallel) resistance value of R1 and R2.

Since the amplitude of Vin is represented by a / (| cos θ | + sin θ), the output of the comparator is ± V,
R4 / (R3 + R4) = {a / (| cos θ | + sin θ)} / V · H = a / V · to provide a hysteresis that does not reverse up to 1 / H (H is the amount of hysteresis) of the amplitude of H · (| cos θ | + sin θ) and R3 and R4 are obtained. At this time, R3 = {Z ′ · V · H · (sin θ + | cos θ |)} / a R4 = {Z ′ · V · H · (sin θ + | cos θ |)} / ｛V · H · (sin θ + | cos θ |) -A｝. Z 'is a combined (parallel) resistance value of R3 and R4.

Thereafter, the values of R1 to R4 are determined in consideration of the input impedance of the comparator A1 and the like.

As described above, in the present example, in the range of π / 2 <θ <π, the inverted signal FG (A) ′ of the signal FG (A) is used, so that the circuit related to each of the signals So0 to So15 is FIG.
And the configuration of the entire circuit is simplified, and the calculation of the resistance value is also simplified.

Returning to FIG. 7, 16 signals So0 to So15 (shown in FIG. 10A) output from the circuit unit 203 are supplied to an exclusive OR circuit 212, and the exclusive OR circuit 212 outputs the signal FG (A). A 16-fold pulse P16 is output (shown in FIG. 10B). The pulse P16 is supplied to the edge extracting circuit 213, and the rising and falling edges of the pulse P16 are extracted by the clock CK 'which is sufficiently faster than the pulse P16. Thus, the signal F is output from the edge extraction circuit 213.
A pulse P32 32 times as large as G (A) is output (FIG. 10C).
Illustrated).

The signal S output from the circuit unit 203
o0 and So8 are supplied to the timer circuit 214. The timer circuit 214 detects the time difference (corresponding to the phase difference) between the signals So0 and So8 and the period of the signal So0.
These detection signals are sent to the CPU 1 via the CPU bus 102.
00 is supplied.

In the above-described circuit section 203, the signal FG
(A) and FG (B) have a phase difference of 90 ° and the same amplitude,
If the condition of no offset is not satisfied,
It becomes impossible to obtain signals So0 to So15 having a phase difference of πk / 16 (k = 0, 1,..., 15). Therefore, in the pulse generation circuit 23 shown in FIG.
The following adjustment is automatically performed by the control (see FIG. 11).

First, the tape is run in the FWD direction (step 221). Then, the gain of the multiplier 209 is set to 0, and the gain of the multiplier 208 is set to 1 (step 22).
2).

Next, the offset (DC voltage) of the signals FG (A) and FG (B) detected by the A / D converter 210 becomes zero.
A subtraction signal (voltage) is supplied to the subtracters 202 and 206 so that
(Step 223).

Next, the signal S detected by the timer circuit 214
The multiplier 209 is provided with a multiplication signal (gain) so that the time difference between o0 and So8 is 1/4 of the period of the signal So0 (step 224).

Finally, the multiplier 208 is provided with a multiplication signal (gain) so that the amplitude of the signal FG (A) detected by the A / D converter 210 becomes equal to the amplitude of the signal FG (B) ( Step 225).

With such adjustment, the signals FG (A),
Without being affected by the accuracy such as the phase difference and amplitude of FG (B),
A highly accurate pulse P32 can be obtained.

The above-mentioned envelope signals Sae, Sbe
The adjustment of the track tilt waveform signal STT and the tracking waveform signal STK based on the difference signal is performed as follows.

In FIG. 24, the heads are mounted at a fixed interval d. In this example, the interval between the heads Ha and Hb of the A channel and the interval between the heads Hc and Hd of the B channel are d '(<d). (Shown in FIG. 12), and the head H
The offset △ d (d−d) between a and Hb (between Hc and Hd)
d ') is provided.

Here, the solid line in FIG. 13A is the head scanning locus when the track inclination waveform signal STT is proper, and the solid line in FIG. 13B is the head scanning locus when the track inclination waveform signal STT is not proper. The envelope signals of the reproduced RF signal corresponding to the head scanning trajectories of the solid lines a and b are shown in FIGS. 14A and 14B, respectively.
It becomes as shown in.

In this embodiment, the distance between the heads Ha and Hb (Hc, H
Since the offset △ d is provided between (d) and (d) (see FIG.
If the ramp waveform signal STT is not appropriate, the head H
The envelope signals Sae and Sbe of the reproduced RF signals a (Hc) and Hb (Hd) are as shown in FIGS. 16A and 16B, respectively, and the difference signal is as shown in FIG.

The direction of the track shift at the position where the envelope exists can be determined by the sign of the difference signal. And
By integrating (or adding) the front end Ls and the end Le of the envelope, and comparing the levels, it is possible to detect a tilt error (direction and magnitude of tilt).

Track inclination waveform output section 13 (see FIG. 1)
In, the adjustment of the amplitude, that is, the optimization of a (s) in Equation 1 is performed based on the tilt error information. In this case, adjustment is performed so that the levels of the front end Ls and the end Le are matched.

FIG. 17 shows a track shift when p (s) in Equation 2 is not appropriate. If the tape position corresponding to half of the track pitch is maintained and the tracking waveform signal STK is not corrected, the reproducing head scans at the position. If p (s) is appropriate, the head is at the appropriate position of or, and tracking is good.

However, when the amplitude is small or large, the head will not be at the proper position of or, and a track shift will occur. In this case, p
It can be optimized by changing (s).

Even when p (s) is not appropriate, the direction of the track shift can be detected by comparing the envelope signals Sae and Sbe. In this case, the envelope signals Sae, S
Since the difference signal of be changes for each scan as shown in FIG. 18, it is determined based on the result of integration (addition) of the difference signal in one scan period.

Tracking waveform output section 24 (see FIG. 1)
In, the adjustment of the amplitude, that is, the optimization of p (s) in Equation 2 is performed based on the information of the track shift. FIG. 19 shows the flow of this processing. Integration (addition) of envelope signals Sae, Sbe for each scan
Let SA and SB be the results.

First, it is determined whether the head is swung in the side or the 'side (step 301).
If it is the side, it is determined which of SA and SB is larger (step 302). P when SA> SB
(S) is increased (step 303), and if SA <SB, p (s) is decreased (step 304).

In step 301, if it is on the 'side,
It is determined which of SA and SB is larger (step 3
05). When SA <SB, p (s) is increased (step 303), and when SA> SB, p (s) is decreased (step 304).

Actually, since the pattern of the change of the amplitude h (see equation 2) changes variously depending on the tape speed, it is necessary to set the amount of increase or decrease according to the pattern.

Further, the DC offset can be adjusted based on the difference signal between the signals SA and SB. FIG.
0 indicates the flow of this processing. α is a variable for determining a DC offset.

First, it is determined which of the signals SA and SB is larger (step 401). If SA> SB, α is increased (step 402), and if SA <SB, α is decreased (step 403). The adjustment of the DC offset is performed, for example, by using the tracking waveform output unit 24.
This is performed by adjusting the amplitude of the tracking waveform signal STK.

As described above, the envelope signals Sae, S
Using be, basic parameters a (s), p
By modifying (s) and α, tracking can be maintained optimally even if the characteristics change or the tape conditions change.

According to the pulse generation circuit 23 of this embodiment, π /
In the range of 2 <θ <π, the inverted signal FG of the signal FG (A)
Since (A) 'is used, the comparator A1 with hysteresis can be constituted by one differential amplifier in the circuit (shown in FIG. 8) relating to each of the signals So0 to So15, and the circuit scale can be reduced. The values of the resistors R1 to R4 are
Since the half of the circuit in 3 is equal to the other half (see FIG. 9), the design can be easily performed.

The signal S output from the circuit unit 203
The phase difference between o0 and So8 and the signals FG (A) and FG (B)
Of the signals FG (A) and FG (B) to control the offset, amplitude and phase of the signals FG (A) and FG (B).
A highly accurate pulse P32 can be obtained regardless of the accuracy of FG (B).

According to the above embodiment, the signal FG
Although the example of obtaining a pulse 32 times as large as (A) has been described, generally, a pulse of m times can be obtained in the same manner.

In the above embodiment, the signal FG
(A) and FG (B) have a phase difference of 90 °, but basically kπ (k = o, ± 1, ± 2,...)
Any other phase difference output is effective.

[0102]

According to the first aspect, the third sine wave signal obtained by inverting the phase of the first sine wave signal is formed.
By using the sine wave signal of the above, all the coefficients of the signals of different phases can be made positive or 0, and the operation can be performed only by the weighting of the resistor. Therefore, a comparator with hysteresis can be configured with one differential amplifier. The circuit scale can be reduced. Further, since half of the circuit is equal in coefficient to the other half, design can be facilitated.

According to the second aspect, the amplitude and phase of the first or second sine wave signal can be corrected by the amplitude correction means or the phase correction means, and the accuracy of the first and second sine wave signals can be corrected. Irrespective of this, it is possible to obtain a pulse having a frequency that is a predetermined multiple of the frequency of the first sine wave signal with high accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a dynamic tracking circuit.

FIG. 2 is a block diagram illustrating a configuration of a waveform output unit.

FIG. 3 is a diagram showing waveform data (analog display).

FIG. 4 is a timing chart for explaining an address signal.

FIG. 5 is a diagram showing a time-division combined signal before sample hold.

FIG. 6 is a diagram showing a tracking waveform signal.

FIG. 7 is a block diagram illustrating a configuration of a pulse generation circuit.

FIG. 8 is a connection diagram showing a part of a circuit constituting the pulse generation circuit.

FIG. 9 is a diagram showing a combination of input and resistance in the example of FIG. 8;

FIG. 10 is a diagram showing a timing chart for explaining a pulse generation operation.

FIG. 11 is a flowchart illustrating an adjustment operation in the pulse generation circuit.

FIG. 12 is a diagram showing an example of the arrangement of heads.

FIG. 13 is a diagram showing a head scanning locus.

FIG. 14 is a diagram showing an envelope signal.

FIG. 15 is a diagram showing an offset between heads.

FIG. 16 is a diagram showing an envelope signal.

FIG. 17 is a diagram showing a track shift.

FIG. 18 is a diagram illustrating a difference signal between envelope signals in each scan.

FIG. 19 is a flowchart illustrating a process of adjusting p (s) in a tracking waveform signal.

FIG. 20 is a flowchart showing a process of adjusting a variable α for determining a DC offset.

FIG. 21 is a diagram showing a track pattern in the D-1 format.

FIG. 22 is a diagram showing an arrangement of audio sectors.

FIG. 23 is a diagram showing a configuration of a rotary magnetic head device.

FIG. 24 is a diagram showing a head arrangement.

FIG. 25 is a diagram showing a head scanning locus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Magnetic tape 7 Rotating drum 12 Speed detection circuit 13 Track inclination waveform output part 22 Position detection circuit 23 Pulse generation circuit 24 Tracking waveform output part 32 Ringing waveform output part 41a, 41b Envelope detection circuit 42 Track deviation detection circuit 43 Tracking error correction waveform Output unit 61 Adder 100 CPU 101 PROM 103 Dual port RAM 104, 105 Address counter 107 Multiplier 108 Address decoder 110 Sample hold circuit 202, 206 Subtractor 203 Circuit unit composed of a comparator with resistance and hysteresis 204 Inverting amplifier 207 Adder 208 , 209 Multiplier 212 Exclusive OR circuit 213 Edge extraction circuit 214 Timer circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 H04N 5/782-5/783 G11B 5/588 H03K 5/08 G11B 20 / 12 103

Claims (2)

(57) [Claims] 1. A plurality of first adding means for weighting and adding first and second sine wave signals having a predetermined phase difference, and comparing output signals of the plurality of first adding means with a reference value. A plurality of first comparators for obtaining a plurality of first signals each having a phase difference θ (0 ≦ θ ≦ π / 2) different from each other with respect to the first sine wave signal; Phase inverting means for inverting the phase of the wave signal to form a third sine wave signal; a plurality of second adding means for weighting and adding the third sine wave signal and the second sine wave signal; The output signals of the plurality of second adding means are compared with a reference value, and a plurality of second signals having different phase differences θ (π / 2 <θ <π) with respect to the first sine wave signal, respectively. A plurality of second comparators for obtaining the signals of the above, the plurality of first signals and the plurality of Based on the second signal, the pulse generating circuit comprising: a pulse generating means for generating a pulse having a predetermined multiple of the frequency of the frequency of the first sinusoidal signal. 2. A plurality of adding means for weighting and adding first and second sine wave signals having a predetermined phase difference, and comparing the output signals of the plurality of adding means with a reference value to each of the first and second sine wave signals. A plurality of comparators for obtaining a plurality of signals having different phase differences from each other with respect to the sine wave signal, and having a frequency that is a predetermined multiple of the frequency of the first sine wave signal based on output signals of the plurality of comparators Pulse generating means for generating a pulse; amplitude correcting means for correcting the amplitude of the first or second sine wave signal; and phase correcting means for correcting the phase of the first or second sine wave signal. A pulse generation circuit characterized by the above.