JP3089138B2 - Quantization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantizing circuit for accurately transmitting level information having a relatively short pulse width in an analog signal when the analog signal is transmitted over a long distance and converted from analog to digital.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIGS. When the A / D conversion is performed on the waveform of FIG. 6B showing the enlargement of the analog video signal shown in FIG. 6A with a sampling clock having a period shown in FIG. ). However, in the waveform of FIG. 6D, A, B, and C that can be effective information
The level of the section may disappear depending on the timing of the sampling clock.

Therefore, as shown in FIG. 5, an analog signal input is delayed by a time delay for peak detection by a delay unit 1 and is input to a level holding unit 2 while a pulse filter 3 is input.
Then, only the high frequency component is passed through the analog signal input, and the peak detection unit 4 detects the peak. Using the detection signal output from the peak detection unit 4 as a trigger, the level holding unit 2 holds the peak level of the analog input signal for a fixed time (slightly longer than the A / D sampling clock).

Accordingly, a waveform as shown in FIG. 5 (e) is obtained, and even if this is subjected to A / D conversion at the same cycle as above, the conversion result as shown in FIG. , B level will be transmitted without fail.

[0005]

Conventionally, there is no problem when a signal having a level higher than the peak level of the portion A does not appear within the holding time as in the portion A shown in FIG.
If a signal C having a higher level than the signal B occurs immediately after the start of holding the peak level as in the signal B, the signal C is ignored. Therefore, an object of the present invention is to provide a quantization circuit that converts an input analog signal into a signal that can be reliably converted into a digital signal.

[0006]

In order to achieve the above object, the present invention provides a first filter means for passing only a low frequency component of an input analog signal, and a first filter means for passing only a high frequency component. And A / A for converting the output of the second filter means into analog / digital.
D conversion means, quantization means for quantizing the output of the A / D conversion means, D / A conversion means for digital / analog conversion of the output of the quantization means, and output of the first filter means. There is provided a quantization circuit including an addition unit for adding the output of the D / A conversion unit.

[0007]

In the quantization circuit of the present invention configured as described above, a signal including a high-frequency band is quantized without losing the level of a high-frequency pulse to process a wide-band signal. Furthermore, the circuit scale can be reduced and the transmission means can be simplified without losing the information of the signal.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. First, an outline of the present embodiment will be described with reference to FIGS. As shown in FIG. 1, the quantization circuit according to the present embodiment includes a low-pass filter (hereinafter, referred to as an LPF) 10 that passes only a low-frequency component to an input signal S1 according to a clock signal S2, and a high-frequency component only. A high-pass filter (hereinafter, referred to as HPF) 11 that passes
An A / D converter 12 for converting the output of the PF 11 from analog to digital, a quantization circuit 13 for quantizing the output of the A / D converter 12, and a digital / analog converter for converting the output of the quantization circuit 13 to digital / analog. / A converter 14, LPF10 and D / A converter
14 and an adder 15 for adding each output.

In this embodiment having the above-described structure, as shown in FIG.
10, the signal is converted into an envelope signal S3.
An HPF output signal S4 is obtained by the HPF 11. This HP
The analog-to-digital conversion of the F output signal S4 is performed by the A / D converter 12 at a frequency sufficiently higher than the frequency component of the HPF output signal S4. The analog / digital converted signal is converted by the quantization circuit 13 into a signal S5 having a maximum absolute value as a representative value every N cycles of the A / D conversion clock signal. Note that the length of the N cycle needs to match the processing speed of the digital / analog conversion for the output of the quantization circuit 13. The signal S5 is converted by the D / A converter 14 into an analog signal. The signal S5 converted into an analog signal and the envelope signal S3 are added by the adder 15 to obtain a signal S6.

Next, the above-described embodiment will be described in detail with reference to FIGS. As shown in FIG. 3, the quantization circuit according to the present embodiment includes a low-pass filter (hereinafter, referred to as an LPF) that allows only a low-frequency component to pass through an input signal.
20; a high-pass filter (hereinafter referred to as HPF) 21 for passing only high-frequency components; and a pulse that indicates a rising edge and a falling edge of the input signal.
Edge pulse generator 22 for controlling the pass frequency band of F21
An A / D converter 23 for converting the output of the HPF 2 from analog to digital in accordance with the clock signal CLK; a latch circuit 24 for latching the output of the A / D converter 23;
And a comparator 25 which compares the absolute value of each output of the A / D converter 23
, A frequency divider 26 for dividing the frequency of the clock signal CLK, and a frequency divider
An OR gate circuit 27 that sets the latch timing of the latch circuit 24 by the logical sum of the output of the comparator 26 and the output of the comparator 25; a latch circuit 28 that latches the output of the latch circuit 24 with the output of the frequency divider 26 as the latch timing; A D / A converter 29 for digital / analog conversion of the output of the latch circuit 28;
And an analog adder 30 that adds the output of the D / A converter 29 in an analog manner.

In this embodiment, an edge pulse S2 is obtained from an input signal S1 by an edge pulse generator 22, as shown in FIG. The edge pulse S2 gives a timing to instantaneously increase or decrease the time constant of the LPF 20 and the HPF 21 at the rising and falling portions of the input signal S1. As a result, the rising and falling edges of the output of the LPF 20 are sharp and the HPF 20
A DC component can be prevented from entering the output 21.

The HPF output S4 is a constant clock signal S
The signal is A / D converted at step 7 and converted to a signal S9. Signal S8
Is a clock obtained by dividing the clock signal S7 by N, and A /
The clock is used to latch the output of the D converter 23.
The absolute value of the output of the latch circuit 24 and the output of the A / D converter 23 are compared for each clock cycle of the clock signal S7, and if the output of the A / D converter 23 is larger than the output of the latch circuit 24. In each case, the comparison result signal is input to the latch circuit 24 through the OR gate circuit 27 each time. The latch circuit 28 operates at the timing of the clock signal S8.
As a result, the data having the largest absolute value within one cycle of the clock signal S8 as shown by the signal S10 is latched in the latch circuit 28.

The output of the latch circuit 28 is a clock signal S8
D / A conversion is performed at the timing shown in FIG. This D / A converter 29
Output is obtained by quantizing the output of the HPF 21 in units of N data. Finally, the output of the D / A converter 29,
By adding the output of the LPF 20 with the adder 30, a signal S6 as a final output is obtained.

As described above, according to this embodiment, the following advantages are obtained by quantizing a signal such as an analog video having a high frequency band without losing the level of the high frequency pulse.

1) A high-bandwidth analog transmission means is not required. 2) High-speed signal processing means is not required. In addition, by giving independent gains to both the output of the LPF 20 and the output of the HPF 21, high-resolution analog / digital conversion can be performed even if the dynamic range of the A / D converter 23 is insufficient.

[0016]

As described above, according to the present invention, when processing a wide band signal such as an analog video, the circuit scale can be reduced and the transmission means can be simplified without losing the information of the signal. realizable.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of the present invention.

FIG. 2 is a view showing signal waveforms in the embodiment shown in FIG. 1;

FIG. 3 is a detailed configuration diagram showing one embodiment of the present invention.

FIG. 4 is a view showing signal waveforms in the embodiment shown in FIG. 3;

FIG. 5 is a schematic configuration diagram showing a conventional quantization circuit.

FIG. 6 is a diagram showing a signal waveform in a conventional quantization circuit.

[Explanation of symbols]

 10, 20, low-pass filter (LPF) 11, 21, high-pass filter (HPF) 12, 23, A / D converter 13, quantization circuit 14, 29, D / A converter 15, 30, adder

Claims (2)

(57) [Claims] A first filter means for passing only a low-frequency component of an input analog signal, a second filter means for passing only a high-frequency component, and an output of the second filter means A / D for digital conversion
Conversion means and an output of the A / D conversion means .
The maximum value of the absolute value is set as the representative value every N cycles of the lock signal.
Quantizing means for converting the output of the quantizing means into digital signals, a D / A converting means for digital-to-analog converting the output of the quantizing means, and adding the output of the first filter means and the output of the D / A converting means. A quantization circuit comprising an adding means. 2. The apparatus according to claim 1, wherein said first filter means for passing only low-frequency components and the second filter means for passing only high-frequency components are provided with independent gains. 2. The quantization circuit according to 1.