JP3088050B2 - Multilayer circuit board - Google Patents

Multilayer circuit board

Info

Publication number
JP3088050B2
JP3088050B2 JP05064551A JP6455193A JP3088050B2 JP 3088050 B2 JP3088050 B2 JP 3088050B2 JP 05064551 A JP05064551 A JP 05064551A JP 6455193 A JP6455193 A JP 6455193A JP 3088050 B2 JP3088050 B2 JP 3088050B2
Authority
JP
Japan
Prior art keywords
circuit board
resin
multilayer circuit
insulating layer
resin content
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP05064551A
Other languages
Japanese (ja)
Other versions
JPH06275951A (en
Inventor
憲一 刈屋
雅之 野田
宏 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Kobe Electric Machinery Co Ltd
Original Assignee
Shin Kobe Electric Machinery Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Kobe Electric Machinery Co Ltd filed Critical Shin Kobe Electric Machinery Co Ltd
Priority to JP05064551A priority Critical patent/JP3088050B2/en
Publication of JPH06275951A publication Critical patent/JPH06275951A/en
Application granted granted Critical
Publication of JP3088050B2 publication Critical patent/JP3088050B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、部品を表面実装方式で
搭載するのに適した多層回路板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board suitable for mounting components in a surface mounting method.

【0002】[0002]

【従来の技術】近年、電子機器は構成部品の組込みが高
密度化し、これにともなって、電子機器に組込んで使用
される多層回路板への部品実装方式は、挿入方式から表
面実装方式へと移行している。この表面実装方式への移
行にともなって、多層回路板の信頼性向上の要求が高ま
っている。例えば、スルーホール信頼性に関しては熱衝
撃試験で100サイクル以上、耐湿マイグレーション性
に関しては1000時間/108Ω以上が要求されてい
る。また、多層回路板の線膨張係数に関しては、10p
pm/℃以下が必要となっている。これは、リードレス
チップキャリア、フリップチップなどのLSIや抵抗、
コンデンサなどの線膨張係数の小さい部品が直接多層回
路板の表面に半田付けされるため、これら部品と多層回
路板との線膨張係数の不整合による半田接続部分のクラ
ック発生が起こらないようにするためである。従来製造
されている多層回路板は、表面と内層の回路層間の絶縁
層がガラス繊維織布基材エポキシ樹脂で構成されたNE
MA規格FR−4に相当するものであり、その構成は次
のようなものである。 (1)ガラス繊維織布は、Eガラス組成(SiO2:5
4重量%,Al23:12重量%,MgO:1%,Ca
O:23%,Na2O:1%,B23:9%)である。 (2)エポキシ樹脂は、ジシアンジアミドを硬化剤とし
ており、多層回路板として見たときのガラス転移温度は
130℃程度である。 (3)絶縁層の樹脂含有量は、48重量%程度が一般的
である。 (4)内層回路を構成する銅箔は、スルーホールメッキ
と内層回路の接続面積を大きくとってスルーホール信頼
性を高めるために、通常35μm厚さのものが使用され
る。 これらFR−4相当の多層回路板の性能は、スルーホー
ル信頼性については良好であるが、耐湿マイグレーショ
ン性では600時間、線膨張係数は15ppm/℃程度
であり、部品の表面実装時の信頼性に問題を残してい
る。耐湿マイグレーション性については、一般に使用す
るエポキシ樹脂の原料がエピクロルヒドリンなどである
ために硬化した樹脂を粉砕して測定した抽出水導電率が
大きく、このため、ジシアンジアミドを硬化剤としたの
では問題を解決できない。また、多層回路板の線膨張係
数を小さくすることについては、数多くの試みがあるが
工業上好ましいものは見いだされていない。例えば、線
膨張係数の小さな石英ガラス繊維、アラミド繊維、グラ
ファイト繊維、カーボン繊維などの織布を基材とした多
層回路板が提案されている。しかし、石英ガラス繊維を
使用したものは、硬くドリル穴明けが非常にむずかしく
高価でもある。アラミド繊維を使用したものは、穴明け
を行なうと穴の内壁に繊維ケバが残り、スルーホールメ
ッキの障害になると同時に耐湿性に問題が出てくる。グ
ラファイト繊維を使用したものは、繊維自体が導電性を
有しているために、絶縁性が要求される多層回路板には
到底使用できない。
2. Description of the Related Art In recent years, electronic devices have been increasingly integrated with component parts, and accordingly, the method of mounting components on a multilayer circuit board used by being incorporated into electronic devices has been changed from an insertion system to a surface mounting system. And has transitioned. With the shift to the surface mounting method, there is an increasing demand for improved reliability of the multilayer circuit board. For example, through-hole reliability is required to be 100 cycles or more in a thermal shock test, and moisture migration resistance is required to be 1000 hours / 10 8 Ω or more. The coefficient of linear expansion of the multilayer circuit board is 10p
pm / ° C. or less is required. This is for LSIs and resistors such as leadless chip carriers and flip chips,
Since components with low linear expansion coefficient, such as capacitors, are soldered directly to the surface of the multilayer circuit board, it is necessary to prevent the occurrence of cracks in the solder connection part due to mismatch of the linear expansion coefficient between these components and the multilayer circuit board. That's why. Conventionally manufactured multilayer circuit boards have a NE in which an insulating layer between a surface and an inner circuit layer is formed of a glass fiber woven fabric base epoxy resin.
It corresponds to the MA standard FR-4, and its configuration is as follows. (1) The glass fiber woven fabric has an E glass composition (SiO 2 : 5).
4% by weight, Al 2 O 3 : 12% by weight, MgO: 1%, Ca
O: 23%, Na 2 O: 1%, B 2 O 3 : 9%). (2) Epoxy resin uses dicyandiamide as a curing agent, and has a glass transition temperature of about 130 ° C. when viewed as a multilayer circuit board. (3) The resin content of the insulating layer is generally about 48% by weight. (4) In order to increase the connection area between the through-hole plating and the inner-layer circuit to enhance the reliability of the through-hole, the copper foil constituting the inner-layer circuit is usually 35 μm thick. The performance of these multilayer circuit boards equivalent to FR-4 is good for through-hole reliability, but the moisture migration resistance is 600 hours, the linear expansion coefficient is about 15 ppm / ° C., and the reliability at the time of surface mounting of components is high. Has left the problem. As for the moisture migration resistance, since the raw material of the epoxy resin commonly used is epichlorohydrin, etc., the extracted water conductivity measured by grinding the cured resin is large. Can not. There have been many attempts to reduce the linear expansion coefficient of a multilayer circuit board, but no industrially preferred one has been found. For example, a multilayer circuit board using a woven fabric such as quartz glass fiber, aramid fiber, graphite fiber, or carbon fiber having a small linear expansion coefficient as a base material has been proposed. However, those using quartz glass fiber are hard, very difficult to drill, and are expensive. In the case of using aramid fiber, when a hole is drilled, a fiber fluff remains on the inner wall of the hole, which hinders plating of a through hole and also causes a problem in moisture resistance. Those using graphite fibers cannot be used for a multilayer circuit board requiring insulation because the fibers themselves have conductivity.

【0003】[0003]

【発明が解決しようとする課題】このように、従来のF
R−4相当の多層回路板においては、耐湿マイグレーシ
ョン性が良好であり、線膨張係数も小さいという特性バ
ランスの取れたものが見いだされていない。本発明が解
決しようとする課題は、表面と内層に回路を有し回路層
間の絶縁層がガラス繊維織布基材エポキシ樹脂で構成さ
れている多層回路板において、耐湿マイグレーション性
を確保するとともに線膨張係数も小さくし、表面実装信
頼性を向上させることである。
As described above, the conventional F
In a multilayer circuit board equivalent to R-4, there has not been found any one having a good balance of characteristics such as good moisture migration resistance and small linear expansion coefficient. The problem to be solved by the present invention is to provide a multilayer circuit board having a circuit on the surface and an inner layer and an insulating layer between circuit layers made of a glass fiber woven fabric base epoxy resin, while ensuring moisture migration resistance and line resistance. The object is to reduce the expansion coefficient and improve the reliability of surface mounting.

【0004】[0004]

【課題を解決するための手段】上記課題を解決するため
に、本発明に係る多層回路板は、表面と内層に回路を有
し回路層間の絶縁層がガラス繊維織布基材エポキシ樹脂
で構成されているものにおいて、(1)ガラス繊維織布
はそのガラス組成が、SiO2:50〜75重量%、A
23:15〜35重量%、アルカリ土類金属酸化物:
5〜15重量%、アルカリ金属酸化物:3重量%未満で
あり、(2)エポキシ樹脂は、フェノール樹脂を硬化剤
とし多層回路板としてのガラス転移温度が140℃以上
であり、(3)絶縁層全体を平均した樹脂含有量は35
〜45重量%であり、(4)内層回路を構成する銅箔の
厚さは20μm以下であることを特徴とする。絶縁層全
体を平均した樹脂含有量は35〜45重量%であるが、
内層回路板を構成する絶縁層の樹脂含有量より、内層回
路板と表面の回路を接着する絶縁層の樹脂含有量を多く
するのが望ましい。また、内層の回路が複数枚の内層回
路板で構成されているときは、内層回路板同士を接着す
る絶縁層の樹脂含有量も多くするのが望ましい。
In order to solve the above-mentioned problems, a multilayer circuit board according to the present invention has a circuit on a surface and an inner layer, and an insulating layer between circuit layers is made of a glass fiber woven fabric base epoxy resin. (1) The glass fiber woven fabric has a glass composition of SiO 2 : 50 to 75% by weight, A
l 2 O 3 : 15 to 35% by weight, alkaline earth metal oxide:
5 to 15% by weight, alkali metal oxide: less than 3% by weight, (2) epoxy resin has a glass transition temperature of 140 ° C. or more as a multilayer circuit board using a phenol resin as a curing agent, and (3) insulating. The average resin content of the entire layer is 35
(4) The thickness of the copper foil forming the inner layer circuit is not more than 20 μm. The average resin content of the entire insulating layer is 35 to 45% by weight,
It is desirable to make the resin content of the insulating layer that bonds the inner layer circuit board and the surface circuit larger than the resin content of the insulating layer that forms the inner layer circuit board. When the inner circuit is composed of a plurality of inner circuit boards, it is desirable to increase the resin content of the insulating layer that bonds the inner circuit boards together.

【0005】[0005]

【作用】一般に、多層回路板の線膨張係数αは、(数
1)に示すようなSCHAPERYの実験式などに基づ
き、含有する各成分の比率により決定される。線膨張係
数の大きい成分を少なくすることにより、多層回路板全
体としての線膨張係数は小さくなり、本発明に係る多層
回路板は、線膨張係数の小さなガラス繊維織布を基材に
用いるとともに線膨張係数の大きい成分である内層銅
箔、エポキシ樹脂の含有率を少なくして線膨張係数を小
さくし、かつ、他の特性の信頼性も確保したものであ
る。
In general, the coefficient of linear expansion α of a multilayer circuit board is determined by the ratio of each component contained, based on the SCHEPARY empirical formula as shown in (Equation 1). By reducing the component having a large coefficient of linear expansion, the coefficient of linear expansion of the multilayer circuit board as a whole is reduced, and the multilayer circuit board according to the present invention uses a glass fiber woven fabric having a small coefficient of linear expansion for the base material and The linear expansion coefficient is reduced by reducing the content of the inner layer copper foil and the epoxy resin, which are components having a large expansion coefficient, and the reliability of other characteristics is secured.

【0006】[0006]

【数1】 (Equation 1)

【0007】本発明に係る多層回路板に用いるガラス繊
維織布は、基本的には、特開平3−112650号公報
に開示されたものであり、その線膨張係数は従来のFR
−4多層回路板に使用されているガラス繊維織布に比べ
て約半分の3ppm/℃と小さく、かつ、ドリル加工性
も実用上問題ない。ガラス繊維織布のガラス成分組成に
おいて、SiO2比率は、50重量%に達しないと熱膨
張係数が大きくなり、75重量%を越えるとガラス繊維
を紡糸する際、炉の腐食が大きいばかりか、ドリル加工
時のドリルの摩耗が大きくなり、多層回路板の加工性が
悪くなる。Al23の比率は、15重量%に達しないと
熱膨張係数が大きくなり、35重量%を越えるとドリル
加工時のドリルの摩耗が大きくなる。アルカリ土類金属
酸化物の比率は、5重量%に達しないとガラス繊維を紡
糸する際、炉の腐食が大きくなり、ドリル加工時のドリ
ルの摩耗が大きくなる。アルカリ土類金属化合物の比率
は、15重量%を越えると熱膨張係数が大きくなる。ア
ルカリ金属酸化物の比率は、3重量%以上であると熱膨
張係数が大きくなると同時に、吸湿時の電気特性が悪く
なる。これらのことは、上記特開平3−112650号
公報に開示されているとおりである。
The glass fiber woven fabric used in the multilayer circuit board according to the present invention is basically disclosed in Japanese Patent Application Laid-Open No. Hei 3-112650, and has a linear expansion coefficient of the conventional FR.
-4: 3 ppm / ° C., which is about half that of the glass fiber woven fabric used for the multilayer circuit board, and there is no practical problem in drilling workability. In the glass component composition of the glass fiber woven fabric, when the SiO 2 ratio does not reach 50% by weight, the coefficient of thermal expansion increases, and when it exceeds 75% by weight, not only does the furnace corrode greatly when spinning glass fibers, Abrasion of the drill during drilling increases, and the workability of the multilayer circuit board deteriorates. If the Al 2 O 3 ratio does not reach 15% by weight, the coefficient of thermal expansion increases, and if it exceeds 35% by weight, drill wear during drilling increases. If the proportion of the alkaline earth metal oxide does not reach 5% by weight, the corrosion of the furnace increases when spinning glass fibers, and the wear of the drill during drilling increases. When the ratio of the alkaline earth metal compound exceeds 15% by weight, the coefficient of thermal expansion increases. If the ratio of the alkali metal oxide is 3% by weight or more, the thermal expansion coefficient increases and the electrical characteristics during moisture absorption deteriorate. These facts are as disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 3-112650.

【0008】回路を構成する銅箔は、線膨張係数が17
ppm/℃と大きいものであるが、特に内層の回路にお
いて多く占められている銅箔の含有率を少なくするこ
と、すなわち、銅箔の厚さを20μm以下に薄くするこ
とも、線膨張係数を小さくする上で大きな作用をしてい
る。内層回路を構成する銅箔の厚さを薄くすると、スル
ーホールメッキと内層回路との接続面積が小さくなり、
スルーホール信頼性が低下することが心配であるが、こ
の点は、樹脂のガラス転移温度を140℃以上とするこ
とで問題を解決している。スルーホールメッキのための
穴明け加工を行なうと、ドリル刃と多層回路板の穴内壁
がこすれて穴内壁は130℃を越える温度になる。その
ときに生じる樹脂の溶融物が内層回路の銅箔断面に付着
し、このような状態でスルーホールメッキを行なうとス
ルーホールメッキと内層回路の接続面積が益々小さくな
ってスルーホール信頼性が低下すると心配されるわけで
ある。しかし、本発明に係る多層回路板では、多層回路
板として見たときの樹脂のガラス転移温度を140℃以
上としていることから、穴明け加工時に生じる樹脂の溶
融物を著しく減少させてスルーホール信頼性を確保して
いる。さらに、ガラス転移温度が高いため、高温の熱衝
撃による多層回路板の厚さ方向の変形も少なくなり、内
層回路を構成する銅箔に薄いものを用いながらスルーホ
ール信頼性を確保することが可能になっている。
The copper foil constituting the circuit has a linear expansion coefficient of 17
Although it is as large as ppm / ° C., the content of the copper foil occupied particularly in the circuit of the inner layer is reduced, that is, the thickness of the copper foil is reduced to 20 μm or less. It has a big effect on making it smaller. If the thickness of the copper foil constituting the inner layer circuit is reduced, the connection area between the through-hole plating and the inner layer circuit is reduced,
There is a concern that the reliability of the through-hole may be reduced, but this problem is solved by setting the glass transition temperature of the resin to 140 ° C. or higher. When a drilling process for through-hole plating is performed, the drill blade and the inner wall of the multilayer circuit board are rubbed, and the inner wall of the hole becomes a temperature exceeding 130 ° C. The molten resin generated at that time adheres to the copper foil cross section of the inner layer circuit, and if through-hole plating is performed in such a state, the connection area between the through-hole plating and the inner layer circuit becomes smaller and the reliability of the through-hole decreases. You are worried. However, in the multilayer circuit board according to the present invention, since the resin has a glass transition temperature of 140 ° C. or higher when viewed as a multilayer circuit board, the resin melt generated at the time of drilling is significantly reduced to reduce the through-hole reliability. Is secured. Furthermore, since the glass transition temperature is high, the deformation of the multilayer circuit board in the thickness direction due to high-temperature thermal shock is reduced, and the through-hole reliability can be secured while using a thin copper foil for the inner layer circuit. It has become.

【0009】熱膨張係数を、目標とする10ppm/℃
以下にするためには、上記の要件に加えて、多層回路板
の絶縁層の樹脂含有量を45重量%以下にする必要があ
る。樹脂含有量を少なくすると耐湿マイグレーション性
の低下が心配となるが、この点については、エポキシ樹
脂の硬化をフェノール樹脂で行なわせることにより対応
している。マイグレーションは、直流電圧をかけると銅
がイオン化して多層回路板中へ溶解析出を繰り返し絶縁
劣化を起こす現象であるが、絶縁層の樹脂含有量や樹脂
中のイオン性不純物含有量の影響を受ける。特に、前記
のように絶縁層の樹脂含有量を制限したときには、イオ
ン性不純物含有量の影響が大きくなる。本発明は、樹脂
中のイオン性不純物含有量の目安となる硬化樹脂の抽出
水導電率はフェノール樹脂を硬化剤としたものが小さく
なるという新たな知見に基づくものである。しかし、絶
縁層の防湿作用を持つ樹脂の含有量を少なくすることは
おのずと限界があり、35重量%未満ではフェノール樹
脂を硬化剤としても耐湿マイグレーション性を維持する
ことができなくなる。絶縁層全体を平均した樹脂含有量
は35〜45重量%にする必要があるが、内層回路板を
構成する絶縁層の樹脂含有量より、内層回路板と表面の
回路を接着する絶縁層の樹脂含有量を多くすると、内層
回路表面の凹凸を樹脂で埋めやすくなり内層にボイドが
残留するのを回避することができる。
The thermal expansion coefficient is set at a target value of 10 ppm / ° C.
In order to make the content below, in addition to the above requirements, it is necessary to make the resin content of the insulating layer of the multilayer circuit board 45% by weight or less. If the resin content is reduced, there is a concern that the moisture migration resistance may be reduced, but this is addressed by curing the epoxy resin with a phenol resin. Migration is a phenomenon in which copper is ionized when a DC voltage is applied and dissolves and precipitates in a multilayer circuit board to cause insulation deterioration, but is affected by the resin content of the insulating layer and the ionic impurity content in the resin. . In particular, when the resin content of the insulating layer is limited as described above, the influence of the ionic impurity content becomes large. The present invention is based on a new finding that the extraction water conductivity of a cured resin, which is a measure of the content of ionic impurities in the resin, is smaller when a phenol resin is used as a curing agent. However, there is naturally a limit to reducing the content of the resin having a moisture-proof effect in the insulating layer. If the content is less than 35% by weight, the moisture migration resistance cannot be maintained even when a phenol resin is used as a curing agent. Although the average resin content of the entire insulating layer needs to be 35 to 45% by weight, the resin content of the insulating layer that bonds the inner layer circuit board and the surface circuit is determined by the resin content of the insulating layer forming the inner layer circuit board. When the content is increased, the irregularities on the surface of the inner layer circuit can be easily filled with the resin, and voids can be prevented from remaining in the inner layer.

【0010】上述のように、本発明に係る多層回路板
は、線膨張係数の大きくなる要因を取り除き、そのため
に生じることが危惧されるスルーホール信頼性低下の問
題も併せて解決するものであるが、上記の(1)〜
(4)の要件を全て満足して初めてなし得るものであ
る。
As described above, the multilayer circuit board according to the present invention eliminates the factor that increases the coefficient of linear expansion, and also solves the problem of reduced through-hole reliability that may be caused by the factor. , Above (1)-
This can be achieved only when all the requirements of (4) are satisfied.

【0011】[0011]

【実施例】本発明に係る多層回路板に使用するエポキシ
樹脂は、成形後の多層回路板としてみたときガラス転移
温度が140℃以上になるものであり、イオン性不純物
含有量の少ない樹脂が好ましい。通常のエピビス形エポ
キシ樹脂、多官能エポキシ樹脂などが好ましい。硬化剤
として使用するフェノール樹脂は、各種レゾール型フェ
ノール樹脂、ノボラック型フェノール樹脂であり、好ま
しくは、フェノールノボラック樹脂、ビスフェノールノ
ボラック樹脂などである。内層回路を構成する銅箔は、
20μm以下の厚さであれば電解箔、圧延箔など特に種
類を制限するものではない。以下、本発明に係る実施例
および参考例と従来例を詳細に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The epoxy resin used in the multilayer circuit board according to the present invention has a glass transition temperature of 140 ° C. or higher when viewed as a molded multilayer circuit board, and is preferably a resin having a low ionic impurity content. . Ordinary epibis epoxy resins, polyfunctional epoxy resins and the like are preferred. The phenolic resin used as the curing agent is various resol type phenolic resins and novolak type phenolic resins, preferably phenol novolak resins, bisphenol novolak resins and the like. The copper foil that constitutes the inner layer circuit is
As long as the thickness is 20 μm or less, there is no particular limitation on types such as an electrolytic foil and a rolled foil. Hereinafter, examples, reference examples, and conventional examples according to the present invention will be described in detail.

【0012】(実施例1)SiO2が54重量%、Al2
3が30重量%、MgOが13重量%、CaOが3重
量%の組成よりなるガラス繊維で構成された厚さ0.1m
mのガラス繊維織布aおよび厚さ0.18mmのガラス繊維
織布bを用意した。臭素化エピビス系エポキシ樹脂(東
都化成製 YDB−500EK80)200g、エピビ
ス系エポキシ樹脂(油化シェル製 Ep−1001EK
75)43g、クレゾールノボラック型エポキシ樹脂
(東都化成製 YDCN−704EK75)170g、
フェノールノボラック樹脂(大日本インキ製 TD−2
090EK60)130g、2−エチル4−メチルイミ
ダゾール(触媒)0.5gを均一に溶かしワニスAを調
製した。ワニスAをガラス繊維織布aに含浸、乾燥さ
せ、樹脂含有量が43重量%のプリプレグa(接着用)
を用意した。また、ワニスAをガラス繊維織布bに含
浸、乾燥させ、樹脂含有量が35重量%のプリプレグb
(内層回路板用)を用意した。次に、プリプレグbを2
枚重ねた両側に厚さ18μmの電解銅箔を重ね、熱媒油
プレスにて温度200℃、圧力40Kg/cm2で90分間
積層・成形し、厚さ0.4mmの銅張り積層板を得た。銅
張り積層板の銅箔を所定の工法でエッチング、黒化処理
して内層回路板とした後、その両表面にプリプレグaを
各2枚ずつ、更に厚さ18μmの電解銅箔を重ね、熱媒
油プレスにて温度200℃、圧力40Kg/cm2で60分
間積層・成形し、厚さ0.9mmの多層回路板とした。
(Example 1) 54% by weight of SiO 2 , Al 2
0.1 m thick made of glass fiber composed of 30% by weight of O 3 , 13% by weight of MgO, and 3% by weight of CaO.
A glass fiber woven fabric a having a thickness of 0.1 m and a glass fiber woven fabric b having a thickness of 0.18 mm were prepared. 200 g of brominated epibis epoxy resin (YDB-500EK80 manufactured by Toto Kasei) and epibis epoxy resin (Ep-1001EK manufactured by Yuka Shell)
75) 43 g, cresol novolak type epoxy resin (YDCN-704EK75 manufactured by Toto Kasei) 170 g,
Phenol novolak resin (TD-2 manufactured by Dainippon Ink and Chemicals, Inc.
090EK60) and 0.5 g of 2-ethyl 4-methylimidazole (catalyst) were uniformly dissolved to prepare Varnish A. Varnish A is impregnated into glass fiber woven fabric a and dried, and prepreg a having a resin content of 43% by weight (for bonding)
Was prepared. Further, the varnish A is impregnated into a glass fiber woven fabric b and dried, and a prepreg b having a resin content of 35% by weight is used.
(For inner layer circuit board) was prepared. Next, prepreg b is changed to 2
An electrolytic copper foil having a thickness of 18 μm is laminated on both sides of the laminated sheet, and laminated and molded by a heat medium oil press at a temperature of 200 ° C. and a pressure of 40 kg / cm 2 for 90 minutes to obtain a copper-clad laminate having a thickness of 0.4 mm. Was. After the copper foil of the copper-clad laminate is etched and blackened by a predetermined method to form an inner circuit board, two prepregs a and two 18 μm-thick electrolytic copper foils are further laminated on both surfaces of the copper foil. Laminating and forming were performed at a temperature of 200 ° C. and a pressure of 40 kg / cm 2 for 60 minutes by a medium oil press to obtain a multilayer circuit board having a thickness of 0.9 mm.

【0013】(実施例2)臭素化エピビス系エポキシ樹
脂(東都化成製 YDB−500EK80)200g、
エピビス系エポキシ樹脂(油化シェル製 Ep−100
1EK75)43g、クレゾールノボラッ型エポキシ樹
脂(東都化成製 YDCN−704EK75)170
g、ビスフェノールノボラック樹脂(油化シェル製 Y
LH−129EK60)100g、2−エチル4−メチ
ルイミダゾール(触媒)0.4gを均一に溶かしワニス
Bを調製した。ワニスBを用い、実施例1と同様の工程
で厚さ0.9mmの多層回路板とした。
Example 2 200 g of a brominated epibis epoxy resin (YDB-500EK80 manufactured by Toto Kasei)
Epibis epoxy resin (Ep-100 made by Yuka Shell)
1EK75) 43 g, cresol novola type epoxy resin (YDCN-704EK75 manufactured by Toto Kasei) 170
g, bisphenol novolak resin (Yukaka Shell Y
LH-129EK60) and 0.4 g of 2-ethyl 4-methylimidazole (catalyst) were uniformly dissolved to prepare Varnish B. Using varnish B, a multilayer circuit board having a thickness of 0.9 mm was obtained in the same process as in Example 1.

【0014】(実施例3)実施例1と同様の工程で、但
し、内層回路板の銅箔には厚さ9μmの電解銅箔を用い
て、厚さ0.9mmの多層回路板とした。
Example 3 A multilayer circuit board having a thickness of 0.9 mm was prepared in the same manner as in Example 1 except that an electrolytic copper foil having a thickness of 9 μm was used as the copper foil of the inner layer circuit board.

【0015】(参考例1)実施例1と同様の工程で、但
し、内層回路板用のプリプレグbの樹脂含有量を30重
量%に、また、接着用のプリプレグaの樹脂含有量を3
6重量%に設定して、厚さ0.9mmの多層回路板とし
た。
Reference Example 1 The same process as in Example 1 was carried out except that the resin content of the prepreg b for the inner layer circuit board was 30% by weight, and the resin content of the prepreg a for bonding was 3%.
A multilayer circuit board having a thickness of 0.9 mm was set at 6% by weight.

【0016】(参考例2)臭素化エピビス系エポキシ樹
脂(東都化成製 YDB−500EK80)200g、
エピビス系エポキシ樹脂(油化シェル製 Ep−100
1EK75)128g、クレゾールノボラック型エポキ
シ樹脂(東都化成製 YDCN−704EK75)85
g、メチルグリコール100gに溶かしたジシアンジア
ミド9g、2−エチル4−メチルイミダゾール(触媒)
0.6gを均一に溶かしワニスCを調製した。ワニスC
を用い、実施例1と同様の工程で厚さ0.9mmの多層回
路板とした。
Reference Example 2 200 g of a brominated epibis epoxy resin (YDB-500EK80 manufactured by Toto Kasei)
Epibis epoxy resin (Ep-100 made by Yuka Shell)
1EK75) 128 g, cresol novolak type epoxy resin (YDCN-704EK75 manufactured by Toto Kasei) 85
g, dicyandiamide 9g dissolved in methyl glycol 100g, 2-ethyl 4-methylimidazole (catalyst)
0.6 g was uniformly dissolved to prepare Varnish C. Varnish C
To obtain a multilayer circuit board having a thickness of 0.9 mm in the same process as in Example 1.

【0017】(参考例3)実施例1と同様の工程で、但
し、内層回路板用のプリプレグbの樹脂含有量を45重
量%に、また、接着用のプリプレグaの樹脂含有量を5
0重量%に設定して、厚さ0.9mmの多層回路板とし
た。
Reference Example 3 The same process as in Example 1 was carried out except that the resin content of the prepreg b for the inner layer circuit board was 45% by weight, and the resin content of the prepreg a for bonding was 5%.
A multilayer circuit board having a thickness of 0.9 mm was set at 0% by weight.

【0018】(参考例4)実施例1と同様の工程で、但
し、内層回路板用の銅箔は厚さ35μmの電解銅箔を用
いて、厚さ0.9mmの多層回路板とした。
REFERENCE EXAMPLE 4 A multilayer circuit board having a thickness of 0.9 mm was prepared in the same manner as in Example 1, except that an electrolytic copper foil having a thickness of 35 μm was used as the copper foil for the inner layer circuit board.

【0019】(参考例5)Eガラス組成の厚さ0.1mm
のガラス繊維織布cを用意した。これに、ワニスAを含
浸、乾燥させ、樹脂含有量が35重量%のプリプレグ
(内層回路板用)と樹脂含有量が43重量%のプリプレ
グ(接着用)を用意した。以下、実施例1と同様の工程
で、厚さ0.9mmの多層回路板とした。
Reference Example 5 E Glass Composition Thickness 0.1 mm
Was prepared. This was impregnated with varnish A and dried to prepare a prepreg having a resin content of 35% by weight (for an inner layer circuit board) and a prepreg having a resin content of 43% by weight (for bonding). Hereinafter, a multilayer circuit board having a thickness of 0.9 mm was obtained in the same steps as in Example 1.

【0020】(従来例1)Eガラス組成の厚さ0.1mm
のガラス繊維織布cを用意した。これに、ワニスCを含
浸、乾燥させ、樹脂含有量が45重量%のプリプレグ
(内層回路板用)と樹脂含有量が50重量%のプリプレ
グ(接着用)を用意した。以下、実施例1と同様の工程
で、但し、内層回路板用の銅箔は厚さ35μmの電解銅
箔を用いて、厚さ0.9mmの多層回路板とした。
(Conventional Example 1) E glass composition thickness 0.1 mm
Was prepared. This was impregnated with varnish C and dried to prepare a prepreg having a resin content of 45% by weight (for an inner circuit board) and a prepreg having a resin content of 50% by weight (for bonding). Hereinafter, the same steps as in Example 1 were performed, except that the copper foil for the inner layer circuit board was a multilayer circuit board having a thickness of 0.9 mm using an electrolytic copper foil having a thickness of 35 μm.

【0021】(実施例4)実施例1におけるプリプレグ
aの樹脂含有量を40重量%、プリプレグbの樹脂含有
量を30重量%として、以下、実施例1と同様の工程で
厚さ0.9mmの多層回路板とした。
(Example 4) The resin content of prepreg a in Example 1 was 40% by weight, and the resin content of prepreg b was 30% by weight. Of a multilayer circuit board.

【0022】(実施例5)実施例1におけるプリプレグ
aの樹脂含有量を50重量%、プリプレグbの樹脂含有
量を40重量%として、以下、実施例1と同様の工程で
厚さ0.9mmの多層回路板とした。
(Example 5) The resin content of prepreg a in Example 1 was set to 50% by weight and the resin content of prepreg b was set to 40% by weight. Of a multilayer circuit board.

【0023】(実施例6)実施例1におけるプリプレグ
aおよびbの樹脂含有量を同じ38重量%として、以
下、実施例1と同様の工程で厚さ0.9mmの多層回路板
とした。
(Example 6) With the same resin content of the prepregs a and b in Example 1 as 38% by weight, a multilayer circuit board having a thickness of 0.9 mm was obtained in the same process as in Example 1.

【0024】(実施例7)臭素化エピビス系エポキシ樹
脂(東都化成製 YDB−500EK80)200g、
エピビス系エポキシ樹脂(油化シェル製 Ep−100
1EK75)128g、クレゾールノボラッ型エポキシ
樹脂(東都化成製 YDCN−704EK75)85
g、ビスフェノールノボラック樹脂(油化シェル製 Y
LH−129EK60)80g、2−エチル4−メチル
イミダゾール(触媒)0.4gを均一に溶かしワニスD
を調製した。ワニスDを用い、以下、実施例1と同様の
工程で厚さ0.9mmの多層回路板とした。
Example 7 200 g of a brominated epibis epoxy resin (YDB-500EK80 manufactured by Toto Kasei)
Epibis epoxy resin (Ep-100 made by Yuka Shell)
1EK75) 128 g, cresol novola type epoxy resin (YDCN-704EK75 manufactured by Toto Kasei) 85
g, bisphenol novolak resin (Yukaka Shell Y
80 g of LH-129EK60) and 0.4 g of 2-ethyl 4-methylimidazole (catalyst) were uniformly dissolved to prepare Varnish D.
Was prepared. Using varnish D, a multilayer circuit board having a thickness of 0.9 mm was obtained in the same steps as in Example 1 below.

【0025】実施例1〜7、参考例1〜5、従来例1に
おける多層回路板の特性を表1および表2に示す。表
中、各特性は、以下のようにして評価した。 (1)Tg温度(ガラス転移温度):多層回路板の厚さ
方向の線膨張係数の変極点をTMA法で測定 (2)耐湿マイグレーション性:多層回路板の第2層目
に図1のパターンを形成し(スルーホール穴径0.3m
m,穴壁間隔0.3mm,スルーホールメッキ厚25μ
m)、85℃/85%RHの雰囲気で直流50Vの電圧
をかけ続けて絶縁抵抗が108Ω以下になるまでの時間
を測定 (3)線膨張係数:多層回路板たて方向の線膨張係数を
30〜80℃の範囲で測定 (4)スルーホール信頼性:連続500穴のスルーホー
ル(穴径1.0mm,スルーホールメッキ厚25μm)に
対して、260℃-5秒〜20℃-20秒の繰返し熱衝撃
を加え、導通しなくなるまでのサイクル (5)ドリル摩耗率:ドリル径1.0mmφのUC−35
(ユニオンツ−ル社製)を使用し、多層回路板3枚を重
ねて、5000ヒット穴明けをした後のドリル刃先の摩
耗率を測定 (6)抽出水導電率:多層回路板を200メッシュ程度
の大きさに粉砕したもの2gを、フッ素樹脂製の容器に
入れた純水20g中に沈め、当該容器を密封状態にして
121℃で168時間のプレッシャークッカー処理に供
し、その後の容器内の水の導電率を測定することにより
行なった。 (7)ボイド個数:銅張り積層板の銅箔を1cm角でエッ
チング除去した部分を125箇所設けたものを便宜上内
層回路板として用意し、多層回路板に成形した後樹脂で
完全に埋まらなかった箇所を計数
Tables 1 and 2 show the characteristics of the multilayer circuit boards in Examples 1 to 7, Reference Examples 1 to 5, and Conventional Example 1. In the table, each characteristic was evaluated as follows. (1) Tg temperature (glass transition temperature): The inflection point of the coefficient of linear expansion in the thickness direction of the multilayer circuit board is measured by the TMA method. (2) Moisture migration resistance: The pattern of FIG. (Through hole hole diameter 0.3m
m, hole wall spacing 0.3mm, through-hole plating thickness 25μ
m), measuring the time until the insulation resistance becomes 10 8 Ω or less while continuously applying a voltage of 50 V DC in an atmosphere of 85 ° C./85% RH. (3) Linear expansion coefficient: linear expansion in the vertical direction of the multilayer circuit board The coefficient is measured in the range of 30 to 80 ° C. (4) Through-hole reliability: 260 ° C for 5 seconds to 20 ° C for 500 continuous through-holes (hole diameter 1.0 mm, through-hole plating thickness 25 µm) Cycle until thermal conduction is repeated by applying thermal shock repeatedly for 20 seconds (5) Drill wear rate: UC-35 with a drill diameter of 1.0 mmφ
(Union Tool Co., Ltd.) was used to stack three multilayer circuit boards and measure the wear rate of the drill bit after drilling 5,000 hits. (6) Extracted water conductivity: about 200 mesh of multilayer circuit board 2 g of the pulverized water is submerged in 20 g of pure water in a container made of a fluororesin, and the container is sealed and subjected to a pressure cooker treatment at 121 ° C. for 168 hours. The measurement was performed by measuring the conductivity. (7) Number of voids: A copper-clad laminate having 125 copper-etched portions removed by 1 cm square was provided as an inner circuit board for convenience, and was not completely filled with resin after being formed into a multilayer circuit board. Count locations

【0026】[0026]

【表1】 [Table 1]

【0027】[0027]

【表2】 [Table 2]

【0028】[0028]

【発明の効果】表1から明らかなように、本発明に係る
多層回路板は、面方向の熱膨張量が小さく、かつ、耐湿
マイグレーション性が良好で、表面実装時の接続信頼性
に優れたものである。多層回路板の絶縁層全体としての
樹脂含有量を35〜45重量%の範囲にしつつ、内層回
路板の絶縁層の樹脂含有量より、内層回路と表面の回路
を接着する絶縁層(内層回路板同士を接着する場合はそ
の絶縁層も含む)の樹脂含有量を多くすれば、さらに、
内層のボイドが少なくなる点で優れている。
As is clear from Table 1, the multilayer circuit board according to the present invention has a small thermal expansion in the surface direction, good moisture migration resistance, and excellent connection reliability during surface mounting. Things. While the resin content of the entire insulating layer of the multilayer circuit board is in the range of 35 to 45% by weight, the insulating layer (the inner circuit board) for bonding the inner circuit and the surface circuit is determined based on the resin content of the insulating layer of the inner circuit board. If the resin content is increased, the insulating layer is also included when bonding them together.
It is excellent in that voids in the inner layer are reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】耐湿マイグレーション性の評価を実施する多層
回路板の内層回路パターンを示す説明図である。
FIG. 1 is an explanatory diagram showing an inner layer circuit pattern of a multilayer circuit board for evaluating the resistance to moisture migration.

フロントページの続き (56)参考文献 特開 平3−112650(JP,A) 特開 昭63−232490(JP,A) 特開 昭63−108797(JP,A) 特開 昭60−257591(JP,A) 特開 平4−329695(JP,A)Continuation of the front page (56) References JP-A-3-112650 (JP, A) JP-A-63-232490 (JP, A) JP-A-63-108797 (JP, A) JP-A-60-257591 (JP , A) JP-A-4-329695 (JP, A)

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】表面と内層に回路を有し回路層間の絶縁層
がガラス繊維織布基材エポキシ樹脂で構成されている多
層回路板において、 (1)ガラス繊維織布はそのガラス組成が、SiO2
50〜75重量%、Al23:15〜35重量%、アル
カリ土類金属酸化物:5〜15重量%、アルカリ金属酸
化物:3重量%未満であり、 (2)エポキシ樹脂は、フェノール樹脂を硬化剤とし多
層回路板としてのガラス転移温度が140℃以上であ
り、 (3)絶縁層全体を平均した樹脂含有量の平均は35〜
45重量%であり、 (4)内層回路を構成する銅箔の厚さは20μm以下で
あることを特徴とする多層回路板。
1. A multilayer circuit board having a circuit on a surface and an inner layer and an insulating layer between circuit layers made of a glass fiber woven fabric base epoxy resin, wherein: (1) the glass fiber woven fabric has a glass composition SiO 2 :
50-75 wt%, Al 2 O 3: 15 to 35 wt%, the alkaline earth metal oxide: 5 to 15 wt%, alkali metal oxides: less than 3 wt%, (2) an epoxy resin, phenol The glass transition temperature of the multilayer circuit board using the resin as a curing agent is 140 ° C. or higher. (3) The average resin content of the entire insulating layer is 35 to
(4) A multilayer circuit board, wherein the thickness of the copper foil constituting the inner layer circuit is 20 μm or less.
【請求項2】内層回路板を構成する絶縁層の樹脂含有量
より、内層回路板と表面の回路を接着する絶縁層の樹脂
含有量を多くした請求項1項記載の多層回路板。
2. The multi-layer circuit board according to claim 1, wherein the resin content of the insulating layer that bonds the inner circuit board to the surface circuit is larger than the resin content of the insulating layer forming the inner circuit board.
【請求項3】内層回路板を構成する絶縁層の樹脂含有量
より、内層回路板同士および内層回路板と表面の回路を
接着する絶縁層の樹脂含有量を多くした請求項1項記載
の多層回路板。
3. The multilayer according to claim 1, wherein the resin content of the insulating layer that bonds the inner circuit boards to each other and the circuit of the surface and the inner layer circuit board is larger than the resin content of the insulating layer constituting the inner circuit board. Circuit board.
JP05064551A 1993-03-24 1993-03-24 Multilayer circuit board Expired - Fee Related JP3088050B2 (en)

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JP3088050B2 true JP3088050B2 (en) 2000-09-18

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CN103963378B (en) * 2014-03-05 2016-06-29 金安国纪科技股份有限公司 A kind of high heat-conducting type metal-based copper-clad plate and preparation method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60257591A (en) * 1984-06-04 1985-12-19 松下電工株式会社 Method of producing multilayer printed circuit board
JPS6256141A (en) * 1985-09-05 1987-03-11 松下電工株式会社 Multilayer printed wiring board
JPS63108797A (en) * 1986-10-27 1988-05-13 ダイヤ電子株式会社 Manufacture of multilayer printed interconnection board with built-in printed resistor
JPS63232490A (en) * 1987-03-20 1988-09-28 松下電工株式会社 Multilayer printed interconnection board
JPH03112650A (en) * 1989-09-27 1991-05-14 Shin Kobe Electric Mach Co Ltd Thermosetting resin laminated board and glass woven fabric base material for laminated board
JPH04329695A (en) * 1991-05-01 1992-11-18 Hitachi Chem Co Ltd Manufacturing lamination plate with metal foil for multi-layer printed circuit board

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