JP3087233B2 - Measuring method of chip position shift - Google Patents

Measuring method of chip position shift

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Publication number
JP3087233B2
JP3087233B2 JP04085252A JP8525292A JP3087233B2 JP 3087233 B2 JP3087233 B2 JP 3087233B2 JP 04085252 A JP04085252 A JP 04085252A JP 8525292 A JP8525292 A JP 8525292A JP 3087233 B2 JP3087233 B2 JP 3087233B2
Authority
JP
Japan
Prior art keywords
chip
pattern
scale
position shift
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP04085252A
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Japanese (ja)
Other versions
JPH05288510A (en
Inventor
浩輔 桂
秀起 恒次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
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Priority to JP04085252A priority Critical patent/JP3087233B2/en
Publication of JPH05288510A publication Critical patent/JPH05288510A/en
Application granted granted Critical
Publication of JP3087233B2 publication Critical patent/JP3087233B2/en
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Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置等に用いら
れるICチップ等のフリップチップ接続に於ける高精度
なチップ位置ズレ測定方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly accurate method for measuring a chip displacement in flip-chip connection of an IC chip or the like used in a semiconductor device or the like.

【0002】[0002]

【従来の技術】フリップチップ接続法は、ICチップと
基板若しくはICチップ同士の相対峙位置決め接続に於
いて、高密度な電極接続若しくは微小な寸法の電極接続
に有効な実装方法である。
2. Description of the Related Art The flip-chip connection method is a mounting method effective for high-density electrode connection or electrode connection of minute dimensions in the opposing positioning connection between an IC chip and a substrate or between IC chips.

【0003】近年、このフリップチップ接続法は、接続
時の位置決め精度の向上により、昭和62年電子情報通
信学会半導体・材料部門全国大会講演論文集(分冊
2),338頁,S9−6に代表される様に、受光素子
や面発光レーザ等の光デバイスチップとレンズや光導波
路等の光部品を構成した基板との位置決め対向接続に用
いられるようになってきているが、当該フリップチップ
接続法に於いては、フリップチップ接続後の両者の位置
ズレが問題となる。
[0003] In recent years, this flip-chip connection method is represented in the 1987 National Institute of Electronics, Information and Communication Engineers Semiconductor and Materials Division National Convention Lecture Papers (Part 2), p. 338, S9-6 due to the improvement of positioning accuracy at the time of connection. It has been used for positioning and opposing connection between an optical device chip such as a light receiving element and a surface emitting laser and a substrate constituting an optical component such as a lens and an optical waveguide. In this case, a positional deviation between the two after flip-chip connection becomes a problem.

【0004】このためフリップチップ接続時の位置ズレ
を正確に検査する必要が生じる。この種、従来のフリッ
プチップ接続による位置ズレ測定方法としては、図4に
示す様なマーカによる測定が一般的であった。図中、1
は透明なガラス材からなる疑似基板、2,5はバンプ用
電極パタン、3はバンプ、4はチップ、6a,6bはマ
ーカである。
[0004] For this reason, it is necessary to accurately inspect the positional deviation at the time of flip chip connection. In this type, as a conventional method for measuring the positional deviation by flip-chip connection, measurement using a marker as shown in FIG. 4 has been common. In the figure, 1
Is a pseudo substrate made of a transparent glass material, 2 and 5 are bump electrode patterns, 3 is a bump, 4 is a chip, and 6a and 6b are markers.

【0005】当該従来の位置ズレ測定方法は、疑似基板
1と当該疑似基板1上にフリップチップ接続するチップ
4の対向面に、それぞれバンプ用電極パタン2,5を形
成すると同時に、当該電極パタン2,5と任意一定の位
置関係を有し、位置ズレがない状態で上方から観察する
と、完全に重合する様に前記疑似基板1側にマーカ6a
を、亦、前記チップ4側にマーカ6bをそれぞれ形成
し、バンプ3を用いてフリップチップ接続した後に、前
記マーカ6a,6bのズレLを透明な前記疑似基板1側
より、図示しない顕微鏡により拡大し、測長器等で読み
とる方法が一般的であった。この方法は、位置ズレLの
読み取りが、マーカ6a,6bの幅より大きな精度でよ
い場合には、有効な位置ズレ測定方法である。
[0005] In the conventional displacement measurement method, bump electrode patterns 2 and 5 are formed on the opposing surface of a pseudo substrate 1 and a chip 4 to be flip-chip connected on the pseudo substrate 1, respectively. , 5 have a certain positional relationship, and when viewed from above without any positional deviation, the marker 6a is placed on the pseudo substrate 1 side so as to completely overlap.
After forming the markers 6b on the chip 4 side and flip-chip connecting them using the bumps 3, the displacement L of the markers 6a and 6b is enlarged from the transparent pseudo substrate 1 side by a microscope (not shown). However, the method of reading with a length measuring device or the like was generally used. This method is an effective position deviation measurement method when the positional deviation L can be read with an accuracy larger than the width of the markers 6a and 6b.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、当該従
来の位置ズレ測定方法に於いては、位置ズレLが微小な
場合、特にマーカ6a,6b自身の読み取り誤差や、測
定に用いる測長器の精度等により測定誤差が大きくなる
可能性があった。
However, in the conventional position deviation measuring method, when the position deviation L is very small, particularly, the reading error of the markers 6a and 6b itself and the accuracy of the length measuring device used for the measurement. There was a possibility that the measurement error would increase due to the above factors.

【0007】即ち、マーカ6a,6bの幅以下の精度の
測長では、そのズレLを当該マーカ6a,6bのエッジ
部分や中央を正確に判別して測長せざるを得ず、読み取
り誤差が大きくなる問題があった。亦、顕微鏡等を用い
て光学的に対象物を透過・拡大し、画像情報として測長
を行う測長器を用いた場合には、顕微鏡の収差等によ
り、透過・拡大した像が歪み、正確な測長が困難であっ
た。
That is, in the length measurement with an accuracy equal to or less than the width of the markers 6a and 6b, the deviation L must be measured by accurately judging the edge portion and the center of the markers 6a and 6b, and the reading error is reduced. There was a growing problem. Also, when a length measuring device that optically transmits and enlarges an object using a microscope and measures the length as image information is used, the transmitted and enlarged image is distorted due to the aberration of the microscope, etc. Length measurement was difficult.

【0008】一方、微動台により対象物を移動させ、マ
ーカを読み取る測長器では、微動台のバックラッシュ等
により正確な測長が得難くなる可能性があった。亦、フ
リップチップ接続の際、位置決め接続する対象物同士が
捻れて接続された場合には、マーカ自身の配置も捻れて
測定誤差が大きくなる問題があった。ここに於いて、本
発明は前記従来の課題に鑑み、フリップチップ接続に於
けるICチップの微小な位置ズレを、正確に測定出来る
チップ位置ズレ測定方法を提供せんとするものである。
On the other hand, in a length measuring device that moves an object by using a fine moving table and reads a marker, it may be difficult to obtain an accurate length measurement due to backlash of the fine moving table. In addition, in flip-chip connection, if the objects to be positioned and connected are twisted and connected, there is a problem that the arrangement of the markers themselves is twisted and the measurement error increases. SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention is to provide a chip position shift measuring method capable of accurately measuring a minute position shift of an IC chip in flip chip connection.

【0009】[0009]

【課題を解決するための手段】前記課題の解決は、本発
明が次に列挙する新規な特徴的構成手法を採用すること
により達成される。即ち、本発明の第1の特徴は、IC
チップ若しくはそれに類する形状のチップが、バンプ用
電極パタンを介して基板と相対峙位置決め接続するフリ
ップチップ接続法に於ける位置決め接続後のチップ位置
ズレ測定方法に於いて、前記フリップチップ接続を行う
チップ或いはこれに対向する基板の何れか一方の表面上
に、バンプ用電極パタンと当該バンプ用電極パタンと任
意所定位置関係の中心点より十重二重に複数の同心相似
形線を放射方向等ピッチ間隔で配置する主尺目盛り位置
ズレ検出パタンをパタン形成すると共に、他方のチップ
或いは基板の何れかの表面上に、前記バンプ用電極パタ
ンと同一寸法でかつ同一位置に配置するバンプ用電極パ
タンと、当該バンプ用電極パタンと前記同様任意所定位
置関係の中心点より十重二重に複数の同心相似形線をこ
れと同一形状の前記対向する前記同心相似形線に比して
所定の値だけ僅かにずらした間隔で等ピッチ間隔で配置
する副尺目盛り位置ズレ検出パタンをパタン形成し、前
記バンプ用電極上に形成したバンプを介してフリップチ
ップ接続した後、前記チップ若しくは基板を光学的に透
過して、前記チップと基板表面にそれぞれパタン形成し
た前記主尺目盛り位置ズレ検出パタンと、副尺目盛り位
置ズレ検出パタンの重合状態から、前記基板に対するチ
ップの位置ズレを測定してなるチップ位置ズレ測定方法
である。
The above object can be attained by adopting the following novel characteristic construction method of the present invention. That is, the first feature of the present invention is that the IC
In the flip-chip connection method in which a chip or a chip having a similar shape is positioned and connected to a substrate via a bump electrode pattern in a flip-chip connection method, a chip for performing the flip-chip connection is described. Alternatively, on one of the surfaces of the substrate opposed thereto, a plurality of concentric similar-shaped lines are arranged at equal pitches in a doubly overlapping manner from the bump electrode pattern and the center point of any predetermined positional relationship with the bump electrode pattern. A pattern of a main scale position shift detection pattern arranged at intervals is formed, and a bump electrode pattern having the same dimensions and the same position as the bump electrode pattern is formed on the surface of either the other chip or the substrate. In the same manner as described above, a plurality of concentric similarity lines are formed in a doubly overlapping manner from the center point of the arbitrary predetermined positional relationship with the bump electrode pattern before the same shape. A pattern of a vernier scale position shift detection pattern arranged at equal pitch intervals at intervals slightly shifted by a predetermined value compared to the opposed concentric similar shape line is formed, and via a bump formed on the bump electrode. After flip-chip connection, the chip or the substrate is optically transmitted, and the main scale scale position shift detection pattern formed on the chip and the substrate surface respectively, and from the superimposed state of the sub scale scale position shift detection pattern And a chip position shift measuring method for measuring a chip position shift with respect to the substrate.

【0010】本発明の第2の特徴は、前記第1の特徴に
於ける主尺目盛り位置ズレ検出パタンと、副尺目盛り位
置ズレ検出パタンのそれぞれ同心相似形線は、無端連続
又は不連続パタンであるチップ位置ズレ測定方法であ
る。
A second feature of the present invention is that the concentric similarity lines of the main scale scale position shift detection pattern and the sub scale scale position shift detection pattern in the first feature are endless continuous or discontinuous patterns. This is a method for measuring a chip position shift.

【0011】本発明の第3の特徴は、前記第1又は第2
の特徴に於ける主尺目盛り位置ズレ検出パタンと、副尺
目盛り位置ズレ検出パタンの同心相似形線は、同心円パ
タンとドットパタンと一部が直線パタンと、これ等の複
数組合せパタンのいずれかであるチップ位置ズレ測定方
法である。
A third feature of the present invention is that the first or the second
Concentric similarity lines of the main scale scale position shift detection pattern and the vernier scale scale position shift detection pattern in the features of the above are either a concentric pattern, a dot pattern, a part of a straight line pattern, or any of a plurality of these combination patterns. This is a method for measuring a chip position shift.

【0012】[0012]

【作用】本発明は、前記の様な手段を講じたので、ノギ
スに使用される主尺目盛りと副尺目盛りとを同心相似形
線パタンとし、半導体製造技術によりバンプ電極から所
定の間隔を隔てて形成し、微小位置ズレを前記主尺目盛
りパタンと副尺目盛りパタンとの重合情報として読み取
るので、パタンのエッジや中央等を正確に読み取る必要
がなく、亦、顕微鏡等の収差や機械的なズレが測長に影
響することがなくなる。
According to the present invention, the above measures are taken, so that the main scale and the vernier scale used for the calipers are concentrically similar line patterns, and are separated by a predetermined distance from the bump electrode by a semiconductor manufacturing technique. It is read as a superposition information of the main scale scale pattern and the vernier scale scale pattern, so that it is not necessary to accurately read the edge or center of the pattern, and it is also possible to obtain aberrations and mechanical problems such as a microscope. The deviation does not affect the length measurement.

【0013】よって、チップがどの方向にずれたとして
も、精密な測長装置を用いずに、容易に正確なチップの
位置ズレ測定が実現出来る。更に、前記主尺目盛りパタ
ンと副尺目盛りパタンが相互に対応相似形線であるた
め、捻れ回転した対象物の位置ズレも容易に測定可能と
なる。
Therefore, even if the chip is displaced in any direction, accurate and accurate measurement of the positional deviation of the chip can be realized without using a precise length measuring device. Further, since the main scale scale pattern and the vernier scale scale pattern are similar to each other, the positional deviation of the twisted and rotated object can be easily measured.

【0014】[0014]

【実施例】【Example】

(第1実施例)本発明の第1実施例を図面につき詳説す
る。図1は本実施例のチップ位置ズレ測定方法に用いる
位置ズレ検出パタンの平面図であって、(a)は接続基
板上に、亦、(b)はチップ上に形成されるものであ
る。図中、1′は例えばセラミック配線板である接続基
板、2′,5′はそれぞれ下側と上側のバンプ用電極パ
タン、4′はチップ、αは接続基板1′上に形成された
位置ズレ検出パタン、βはチップ4′上に形成された位
置ズレ検出パタンである。
(First Embodiment) A first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view of a displacement detection pattern used in the chip displacement measurement method of the present embodiment, wherein (a) is formed on a connection substrate and (b) is formed on a chip. In the figure, reference numeral 1 'denotes a connection board which is, for example, a ceramic wiring board, 2' and 5 'denote lower and upper bump electrode patterns respectively, 4' denotes a chip, and α denotes a position shift formed on the connection board 1 '. The detection pattern β is a misregistration detection pattern formed on the chip 4 ′.

【0015】図1(a)に示す様、接続基板1′上に、
20μmφのバンプ用電極パタン2′を四隅に一個ずつ
形成し、当該下側バンプ用電極パタン2′同志を結ぶ斜
線の交点を中心点0として、当該中心点0からの円周ピ
ッチaを例えば10μmと等間隔になる様配置すると共
に、例えばパタン幅bを5μmに統一設定した複数の同
心円αa〜αhの円周が主尺目盛り位置ズレ検出パタン
αをフォトリソグラフィ技術等の半導体形成技術により
同時に形成する。
As shown in FIG. 1A, on a connection board 1 ',
A 20 μmφ bump electrode pattern 2 ′ is formed one at each of the four corners, and the intersection of the oblique lines connecting the lower bump electrode patterns 2 ′ is defined as the center point 0, and the circumferential pitch a from the center point 0 is, for example, 10 μm. And at the same time, a plurality of concentric circles αa to αh having a uniform pattern width b of 5 μm are formed at the same time by a semiconductor forming technique such as a photolithography technique. I do.

【0016】他方、ダイシングすると多くのチップに裁
断することの出来る半導体ウェハのチップ4′の対向面
に、前記接続基板1′上に形成する下側バンプ用電極パ
タン2′と同一配置及び同一寸法の下側バンプ用電極パ
タン5′を形成すると共に、各チップ4′毎に前記接続
基板1′同様、当該上側バンプ用電極パタン5′の対角
線の交点を中心点0として、当該中心点0からの円周ピ
ッチcを例えば9.9μmと等間隔になる様配置すると
共に、例えばパタン幅dを5μmに統一設定した複数の
同心円βa〜βhの円周が副尺目盛り位置ズレ検出パタ
ンβをフォトリソグラフィ技術等の半導体形成技術によ
り同時に形成する。
On the other hand, the same arrangement and the same dimensions as the lower bump electrode pattern 2 'formed on the connection substrate 1' are provided on the opposite surface of the semiconductor wafer chip 4 'which can be cut into many chips by dicing. The lower bump electrode pattern 5 ′ is formed, and the intersection of the diagonal line of the upper bump electrode pattern 5 ′ is set as the center point 0 similarly to the connection board 1 ′ for each chip 4 ′. Are arranged such that the circumferential pitch c is equal to, for example, 9.9 μm, and the circumference of a plurality of concentric circles βa to βh whose pattern width d is uniformly set to, for example, 5 μm is a photo of the sub-scale scale position shift detection pattern β. It is formed simultaneously by a semiconductor formation technique such as a lithography technique.

【0017】その後、ウェハ上の各チップ対応の上側バ
ンプ用電極パタン5′に、例えばAuSnやSnPbのバンプを
形成し、前記ウェハを裁断して単独のチップ4′とし、
両面位置合わせ装置等によりフェイスダウンで前記接続
基板1′と当該チップ4′対向面上に形成したバンプ用
電極パタン2′及び5′同士を精密に相対峙位置合わせ
し、前記チップ4′を前記接続基板1′上にボンディン
グしてフリップチップ接続を行う。
Thereafter, for example, AuSn or SnPb bumps are formed on the upper bump electrode pattern 5 'corresponding to each chip on the wafer, and the wafer is cut into single chips 4'.
The connection substrate 1 ′ and the electrode patterns 2 ′ and 5 ′ for bumps formed on the opposing surface of the chip 4 ′ are precisely face-to-face aligned by face-down using a double-sided alignment device or the like, and the chip 4 ′ is Flip chip connection is performed by bonding on the connection substrate 1 '.

【0018】次に、当該フリップチップ接続を終了した
試料を、前記接続基板1′及びチップ4′対向表面に形
成した2つの同心円状の位置ズレ検出パタンα,βの重
合を、赤外線顕微鏡により前記チップ4′を透過して拡
大観察し、主尺目盛り位置ズレ検出パタンαと、副尺目
盛り位置ズレ検出パタンβの重合位置を読み取り、その
目盛りからゼロ中心、即ち位置ズレがゼロの時に前記主
尺目盛りと副尺目盛りとが完全に重合する目盛りである
同心円の中心点0までの目盛りの本数からチップ4′の
接続基板1′に対する位置ズレを測定する。
Next, the sample after the flip-chip connection has been completed is subjected to polymerization of two concentric misalignment detection patterns α and β formed on the surface facing the connection substrate 1 ′ and chip 4 ′ by an infrared microscope. It is transmitted through the tip 4 ′ and observed through magnification, and the overlapping position of the main scale scale position shift detection pattern α and the sub scale scale position shift detection pattern β is read. From the scale, the zero center, that is, the position shift is zero, the main scale scale position shift is zero. The positional deviation of the chip 4 'with respect to the connection substrate 1' is measured from the number of scales up to the center point 0 of the concentric circle, which is a scale in which the scale scale and the vernier scale completely overlap.

【0019】本実施例のチップ位置ズレ測定方法によれ
ば、円周ピッチaが10μmの同心円αa〜αhの主尺
目盛り位置ズレ検出パタンαと、円周ピッチcが9.9
μmの同心円βa〜βhの副尺目盛り位置ズレ検出パタ
ンβにより、チップ4′がどの方向にずれても0.1μ
mと高い精度で位置ズレの検出が可能となり、位置ズレ
が目盛りパタン幅b,dの5μmよりも小さなズレであ
っても、精密な測長装置を用いることなく、顕微鏡でチ
ップ4′を透過して前記位置ズレ検出パタンα,βの重
合を観察するだけで、容易にチップ位置ズレを測定出来
る。亦、主尺・副尺目盛りを円状に形成しているので、
接続されたチップ4′と接続基板1′が相互に捻れた位
置関係であっても、支障なく同一の精度で測定可能であ
る。
According to the chip position displacement measuring method of this embodiment, the main scale scale position displacement detection pattern α of the concentric circles αa to αh having the circumferential pitch a of 10 μm and the circumferential pitch c of 9.9.
Due to the vernier scale position shift detection pattern β of the concentric circles βa to βh of μm, even if the tip 4 ′ is shifted in any
The position deviation can be detected with a high accuracy of m, and even if the position deviation is smaller than 5 μm of the scale pattern widths b and d, the chip 4 ′ can be transmitted through the microscope without using a precise length measuring device. Then, simply by observing the polymerization of the position shift detection patterns α and β, the chip position shift can be easily measured. Also, since the main scale and vernier scale are formed in a circle,
Even if the connected chip 4 'and the connection board 1' have a mutually twisted positional relationship, the measurement can be performed with the same accuracy without any trouble.

【0020】尚、本実施例では、主尺目盛り位置ズレ検
出パタンαの同心円αa〜αh円周パタンピッチaを1
0μm,副尺目盛り位置ズレ検出パタンβの同心円βa
〜βh円周パタンピッチcを9.9μmとしたが、本発
明のチップ位置ズレ測定方法により必要な測定精度Xを
得るためには、当該必要な測定精度Xより前記主尺目盛
り位置ズレ検出パタンαの同心円αa〜αh円周パタン
ピッチaをひいたピッチ(X−a)となる様、前記副尺
目盛り位置ズレ検出パタンβの同心円βa〜βh円周パ
タンピッチcを定め、ゼロ中心の目盛りから当該ピッチ
a及びc(=X−a)で等間隔に円状の目盛りを配置形
成すれば良い。亦、本実施例に於いては接続基板1′表
面に主尺目盛りを配置し、チップ4′表面に副尺目盛り
を配置したが、チップ4′側に主尺目盛りを、且つ接続
基板1′側に副尺目盛りを配置しても同様の効果を得ら
れることは言うまでもない。
In this embodiment, the circumferential pattern pitch a of the concentric circles αa to αh of the main scale scale position shift detection pattern α is set to 1
0 μm, concentric circle βa of vernier scale position shift detection pattern β
.Beta.h circumferential pattern pitch c was set to 9.9 .mu.m. However, in order to obtain the required measurement accuracy X by the chip position displacement measuring method of the present invention, the main scale scale position displacement detection pattern was obtained from the required measurement accuracy X. The concentric circles βa to βh of the vernier scale position shift detection pattern β are determined so as to have a pitch (X−a) obtained by subtracting the concentric circles αa to αh circumferential pattern pitch a of α, and the center of the scale is zero. Therefore, circular scales may be arranged and formed at equal intervals at the pitches a and c (= X−a). Further, in this embodiment, the main scale is arranged on the surface of the connection board 1 'and the vernier scale is arranged on the surface of the chip 4'. It goes without saying that a similar effect can be obtained even if a vernier scale is arranged on the side.

【0021】(第2実施例)本発明の第2実施例を図面
につき詳説する。図2(a),(b),(c),(d)
は、本実施例に用いる位置ズレ検出パタンのバリエーシ
ョンを示す平面図である。第1実施例に於いては、主尺
・副尺目盛りが同心円状のパタンである場合に付き説明
したが、本実施例の如く主尺・副尺目盛りパタンの一方
又はその両方が、同心円を裁断した不連続パタンであっ
てもかまわない。
(Second Embodiment) A second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 (a), (b), (c), (d)
FIG. 4 is a plan view showing a variation of a displacement detection pattern used in the present embodiment. In the first embodiment, the case where the main scale and the vernier scale scale are concentric patterns has been described. However, as in the present embodiment, one or both of the main scale and the vernier scale scale pattern form a concentric circle. It may be a cut discontinuous pattern.

【0022】ここで図2の位置ズレ検出パタンのバリエ
ーションを各々に付き説明する。図2(a)は、同心円
α,βの円周をそのままある間隔で裁断した位置ズレ検
出パタンγである。図2(b)は、図1に示した同心円
α,βの円周の位置に、丸型のドットパタンを配置した
位置ズレ検出パタンδである。
Here, each of the variations of the displacement detection pattern shown in FIG. 2 will be described. FIG. 2A shows a positional deviation detection pattern γ obtained by cutting the circumferences of the concentric circles α and β at an interval. FIG. 2B shows a positional deviation detection pattern δ in which a circular dot pattern is arranged at positions around the concentric circles α and β shown in FIG.

【0023】図2(c)は、図1に示した同心円α,β
の円周の位置に、角型ドットパタンを配置した位置ズレ
検出パタンεである。図2(d)は、図1に示した同心
円α,βの円周の位置に、三角型ドットパタンを配置し
た位置ズレ検出パタンωである。
FIG. 2C shows the concentric circles α and β shown in FIG.
Is a positional shift detection pattern ε in which a square dot pattern is arranged at a position on the circumference of. FIG. 2D shows a positional shift detection pattern ω in which triangular dot patterns are arranged at positions around the concentric circles α and β shown in FIG.

【0024】図2(a),(b),(c),(d)に示
す位置ズレ検出パタンγ,δ,ε,ωによれば、図1の
位置ズレ検出パタンα,βと比してパタン重合の視認性
が向上し、より正確な位置ズレ検出が可能となる。以上
のパタンは代表例であって、図2(b),(c),
(d)のドットパタンにはどの様な形状のものを用いて
も良いし、種類の異なるドットパタンを組み合わせても
良い。
According to the displacement detection patterns γ, δ, ε, and ω shown in FIGS. 2A, 2B, 2C, and 2D, compared with the displacement detection patterns α and β in FIG. As a result, the visibility of the pattern polymerization is improved, and more accurate positional deviation detection becomes possible. The above pattern is a typical example, and FIGS. 2 (b), (c),
Any shape may be used for the dot pattern (d), or different types of dot patterns may be combined.

【0025】更に、図1で示した同心円状パタン,図2
(a)の裁断同心円状パタン及び図2(b),(c),
(d)の各種ドットパタンをそれぞれ複合して用いても
良いことは自明である。以上、前記第1及び第2本実施
例では、目盛りのゼロ中心(即ち位置ズレがゼロの時に
主尺と副尺とが完全に重合する目盛り)が同心円の中心
となる例のみ述べたが、本発明のチップ位置ズレ測定方
法はどの同心円の円周をゼロ中心としても良い。
Further, the concentric pattern shown in FIG.
The cut concentric pattern of (a) and FIGS. 2 (b), (c),
It is obvious that the various dot patterns of (d) may be used in combination. As described above, in the first and second embodiments, only the example where the zero center of the scale (ie, the scale where the main scale and the vernier scale completely overlap when the positional deviation is zero) is the center of the concentric circle has been described. In the method of measuring a chip position deviation according to the present invention, the circumference of any concentric circle may be set as the zero center.

【0026】亦、第1実施例に於いて、パタンの線幅
b,dを5μm,バンプ用電極パタン2′,5′寸法を
50μmφ四個,配線基板1′材料をセラミック,バン
プ材質をAuSn若しくはSnPbとしたが、本発明はこの値や
材質に制限されるものではなく、更に位置ズレ検出パタ
ンα,βを四個の下側と上側のバンプ用電極パタン
2′,5′の対角線の交点に設定したが、当該バンプ用
電極パタン2′,5′に対して所定の間隔にあればどの
位置に配置形成しても良い。亦、前記第1実施例では、
位置ズレ検出パタンα,βとバンプ用電極パタン2′,
5′を同時に形成すると説明したが、所望の位置に正確
に位置ズレ検出パタンα,βを形成出来れば、同時に形
成する必要はない。
Also, in the first embodiment, the line widths b and d of the pattern are 5 μm, the dimensions of the bump electrode patterns 2 ′ and 5 ′ are four 50 μm φ, the wiring board 1 ′ is made of ceramic, and the bump material is made of AuSn. Or SnPb, but the present invention is not limited to this value or material, and furthermore, the displacement detection patterns α and β are defined by the four diagonal lines of the lower and upper bump electrode patterns 2 ′ and 5 ′. Although they are set at the intersections, they may be arranged and formed at any positions as long as they are at predetermined intervals with respect to the bump electrode patterns 2 'and 5'. Also, in the first embodiment,
The displacement detection patterns α and β and the bump electrode pattern 2 ′,
Although it has been described that 5 ′ is formed at the same time, it is not necessary to form them simultaneously if the displacement detection patterns α and β can be formed accurately at desired positions.

【0027】(第3実施例)本発明の第3実施例を図面
につき詳説する。図3(a),(b)はそれぞれ本実施
例のチップ位置ズレ測定方法に用いる主尺・副尺目盛り
位置ズレ検出パタンであって、(a)は図1に示す第1
実施例の同心円パタンと、その中心を通る5μmの直交
十字線を配した位置ズレ検出パタン、(b)は図1に示
す第1実施例の同心円パタンと、その外周に等間隔のド
ットパタンを同心円状に配置した位置ズレ検出パタンで
ある。図中、θ,λは位置ズレ検出パタンである。
(Third Embodiment) A third embodiment of the present invention will be described in detail with reference to the drawings. FIGS. 3A and 3B are main scale and vernier scale position shift detection patterns used in the tip position shift measuring method of the present embodiment, and FIG. 3A shows the first scale shown in FIG.
The concentric pattern of the embodiment and a misregistration detection pattern in which a 5 μm orthogonal cross line passing through the center is arranged. FIG. 2B shows the concentric pattern of the first embodiment shown in FIG. These are misalignment detection patterns arranged concentrically. In the figure, θ and λ are positional shift detection patterns.

【0028】本実施例の位置ズレ検出パタンθ,λは、
基板1′とチップ4′対向表面に形成した後、前記第1
実施例同様にフリップチップ接続し、赤外線顕微鏡で観
察することにより、位置ズレだけでなく、捻れ角度も各
々同時に測定出来る。本実施例では、直交十字線θaと
ドットパタンλaをそれぞれ別々のパタンとしたが、複
合したパタンを同心円パタンと共に形成しても良い。
The displacement detection patterns θ and λ of the present embodiment are
After being formed on the surface facing the substrate 1 'and the chip 4', the first
As in the embodiment, by flip-chip connection and observation with an infrared microscope, not only positional deviation but also twist angle can be measured simultaneously. In the present embodiment, the orthogonal cross line θa and the dot pattern λa are respectively different patterns, but a composite pattern may be formed together with a concentric pattern.

【0029】亦、本実施例の直交十字線θa付き同心円
パタンとドットパタンλa付き同心円パタンは、一方を
チップに、他方を基板にと分けて形成しても良い。尚、
これ等実施例では、赤外線顕微鏡により試料を透過・拡
大して測長する例に付いて述べたが、基板若しくはチッ
プを透過・拡大出来るものであればどの様な顕微鏡でも
よく、例えばX線顕微鏡等であってもよいし、さらに基
板若しくはチップを透明な材料で形成して、透明な方か
ら通常の顕微鏡等で測長しても良い。
Further, the concentric pattern with the orthogonal cross line θa and the concentric pattern with the dot pattern λa of the present embodiment may be formed such that one is a chip and the other is a substrate. still,
In these embodiments, an example in which a sample is transmitted and enlarged by an infrared microscope to measure a length is described. However, any microscope that can transmit and enlarge a substrate or a chip may be used. For example, an X-ray microscope Alternatively, the substrate or the chip may be formed of a transparent material, and the length may be measured with a normal microscope or the like from the transparent side.

【0030】さらに、これ等実施例では同心円パタンを
基板とチップに描いたが同心円に限らず同一形状の同心
相似形線パタンを用いても同様である。亦、これ等実施
例では基板とチップとのフリップチップ接続した試料に
付いて述べたが、同一形状の相似形線パタンを有すれ
ば、チップとチップ同士のフリップチップ接続した試料
についしても位置ズレ測定にしよう出来ることは言うま
でもない。
Further, in these embodiments, the concentric patterns are drawn on the substrate and the chip. However, the present invention is not limited to the concentric circles, and the same applies to the use of concentric and similar line patterns having the same shape. In addition, in these embodiments, a sample in which a substrate and a chip are flip-chip connected is described. However, if a sample has a similar shape line pattern of the same shape, a sample in which a chip and a chip are flip-chip connected may be used. It goes without saying that the displacement can be measured.

【0031】[0031]

【発明の効果】かくして本発明によれば、ノギスに使用
される主尺目盛りと副尺目盛りとを同一形状の同心相似
形線パタンとし、半導体製造技術によりバンプ用電極パ
タンから任意所定の間隔を隔てて形成し、位置ズレを主
尺と副尺の重合パタンとして読み取ることを可能とした
ため、マーカの細かい読み取り誤差や測長器の精度に影
響されることなく、チップがどの方向にずれても、容易
にしかも正確にチップの位置ズレを測定することが出
来、更に主尺と副尺目盛りを特に同心円状とすると、捻
れ回転した対象物の位置ズレに対しても同一の精度で測
定可能な効果を有する等、優れた実用性,有用性を具有
する。
As described above, according to the present invention, the main scale and the vernier scale used for the calipers are concentric and similar line patterns of the same shape, and an arbitrary predetermined distance from the bump electrode pattern is obtained by the semiconductor manufacturing technology. Since it is formed at a distance, it is possible to read misalignment as a superimposed pattern of the main scale and the vernier scale, so it is not affected by the fine reading error of the marker or the accuracy of the length measuring instrument, and even if the chip is shifted in any direction It is possible to easily and accurately measure the displacement of the tip, and if the main scale and the vernier scale are particularly concentric, the same displacement can be measured with the same accuracy even when the position of the twisted and rotated object is changed. It has excellent practicality and usefulness such as having an effect.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例のチップ位置ズレ測定方法
に用いる位置ズレ検出パタンの平面図であって、(a)
は接続基板上に、亦、(b)はチップ上に形成されるも
のである。
FIG. 1 is a plan view of a displacement detection pattern used in a chip displacement measurement method according to a first embodiment of the present invention, and FIG.
Is formed on a connection substrate, and (b) is formed on a chip.

【図2】(a),(b),(c),(d)はそれぞれ本
発明の第2実施例チップ位置ズレ測定法に用いる位置ズ
レ検出パタンのバリエーションを示す平面図である。
FIGS. 2 (a), (b), (c) and (d) are plan views showing variations of a displacement detection pattern used in a chip displacement measurement method according to a second embodiment of the present invention.

【図3】(a),(b)はそれぞれ本発明の第3実施例
のチップ位置ズレ測定方法に用いる主尺・副尺目盛り位
置ズレ検出パタンである。
FIGS. 3 (a) and 3 (b) are main scale and vernier scale position shift detection patterns used in a tip position shift measuring method according to a third embodiment of the present invention.

【図4】従来のフリップチップ接続の位置ズレ測定方法
を示す説明側面図である。
FIG. 4 is an explanatory side view showing a conventional method for measuring a positional shift in flip chip connection.

【符号の説明】[Explanation of symbols]

1…疑似基板 1′…接続基板 2,5,2′,5′…バンプ用電極パタン 3…バンプ 4,4′…チップ 6a,6b…マーカ 0…中心点 α…接続基板上に形成された位置ズレ検出パタン αa〜αh,βa〜βh…同心円 β…チップ上に形成された位置ズレ検出パタン γ,δ,ε,ω,θ,λ…位置ズレ検出パタン DESCRIPTION OF SYMBOLS 1 ... Pseudo board 1 '... Connection board 2,5,2', 5 '... Bump electrode pattern 3 ... Bump 4,4' ... Chip 6a, 6b ... Marker 0 ... Center point α ... Formed on connection board Position shift detection patterns αa to αh, βa to βh: concentric circles β: position shift detection patterns formed on the chip γ, δ, ε, ω, θ, λ: position shift detection patterns

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平3−19312(JP,A) 特開 昭48−93270(JP,A) 特開 昭62−19856(JP,A) 特開 平3−268415(JP,A) (58)調査した分野(Int.Cl.7,DB名) G01B 11/00 - 11/30 102 H05K 3/32 - 3/34 H05K 13/00 - 13/04 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-19312 (JP, A) JP-A-48-93270 (JP, A) JP-A-62-19856 (JP, A) 268415 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) G01B 11/00-11/30 102 H05K 3/32-3/34 H05K 13/00-13/04

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】ICチップ若しくはそれに類する形状のチ
ップが、バンプ用電極パタンを介して基板と相対峙位置
決め接続するフリップチップ接続法に於ける位置決め接
続後のチップ位置ズレ測定方法に於いて、前記フリップ
チップ接続を行うチップ或いはこれに対向する基板の何
れか一方の表面上に、バンプ用電極パタンと当該バンプ
用電極パタンと任意所定位置関係の中心点より十重二重
に複数の同心相似形線を放射方向等ピッチ間隔で配置す
る主尺目盛り位置ズレ検出パタンをパタン形成すると共
に、他方のチップ或いは基板の何れかの表面上に、前記
バンプ用電極パタンと同一寸法でかつ同一位置に配置す
るバンプ用電極パタンと、当該バンプ用電極パタンと前
記同様任意所定位置関係の中心点より十重二重に複数の
同心相似形線をこれと同一形状の前記対向する前記同心
相似形線に比して所定の値だけ僅かにずらした間隔で等
ピッチ間隔で配置する副尺目盛り位置ズレ検出パタンを
パタン形成し、前記バンプ用電極上に形成したバンプを
介してフリップチップ接続した後、前記チップ若しくは
基板を光学的に透過して、前記チップと基板対向面にそ
れぞれパタン形成した前記主尺目盛り位置ズレ検出パタ
ンと、副尺目盛り位置ズレ検出パタンの重合状態から、
前記基板に対するチップの位置ズレを測定することを特
徴とするチップ位置ズレ測定方法
In a flip chip connection method in which an IC chip or a chip having a similar shape is positioned and connected to a substrate via an electrode pattern for bumps, a method for measuring a chip position shift after a positioning connection is used. A bump electrode pattern and a plurality of concentric similar shapes are formed on the surface of either one of the chip to be flip-chip connected or the substrate facing the same in a doubly double manner from a center point of an arbitrary predetermined positional relationship with the bump electrode pattern. A main scale scale position shift detection pattern for arranging the lines at equal pitches in the radial direction is formed in a pattern, and the same size and the same position as the bump electrode pattern are arranged on one surface of the other chip or the substrate. And a plurality of concentrically similar lines in a doubly overlapping manner from the center point of the predetermined predetermined positional relationship with the bump electrode pattern to be formed. A pattern of a vernier scale position shift detection pattern arranged at equal pitch intervals at intervals slightly shifted by a predetermined value compared to the opposed concentric similar shape line having the same shape as the above is formed on the bump electrode. After flip-chip connection via the formed bump, the chip or substrate is optically transmitted, and the main scale scale position shift detection pattern formed on the chip and the substrate facing surface respectively, and the sub scale scale position shift. From the polymerization state of the detection pattern,
A method for measuring a positional shift of a chip with respect to the substrate, comprising:
【請求項2】主尺目盛り位置ズレ検出パタンと、副尺目
盛り位置ズレ検出パタンのそれぞれ同心相似形線は、無
端連続又は不連続パタンであることを特徴とする請求項
1記載のチップ位置ズレ測定方法
2. The chip position shift according to claim 1, wherein the concentric similar lines of the main scale scale position shift detection pattern and the sub scale scale position shift detection pattern are endless continuous or discontinuous patterns. Measuring method
【請求項3】主尺目盛り位置ズレ検出パタンと、副尺目
盛り位置ズレ検出パタンの同心相似形線は、同心円パタ
ンとドットパタンと一部が直線パタンと、これ等の複数
組合せパタンのいずれかであることを特徴とする請求項
1又は2記載のチップ位置ズレ測定方法
3. The concentric similar lines of the main scale scale position shift detection pattern and the sub scale scale position shift detection pattern may be any one of a concentric pattern, a dot pattern, a partially linear pattern, and a combination of a plurality of these patterns. 3. The method according to claim 1, wherein:
JP04085252A 1992-04-07 1992-04-07 Measuring method of chip position shift Expired - Fee Related JP3087233B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04085252A JP3087233B2 (en) 1992-04-07 1992-04-07 Measuring method of chip position shift

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04085252A JP3087233B2 (en) 1992-04-07 1992-04-07 Measuring method of chip position shift

Publications (2)

Publication Number Publication Date
JPH05288510A JPH05288510A (en) 1993-11-02
JP3087233B2 true JP3087233B2 (en) 2000-09-11

Family

ID=13853385

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Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3087233B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5343219B2 (en) * 2008-03-27 2013-11-13 福岡県 Strain measurement method, strain measurement system

Also Published As

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JPH05288510A (en) 1993-11-02

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