JP3084785B2 - Timing signal generation circuit and motor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit for accurately timing an index signal of a floppy disk drive or the like or a PG signal of a video tape recorder or the like.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing an example of a conventional index signal synchronization circuit. A conventional index signal synchronizing circuit 21 includes a comparator 21b for comparing an index signal Vh detected by a Hall element 21a with a reference voltage Vt, and a flip-flop 2 for synchronizing an output signal Vp of the comparator 21b with a reference timing signal Vc.
1c. Further, the configuration is such that the index voltage Vh and the reference voltage Vt are divided by resistors R1, R2 and R3, R4, respectively, and input to the comparator 21b. Also, a so-called FG (Frequency Generator) provided on the outer periphery of the rotor of the motor.
or) An index magnetic pole is provided in a part of the magnet, and this index magnetic pole is detected by the Hall element 21a provided near the index magnetic pole on the stator to obtain the index signal Vh. Generally, an FG signal obtained by the rotation of the rotor is used as a reference timing signal, and every time the rotor makes one rotation, the FG signal is increased.
The configuration was such that a signal of 0 pulse was generated.

FIG. 6 is a timing chart showing the operation of the synchronizing circuit 21. FIG. 6A shows the index signal Vh. The index signal Vh is compared with the reference voltage Vt by the comparator 21b. The signal is output as a pulse signal Vp shown in B). However, in this state, the signal Vp causes a timing error exceeding an allowable limit due to a variation or variation in the sensitivity of the index signal Vh and a mounting error of the Hall element 21a. Synchronization is performed with the FG signal Vc, which is extremely small. FIG. 7C shows the waveform of the FG signal Vc. The signal Vp is input to one input terminal of the flip-flop 21c and the signal Vc is input to the other input terminal, thereby generating the signal Vp. As long as the fall E11 is between the rises E12 and E13 of the signal Vc, the fall E14 of the output signal Vd of the flip-flop 21c becomes the timing of E13 of the signal Vc as shown in FIG. The timing error of the signal Vp is substantially the same as the error of the FG signal Vc.

[0004]

However, if the timing error or fluctuation of the index signal Vh increases, the generation of the index signal is delayed, and the index signal Vh 'becomes as shown in FIG. Therefore, the fall of the signal Vp also exceeds the interval between E12 and E13 shown in FIG. 9C and shifts between E13 and E15, and the fall becomes E16 as the signal Vp ′ shown in FIG. , Same figure (G)
As shown in the figure, the falling index E17 of the output index signal Vd 'has a timing E15 which is further delayed than the timing E14. If the fall of the output index signal Vd is delayed until the timing of E17, for example, a disk-shaped storage device such as a floppy disk drive tends to hinder data writing and reading, and a screen disturbance occurs in a drum motor of a video tape recorder. Tends to occur. This occurs because the period of the reference timing signal Vc is short and the allowable width (ie, the interval between the falling edges of Vc) is narrow with respect to the timing error and the magnitude of the fluctuation of the index signal Vh. . On the other hand, when the reference timing signal has a long cycle, for example, when synchronization is made with a rotor position detection signal of a motor or the like, the permissible width is widened, but the timing fluctuation of the reference timing signal itself becomes larger than that of the FG signal, and the output index The timing of the signals makes it difficult to obtain the required accuracy.

[0005]

Means for Solving the Problems] timing signal generating circuit according to the present invention in order to solve the above problems, the motor B
Period of the index signal generated per one rotation of the over motor
Cycle is shorter than that, and multiple rotors are generated per rotation of the rotor
Period than the period of the first pulse signal in synchronism with the long second pulse <br/> signals to, first obtained by detecting the index signal 1
A first detection means for outputting a detection signal, and a second detection signal obtained by detecting the first detection signal in synchronization with the first pulse signal.
And a second detecting means for outputting. Ma
Further, another timing signal generating circuit according to the present invention comprises an index signal generated once per rotation of a motor rotor.
Cycle is shorter than the cycle of
In synchronism with the first pulse signal generated, the period is shorter than the period of the index signal and is shorter than the period of the first pulse signal.
First detecting means for outputting a first detection <br/> signal obtained by detecting the long second pulse signal having remote period, in synchronization with the first detection signal, first obtained by detecting the index signal 2 Output detection signal
And a second detecting means for applying force . Departure
The motor according to the present invention includes the above-described timing signal generation circuit.
A motor comprising: an index signal;
Detection to detect the rotation of the rotor to obtain a pulse signal
Means are provided .

[0006]

In the first means, the index signal is first converted to the first signal.
The synchronization means synchronizes with the first reference signal having a long cycle, and then the output signal of the first synchronization means is synchronized with the second reference signal having a short cycle by the second synchronization means. In the second means, first the third
The first reference signal is synchronized with the second reference signal by synchronization means, and the index signal is then synchronized by the fourth synchronization means with the third reference signal.
Synchronize with the output signal of the synchronization means.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a configuration diagram of a first embodiment of an index signal synchronization circuit according to the present invention, FIG. 2 is a timing chart showing the operation of the first embodiment, FIG. 3 is a configuration diagram of the second embodiment, FIG. Is a timing chart showing the operation of the second embodiment. Note that the same parts as those in the conventional example are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, a rotor position signal for detecting a rotor position is used as an example of a reference signal having a relatively long cycle, and an FG signal is used as an example of a signal having a relatively short cycle. Other signals may be used as long as they are generated. First, a first embodiment according to claim 1 will be described. In FIG. 1, a synchronization circuit 1 for an index signal
Is an index signal generation circuit 2 composed of a Hall element 21a, voltage dividing resistors R1 to R4, and a comparator 2a, and an output signal V of the index signal generation circuit 2
A first synchronization circuit 3 composed of a flip-flop 3a for synchronizing p with the rotor position signal Vr, and a second synchronization circuit composed of a flip-flop 4a for synchronizing the output signal Vu of the first synchronization circuit 3 with the FG signal Vc. And a circuit 4.

In FIG. 2, (A) shows the Hall element 2
1a shows a waveform of an index signal Vh which is an output signal of the comparator 2a.
Compared with t, a signal Vp is obtained as an output signal as shown in FIG. The output signal Vp is further input to the flip-flop 3a, synchronized with the rotor position signal Vr shown in FIG. 3C, and an output signal Vu shown in FIG. That is, the signal V in FIG.
The signal Vu is generated at a point E2 where p falls to a low level at E1 and the signal Vr rises in FIG. Next, this signal Vu is input to the flip-flop 4a and is again synchronized with the signal Vc having a relatively shorter cycle than the signal Vr shown in FIG. That is, as in the case of the flip-flop 3a, the signal Vu in FIG. 4D falls at E3 and goes to a low level, and the signal Vc in FIG. The signal Vw is generated as shown in FIG.

Even if the timing of the fall E1 of the signal Vp is delayed, the signal Vu is not delayed unless the E1 is delayed from the timing of the rise E2 of the signal Vr.
Of the falling edge E3 does not change.
That is, since the cycle of the signal Vr is made longer than the cycle of the Vc, the allowable range of the rising timing error of the signal Vp can be increased as compared with the case where the signal Vp is synchronized with the signal Vc. The operation of inputting the signal Vu to the flip-flop 4a and synchronizing with the signal Vc is the same as in the conventional example. Therefore, the allowable range of the timing error can be increased as compared with the case where synchronization is achieved only with the Vc.

Next, a second embodiment according to claim 2 will be described. In FIG. 3, an index signal synchronization circuit 1
Reference numeral 1 denotes an index signal generating circuit 1 including a not-shown Hall element, a voltage dividing resistor, and a comparator 12a.
2 and a third synchronizing circuit 13 composed of a flip-flop 13a for synchronizing the rotor position signal Vr with the FG signal Vc.
And a fourth synchronization circuit 14 including a flip-flop 14a for synchronizing the output signal Vx of the flip-flop 13a with the signal Vp.

In FIG. 4, (A) and (B) are the same as those in FIG. In the second embodiment, first, the signal Vr is synchronized with the signal Vc. That is, the signal Vr shown in FIG. 9C is input to the flip-flop 13a, synchronized with the signal Vc shown in FIG. 9D, and an output signal Vx shown in FIG. That is, the cycle of the output signal Vx is relatively longer than that of the signal Vc. The signal Vp is input to the flip-flop 14a to generate an output signal Vy in synchronism with the signal Vx shown in FIG. 9F, thereby increasing the allowable error of the rising timing error of the signal Vp. be able to.

[0013]

According to the present invention, the index signal is synchronized by using the first reference signal and the second reference signal having a relatively shorter cycle than the first reference signal. Can be bigger.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of an index signal synchronization circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment.

FIG. 3 is a configuration diagram of the second embodiment.

FIG. 4 is a timing chart showing the operation of the second embodiment.

FIG. 5 is a circuit diagram of an example of a conventional index signal synchronization circuit.

FIG. 6 is a timing chart showing the operation of the synchronous circuit.

[Explanation of symbols]

1,11 ... index signal synchronization circuit, 2,12 ... index signal generation circuit, 2a, 12a ... comparator, 3 ... first synchronization circuit, 3a, 4a, 13a, 14a ...
Flip-flop, 4 ... second synchronous circuit, 13 ... third synchronous circuit, 14 ... fourth synchronous circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02P 6/06

Claims (4)

(57) [Claims] A period that is shorter than a period of an index signal generated once per rotation of a rotor of a motor;
Circumference of the first pulse signal to a plurality generated per rotation of the rotor
Period than the period in synchronization with the long second pulse signal, a first detection means for outputting a first detection signal obtained by detecting the index signal, in synchronization with the first pulse signal, said first It detects the detection signal
A second detection means for outputting a second detection signal obtained from the timing signal generation circuit. 2. The timing signal generating circuit according to claim 1,
And a motor for obtaining the index signal and the first pulse signal.
To detect the rotation of the rotor.
Features motor . 3. A cycle shorter than a cycle of an index signal generated once per rotation of a rotor of a motor , and
The period is shorter than the period of the index signal in synchronization with a plurality of first pulse signals generated per rotation of the rotor.
And longer second path periodicity than the period of the first pulse signal
First detection for outputting a first detection signal obtained by detecting the pulse signal
Output means, and the index signal is synchronized with the first detection signal.
Timing signal generating circuit, characterized in that a second detection means for outputting a second detection signal obtained by detecting. 4. The timing signal generating circuit according to claim 3,
And a motor for obtaining the index signal and the first pulse signal.
To detect the rotation of the rotor.
Features motor .