JP3080769B2 - VLIW type computer abnormality detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormality detection system for a VLIW computer which executes a VLIW instruction.

[0002]

2. Description of the Related Art There is a VLIW type computer which processes a plurality of instruction words in parallel. The VLIW computer operates according to an instruction called a VLIW instruction having a plurality of instruction fields in which independent instruction words can be set.
Instruction words set in each instruction field are processed in parallel.

By the way, in order to detect an abnormality of a computer such as the VLIW type computer described above, conventionally, the same calculation is executed a plurality of times in a target computer, and the calculation results are compared. A method has been known in which an operation is performed and the operation result is compared with a predicted value.

[0004] This abnormality detection method has a drawback that it performs a test operation, that is, a redundant operation, which is different from a normal operation in a computer, and thus affects the performance of the computer. That is, if a test operation is inserted into a calculation that one really wants to perform in order to detect a computer abnormality, there is a problem that the operation that one really wants to perform becomes slow because of the test operation.

[0005]

As described above, conventionally, a test operation, that is, a redundant operation is inserted in order to detect an abnormality in a computer, so that the performance of the computer is reduced.

However, in a VLIW type computer, a VLIW type computer in which instruction words are arranged by a compiler or a linker is used.
Generally, empty instruction fields are scattered in the type instruction group (assembly list or execution load module). Such an empty instruction field occurs when an instruction cannot be executed in parallel due to mutual dependency or the like.

The present invention focuses on the fact that there is an empty instruction field in which instruction words can be arranged in a VLIW instruction group in which instruction words have been arranged by a compiler or a linker. An object of the present invention is to provide a VLIW-type computer abnormality detection method capable of detecting a computer abnormality without deteriorating computer performance by embedding a test operation instruction word group necessary for computer operation abnormality detection.

[0008]

According to the present invention, there is provided a VLIW instruction group including at least M VLIW instructions having at least one empty instruction field from a VLIW instruction group in which instruction words are arranged by a compiler or a linker. Detecting means for detecting at least one type of instruction sequence, and in the detected VLIW type instruction sequence, any N (where N ≦ M) test operation instruction words required for detecting a computer operation abnormality are provided in an empty instruction field. Whether it is possible to embed using
Discriminating means for discriminating each LIW-type instruction sequence, and for a VLIW-type instruction sequence for which it has been determined that the test operation instruction word can be embedded, the empty instruction field included in the VLIW-type instruction sequence is determined. N Vs with
Test operation embedding means for embedding N test operation instructions using the empty instruction field in the LIW type instruction, wherein the VLI in which the test operation instruction is embedded is provided.
A computer abnormality is detected by executing a W-type instruction group.

[0009]

In the above configuration, the VLIW-type instruction string including M VLIW-type instructions having an empty instruction field is detected by the detection means from the VLIW-type instruction group in which instruction words are arranged by the compiler or the linker. At least one is detected. The determining means determines the detected VLI.
For each VLIW-type instruction sequence, it is determined whether or not N (N ≦ M) test operation instruction words necessary for detecting a computer operation abnormality can be embedded in a W-type instruction sequence using an empty instruction field. Is determined. This embedding-possible determination condition is that, for example, a register (destination-designated register) that is overwritten by (any instruction word of) the next VLIW-type instruction in the detected VLIW-type instruction string, and that register Is not referenced in the detected VLIW type instruction sequence.

[0010] For the VLIW type instruction sequence for which embedding is determined by the determining means, N test operation instruction words for overwriting the register used for the embedding determination with the test operation result are embedded. Embedded by means. This embedding is performed by using one vacant instruction field in one VLIW-type instruction among the N VLIW-type instructions having an empty instruction field in the same VLIW-type instruction sequence.
The test is performed in units of one test operation instruction word per W-type instruction.

By repeating the above operation, various N test operation instruction words can be embedded anywhere in the VLIW instruction group using the empty instruction field of the instruction group. Therefore, by executing the VLIW type instruction group in which the test operation instruction word is embedded, the test operation instruction word is processed in parallel with the original instruction processing, so that the performance of the computer is not reduced. , It is possible to detect a computer abnormality. Moreover, the register used for overwriting the test operation result is not referred to by the original instruction processing during the test operation processing, but is overwritten by the original instruction processing after the test operation processing. Therefore, the processing of the test operation instruction word embedded in the VLIW type instruction group does not affect the original instruction processing.

When M> N, that is, when the detected VL
If the number of VLIW-type instructions having empty instruction fields included in the IW-type instruction sequence is larger than N, the register used for overwriting the test operation result is the detected VL
It may be overwritten in the IW type instruction sequence. However, overwrite that register (has an instruction word)
From the VLIW-type instruction, the V that refers to the register last (having an instruction word) in the detected VLIW-type instruction sequence
There must be N VLIW-type instructions with empty instruction fields before the LIW-type instruction (if there is no VLIW-type instruction referring to the register, the first VLIW-type instruction).

[0013]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention.

In FIG. 1, reference numeral 1a denotes a VLIW composed of a VLIW type instruction word group in which an instruction word is arranged by a compiler or a linker (that is, after completion of compilation or linking).
An assembly list or an execution load module (hereinafter, referred to as a code before embedding) that can be executed by the type computer. Reference numeral 1b denotes a code (hereinafter referred to as a post-embedding code) after the test operation instruction word embedding by the test operation embedding device 2 described below is performed on the code 1a before embedding. In the present embodiment, the post-embedding code 1b is to be executed by the VLIW computer.

The code 1a before embedding execution in FIG.
In the post-embedding code 1b, one horizontal line is 1
A VLIW type instruction (cluster) is shown, and each vertical column in the VLIW type instruction shows an instruction field. In the code 1a before embedding and the code 1b after embedding, the shaded instruction fields indicate that instruction words are arranged, and blank instruction fields indicate empty instruction word allocable instruction fields (empty instruction fields). Field). In the post-embedding code 1b, the instruction field in which the character string “TEST” is written has an operation instruction (test operation instruction) for testing embedded in an empty instruction field (hereinafter simply referred to as an empty field). Indicates that

Reference numeral 2 denotes a test operation embedding device that executes a test operation instruction word embedding on the code 1a before embedding and generates a code 1b after embedding. The test operation embedding device 2 includes an empty field detection mechanism 2
1, a test operation embedding determination mechanism 22 and a test operation embedding mechanism 23.

The vacant field detection mechanism 21 is configured to execute a VLIW instruction including at least M VLIW instructions having at least one vacant field from the pre-embedding code 1a.
At least one type instruction sequence is detected. The test operation embedding determination mechanism 22 includes, in the VLIW type instruction sequence detected by the empty field detection mechanism 21, any N (where N ≦ M) test operation instructions necessary for detecting an abnormal operation of the VLIW type computer. It is determined whether it is possible to embed using an empty field. Test operation embedding mechanism 2
3 is a VL for which it has been determined by the test operation embedding determination mechanism 22 that the test operation instruction word can be embedded.
Regarding the IW-type instruction sequence, among the N VLIW-type instructions having an empty field included in the VLIW-type instruction sequence,
N test operation instructions are embedded using the empty field. Next, the operation of the test operation embedding device 2 in the configuration of FIG. 1 will be described with reference to the flowchart of FIG.

First, the empty field detection mechanism 21 in the test operation embedding device 2 checks the code 1a before embedding in order from the head VLIW type instruction (that is, the head cluster), and finds M VLIW type instructions having at least one empty field. A sequence of VLIW-type instructions (VLIW-type instruction sequences) that are included and are neither a branch source nor a branch destination are searched for (step S1).

If the target VLIW type instruction sequence exists, the empty field detecting mechanism 21
The range of the type instruction sequence (start cluster position and end cluster position) is notified to the test operation embedded discrimination mechanism 22 (step S2). And the empty field detecting mechanism 21
Returns to step S1 and sequentially executes the code 1a before embedding in order from the next VLIW-type instruction in the previously searched VLIW-type instruction sequence.
Is searched for a subsequent VLIW-type instruction sequence (a VLIW-type instruction sequence that includes M VLIW-type instructions having at least one empty field and is neither a branch source nor a branch destination). On the other hand, if the target VLIW type instruction sequence does not exist, the empty field detection mechanism 21 ends the processing (empty field detection processing).

When notified of the range of the VLIW type instruction sequence from the empty field detecting mechanism 21, the test operation embedding determining mechanism 22
A register overwritten in the next VLIW-type instruction of the VLIW-type instruction sequence indicated in the notified range (that is, a register designated as a destination) is searched (step S).
11).

If the target register exists,
The test operation embedding determination mechanism 22 determines that the register
It is checked whether or not it is referenced in the VLIW type instruction sequence in the range notified by the empty field detection mechanism 21 (that is, whether or not the source is specified) (step S12). Here, if the above-mentioned register is referred to, the test operation embedding determination mechanism 22 proceeds to step S
Returning to step 11, search for another overwritten register.

On the other hand, if the above register is not referred to, the test operation embedding / discriminating mechanism 22
It is determined that the test operation instruction words can be embedded in the VLIW-type instruction sequence in the range notified by the empty field detection mechanism 21 using the empty field, and the process of step S13 described below is executed. I do.

That is, the test operation embedded discrimination mechanism 22
N test operation commands for testing a VLIW type computer, which are operations that can predict the result in advance (for example, an integer type or floating point type operation with a known answer, or a memory containing a specific value). Is read out), and N test operation instruction words for storing and checking the result in the register (confirmed not being referred to in step S12) are determined. The test operation embedding mechanism 2 in the test operation embedding device 2 compares the word and the range of the VLIW type instruction sequence to be embedded.
Notify 3. And a test operation embedded discrimination mechanism 22
Returns to step S11 if it is necessary to embed (determine) the next test operation and if the range of the next VLIW-type instruction sequence is notified from the empty field detection mechanism 21, that is, if it is not the end (step S14). .

On the other hand, if the target register does not exist, the test operation embedding determining mechanism 22 determines that the embedding of the test operation instruction into the VLIW type instruction sequence notified by the empty field detecting mechanism 21 is impossible. I do. In this case, the test operation embedded discrimination mechanism 2
If the next test operation embedding (determination) is necessary and the empty field detection mechanism 21 notifies the next VLIW type instruction sequence range, the process returns to step S11. It should be noted that also when the VLIW type instruction following the VLIW type instruction sequence is a branch source or a branch destination, it is determined that the test operation instruction word cannot be embedded.

Each time the test operation embedding mechanism 23 receives the notification from the test operation embedding determination mechanism 22, the test operation embedding mechanism 23 replaces the notified N test operation instructions with the notified range in the code 1a before embedding execution. Each VLIW-type instruction is buried in a free field in the VLIW-type instruction sequence in units of one test-operation instruction for each VLIW-type instruction.

As described above, the test operation embedding mechanism 23 embeds the test operation instruction word in the pre-embedding code 1a each time the notification is sent from the test operation embedding determination mechanism 22. An operation instruction word can be embedded anywhere in the code 1a using the empty field of the code 1a before embedding. As a result, the code 1a before embedding is changed to the code 1b after embedding.

Therefore, by executing the post-embedding code 1b in which such a test operation instruction is embedded by a VLIW type computer (not shown), the test operation instruction is executed in parallel with the original instruction processing. To be processed,
It is possible to detect a computer abnormality without deteriorating the performance of the computer. Moreover, the register used for overwriting the test operation result is not referred to by the original instruction processing during the test operation processing, but is overwritten by the original instruction processing after the test operation processing. Therefore, the processing of the test operation instruction word embedded in the post-embedding code 1b does not affect the original instruction processing.

A specific example of the embedding of the test operation instruction word in the case where M = N = 2 will be described with reference to FIG. First, as shown in FIG. 3A, from the pre-embedding code 1a, M (= 2) VLIWs which have an empty field and become neither a branch source nor a branch destination are obtained by the empty field detection mechanism 21 of FIG. VLIW consisting of type instructions
It is assumed that the type instruction sequence 31 has been detected.

In this case, the test operation embedded discriminating mechanism 2
2 indicates that the VLIW-type instruction 32 following the VLIW-type instruction sequence 31 is neither a branch source nor a branch destination, and the instruction 32
The register (r3) that is overwritten as shown in the figure
Exists, it is checked whether or not the register (r3) is referenced in the VLIW type instruction sequence 31. If the register (r3) is not referred to in the VLIW type instruction sequence 31, the test operation embedded discrimination mechanism 2
2 is that the register (r3) can be used for storing the result in the test operation, and therefore, N (= 2) test operation instruction words can be embedded in the empty field of the VLIW type instruction sequence 31. And N (= 2) test operation instructions are determined. Here, “1 + 1 →
r3 "(instruction word for storing the addition result of 1 + 1 in r3) and is" r3 2 "? "(Command for checking whether the content of r3 is" 2 ") is determined.

The test operation embedding mechanism 23 receives the test operation command words “1 + 1 → r3” and “is r3 2?” Determined by the test operation embedding determination mechanism 22 in FIG.
As shown by reference numerals 33 and 34 in (b), VLIW
The VLIW-type instruction is buried in an empty field in the type instruction sequence 31 in units of one test operation instruction word in order from the first test operation instruction word.

Now, the first VL of the VLIW type instruction sequence 31
When the test operation instruction word “1 + 1 → r3” of code 33 embedded in the empty field of the IW type instruction is executed,
The addition result of "1 + 1" is stored in the register r3, and subsequently, is the test operation instruction word "r3 2" embedded in an empty field of the second (last) VLIW type instruction of the VLIW type instruction sequence 31? Is executed, it is checked whether or not the content of the register r3 is "2". r
If 3 = 2, the VLIW computer is normal and the next VL
The process proceeds to the IW type instruction processing. If r3 = 2, the VLIW type computer is abnormal and performs abnormal processing such as stopping the machine.

During the execution period of the test operation instruction words “1 + 1 → r3” and “is r3 2?” Embedded in the VLIW type instruction sequence 31, the original instruction processing in the VLIW type instruction sequence 31 is performed. The register r3 is not referred to. Moreover, the register r3 stores the next VLI of the VLIW type instruction sequence 31.
Overwritten by W-type instruction 32. Therefore, the test operation instruction word “1 + 1 → r” embedded in the VLIW type instruction sequence 31
3 "," r3 is 2? Does not affect the original instruction processing.

The case where M = N has been described above. However, when M> N, that is, the number of VLIW instructions having an empty field included in the VLIW instruction sequence detected by the empty field detecting mechanism 21 Is larger than N, the register used for overwriting the test operation result may be the register overwritten in the detected VLIW type instruction sequence. Here, the target VLIW-type instruction is overwritten while being switched in the order of the next VLIW-type instruction of the detected VLIW-type instruction sequence, the last instruction of this VLIW-type instruction sequence, the instruction immediately before that, and so on. It is possible to search for a register that is in use. However, from the VLIW type instruction which overwrites the register (has an instruction word),
In the detected VLIW-type instruction sequence, a VLIW-type instruction that refers to the register last (has an instruction word) (if there is no VLIW-type instruction that refers to the register, the first V
VLIW with empty fields before the LIW instruction)
There must be N type instructions.

Further, in the above-described embodiment, the empty field detecting process by the empty field detecting mechanism 21 is repeated until a VLIW type instruction sequence satisfying the predetermined condition is not found. However, the present invention is not limited to this. For example, if a predetermined number of VLIW-type instruction strings are found or a number required by the test operation embedded discrimination mechanism 22, the processing of the empty field detection mechanism 21 may be terminated. Alternatively, the test operation embedding determination mechanism 22 may sequentially request the empty field detection mechanism 21 to detect the empty field, and the empty field detection mechanism 21 may detect the empty field each time this request is made.

[0035]

As described in detail above, according to the present invention,
Utilizing a free field (a free instruction word allocable instruction field) existing in a VLIW type instruction group (code before embedding execution) after completion of compiling or linking,
A test operation instruction group necessary for detecting an abnormal operation of the W-type computer is embedded, and the VL after embedding the test operation instruction group is embedded.
Since the computer abnormality is detected by executing the IW instruction group, the computer abnormality detection processing (test operation instruction processing) can be performed in parallel with the original instruction processing in the VLIW instruction group. Therefore, a computer abnormality can be detected without lowering the computer performance.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing procedure of an empty field detection mechanism 21 and a test operation embedding determination mechanism 22 in the test operation embedding device 2 of FIG.

FIG. 3 is an exemplary view for explaining a specific operation in the embodiment.

[Explanation of symbols]

1a: code before embedding execution (VLIW type instruction group), 1
b: code after execution of embedding, 2: test operation embedding device, 21: empty field detection mechanism, 22: test operation embedding determination mechanism, 23: test operation embedding mechanism.

Claims (2)

(57) [Claims] 1. A VLIW (Very Long Instruction) having a plurality of instruction fields in which independent instruction words can be set.
In a VLIW-type computer for executing an instruction word, a free instruction field existing in a VLIW-type instruction group in which an instruction word is arranged by a compiler or a linker is searched, and the VLIW-type computer is used by using the empty instruction field. A test operation instruction group necessary for detecting an abnormal operation of the VL is embedded, and the VL after the test operation instruction group is embedded.
An abnormality detection method for a VLIW type computer, wherein a computer error is detected by executing an IW type instruction group. 2. A VL for executing a VLIW type instruction having a plurality of instruction fields in which independent instruction words can be set.
In the IW type computer, a VLIW instruction including at least M VLIW type instructions having at least one empty instruction field is selected from a group of VLIW type instructions in which instruction words are arranged by a compiler or a linker.
Detecting means for detecting at least one W-type instruction sequence; and in the VLIW-type instruction sequence detected by this detecting means, any N (where N ≦ M) necessary for detecting an abnormal operation of the VLIW-type computer Determining means for each VLIW-type instruction sequence as to whether or not the test operation instruction word can be embedded using the empty instruction field; and that the test operation instruction word can be embedded by the determination means. In the VLIW type instruction sequence for which is determined, among the N VLIW type instructions having an empty instruction field included in the VLIW type instruction sequence, the N test operation instruction words are utilized by using the empty instruction field. And a test operation embedding unit for embedding the test operation instruction word.
An abnormality detection method for a VLIW-type computer, wherein a computer abnormality is detected by executing a LIW-type instruction group.