JP4747028B2 - Microprocessor, information processing method and program using the same - Google Patents

Description

  The present invention relates to a microprocessor, and more particularly to a microprocessor that executes branch processing.

  In recent years, VLIW computer systems have been developed to speed up processing. Here, the VLIW method is a method in which a plurality of arithmetic units capable of operating in parallel are controlled by one long instruction word called VLIW (Very Long Instruction Word) which is a collection of a plurality of independent instructions. That is, this type of computer system includes a plurality of arithmetic units capable of operating in parallel, and operates by controlling each arithmetic unit individually and in parallel in synchronization with each independent command on the VLIW. .

  The VLIW processor as described above has an advantage that instructions having no dependency relationship between instructions can be simultaneously executed. On the contrary, depending on the processing, an arithmetic unit that is not used due to the dependency relationship is generated. There is a method of improving data integrity (reliability) by making use of this unused computing unit to duplicate the computation. For example, there is a method for detecting a hardware failure by a program by duplicating a process for testing the output of the preceding process and comparing the test results of the two (see Patent Document 1 below). .

JP 60-151753 A

  Here, when programming using the VLIW type processor as described above, it is common to use a compiler to generate code that can perform parallel processing most efficiently. At this time, when it is necessary to ensure the reliability of the hardware in the program, there is a case where coding is performed to improve the reliability consciously by the assembly language. In such a case, it is necessary to increase the failure detection rate of the processor without degrading the original performance of the program, but generally there is a tendency to conflict with the performance improvement.

  For example, in the conventional example of Patent Document 1 described above, since an actual branch process is executed after it is determined that the test results match, extra processing time is required until such a branch process is executed. Also, if the test results do not match due to a hardware failure, the recovery function for the failure is not provided, and the failed processor is disconnected from the system, or the system is stopped, etc. There was a problem that the process could not be continued because the process was being performed.

  For this reason, the present invention improves the inconveniences of the above-described conventional example, and in particular, improves recovery by executing recovery processing when a failure occurs in the hardware that performs branch processing, and decreases processing performance. It is an object of the present invention to provide a microprocessor capable of suppressing the problem.

Therefore, a microprocessor according to an embodiment of the present invention is
A plurality of test processing means for respectively testing the same predetermined processing result;
A plurality of branch processing means for performing branch processing according to the test results of each test processing means,
Trap means for executing failure handling processing when a predetermined branch processing means executed in preference to other branch processing means cannot be branched;
It is characterized by having.

  Specifically, the trap means is executed when the test result by the test processing means corresponding to the predetermined branch processing means is correct, but the branch cannot be made in the correct direction. Then, the trap means performs processing for acquiring information related to the failure of the predetermined branch processing means. Further, the trap means returns to the execution of the other branch processing means after the execution of the failure handling process.

  Further, the predetermined branch processing means and the other branch processing means are executed substantially in parallel. For example, the microprocessor includes a predetermined branch processing means and another branch processing means. It is a VLIW processor that is executed by different computing units.

  According to the above invention, first, a test of the same predetermined processing result is executed by a plurality of test processing means, and the same branch processing for the test is multiplexed by a plurality of branch processing means. Can be improved. In addition to this, even if a hardware failure occurs, such as when the predetermined branch processing means does not branch normally, recovery processing such as acquisition of such fault information is executed by the trap means, so that further reliability can be achieved. The improvement can be achieved, and the processing by the other branch processing means that follows can be executed, so that a decrease in processing performance can be suppressed. In particular, by using the VLIW processor to execute the same branch processing almost in parallel with different computing units, it is possible to more effectively suppress a decrease in processing performance.

Moreover, the program which is the other form of this invention is:
To the microprocessor
A plurality of test processing means for respectively testing the same predetermined processing result;
A plurality of branch processing means for performing branch processing according to the test results of each test processing means,
Trap means for executing failure handling processing when a predetermined branch processing means that is executed in preference to other branch processing means cannot branch.
It is characterized by realizing.

Furthermore, an information processing method by a microprocessor according to another aspect of the present invention is as follows.
The microprocessor
A plurality of branch condition test steps for respectively testing the same predetermined processing result, and a plurality of branch processing steps respectively executed according to the test result by each test processing,
Trap that executes failure handling processing when a predetermined branch processing step cannot be branched following a predetermined branch processing step that is executed in preference to other branch processing steps among a plurality of branch processing steps Having steps,
It is characterized by that.

  Even the program and the information processing method having the above-described configuration operate in the same manner as the above-described microprocessor, so that the above-described object of the present invention can be achieved.

  Since the present invention is configured and functions as described above, according to this, the test of the same predetermined processing result and the branch processing according to this are multiplexed, and compared with other branch processing means. In the event of a hardware failure, such as when a predetermined branch processing unit that is executed first does not branch normally, recovery processing such as acquisition of such failure information is performed by the trap unit, thereby improving reliability. In addition, the present invention has an unprecedented excellent effect that a decrease in processing performance can be suppressed without stopping the system by executing processing by another branch processing means that follows.

  The microprocessor according to the present invention is characterized in that recovery processing is performed during multiplexed branch processing. Hereinafter, in the embodiment, a case where it is realized by a VLIW processor will be described as an example.

  A first embodiment of the present invention will be described with reference to FIGS. FIGS. 1 and 2 are diagrams illustrating the configuration and operation of the microprocessor according to the present embodiment. FIG. 3 is a diagram illustrating a program example.

[Constitution]
As described above, the microprocessor according to this embodiment includes a plurality of arithmetic units capable of operating in parallel, and one long instruction called a VLIW (Very Long Instruction Word) which is a collection of a plurality of independent instructions. This is a VLIW processor controlled by words. FIG. 1 shows an information processing apparatus 70 equipped with this VLIW processor.

  Then, the configuration and operation as shown in FIG. 1 can be realized by incorporating the program according to the present invention in the processor of the information processing apparatus 70. Specifically, the information processing apparatus 70, that is, the VLIW processor, incorporates a program, thereby executing a function of executing the process W (10), a function of executing the process X (201), and a process W (10). A function (test processing means) for executing the test A (202) for testing the result of the test, a function (test processing means) for executing the test B (203) for performing the same test as the test A (202), and a test A A function (branch processing means) that executes a branch process a (301) that branches according to the result of (202), and a recovery process (60 that follows the branch process a (301) according to the result of test A (202) ) (Trap means) for executing a trap (302) that interrupts, and branch processing b (303) that branches after the trap (302) according to the result of the test B (203) Ability to run the (branch processing unit), are constructed. In addition, a function for executing a process Y (40) and a process Z (50) executed according to the results of the branch process a (301) and the branch process b (303) is also constructed.

  As described above, since the VLIW processor is equipped with a plurality of arithmetic units and can perform parallel processing, the functions described above operate in parallel as shown in FIG. Here, three arithmetic units are provided, and in cycle 1, the arithmetic unit 1 executes the process W (10), and the arithmetic units 2 and 3 are not used (nop). In the subsequent cycle 2 (reference numeral 20 in FIG. 1), the computing unit 1 performs the processing X (202), the computing unit 2 performs the test A (202), and the computing unit 3 performs the test B (203) in parallel. To run. Further, in the subsequent cycle 3 (reference numeral 30 in FIG. 1), the computing unit 1 performs the branch process a (301), the computing unit 2 performs the trap (302), and the computing unit 3 performs the branch process b (303) in parallel. To run.

  Here, the trap (302) is, in particular, when the branch process a (301) cannot branch normally between the duplex branch process a (301) and the branch process b (303), that is, It is executed when a hardware failure of the branch circuit occurs. The specific operation will be described in detail when the operation is described.

  The function of executing the recovery process (60) by the trap (302) is for collecting data necessary for leaving the status of the hardware failure that has occurred in the branch process a (301) and executing the branch process again. The program storage address of the interrupt source is calculated, and after data collection is completed, the process returns to the address next to the program storage address where the interrupt occurred, that is, the branch process b (303) (reference numerals 601 and 602 in FIG. 1). 603).

  Here, FIG. 3 shows an example in which the instruction sequence shown in FIG. 2 is coded by an assembly language mnemonic in the Intel RIA64 architecture software developer's manual. In the figure, “cmp” represents a comparison instruction. “Br” represents a branch instruction. “(P) br” represents a conditional branch instruction. “Break” represents an interrupt. “P” and “r” represent registers in which the results of test A (202) and test B (203) are stored, respectively. FIG. 4 shows an example in which the operation of the trap (302) is coded.

[Operation]
Next, the operation of the present invention will be described with reference to FIGS. First, as shown in FIG. 2, process W (10) is executed in cycle 1. Then, in the next cycle 2, a test for the preceding process W (10) is performed. That is, as shown in the cycle 20 of FIG. 1 and FIG. 2, the test A (202) is executed by the computing unit 2, and the test B (203) is executed by the computing unit 3 (test processing step). The test B (203) is a process in which the test A (202) is duplicated, and the result of the process W (10) is tested in the same manner as the test A (202).

  In the next cycle 30 shown in FIG. 1, that is, in cycle 3 shown in FIG. 2, the branch processing a (301) (predetermined branch processing step), trap (302) (trap step), and branch processing are performed by each arithmetic unit. b (303) (another branch processing step) is executed. At this time, the calculation of each branch destination address is executed almost simultaneously (in parallel), but the operation of actually jumping to the branch destination is the “# cycle 2” and “# cycle 3” in the coding example of FIG. As shown in the middle, the process is executed in the priority order of the branch process a (301), the trap (302), and the branch process b (303). That is, processing is executed in the order shown in the cycle 30 of FIG.

  Specifically, in branch process a (301), if the result of test A (202) is “true”, the process branches to process Y (40). That is, if the result of test A is branch GO (p = 1), the process proceeds to process Y (40), the prefetched trap (302), that is, “(p) break 10” shown in FIG. It does not jump to the branch destination of b (303), that is, “(r) br.cond.spnt Y”.

  Here, although the test result is correctly “true” (p = 1) due to a failure or the like of the branch circuit of the arithmetic unit 1 executing the branch process a (301), the actual process Y (40 ) Go to the trap (302). That is, priority shifts to “(p) break 10” shown in FIG. 3, and in this case, “p = 1”, so “break 10” is executed. Then, the recovery process (60) as the trap destination of the coding shown in FIG. 4 is executed, the trap source address is acquired and stored (601), and the fault process for collecting fault information and the like is executed (602). When the failure processing is completed, failure handling processing is performed to return to the address next to the trap source address (603). Thereafter, the process returns to the branch process b (303), the branch process b is executed, and the branch is normally executed here.

  On the other hand, in the branch process a (301), when the result of the test A (202) is “false”, or because of a hardware failure in which the register “p” is broken in the branch process a (301), the test A (202) If the result of (2) is illegal (predication register failure), the process proceeds to the trap (302) in the cycle 30 without branching to the process Y (40). However, since “p = 0” at this time, nothing is performed in the trap (302), and the process proceeds to the subsequent branch process b (303) in the cycle 30. Then, the branch process b (303) branches to the process Y (40) or proceeds to the process Z (50) depending on the result of the test B (203). In this case (failure of the arithmetic unit 2 in cycle 2), the result of the test B (203) is “true” and “r = 1”, so that the process Y (40) is normally performed in the branch process b (303). ).

  Even if both the arithmetic unit 1 and the arithmetic unit 2 are broken and cannot jump to “(p) br.cond.spnt Y” and “(p) break 10”, “(r) You can branch correctly with "br.cond.spnt". In the case of “p = r = 0”, the branch condition is not satisfied, so “(p) br.cond.spnt”, “(p) break 10”, “(r) br.cond.spnt” in cycle 3 “Y” is only the generation of the branch destination address, and the NOP operation is performed without actually jumping.

  As described above, according to the present invention, since the test processing as a branch condition is multiplexed, the reliability can be improved, and a hardware failure has occurred such that the branch processing a does not branch normally. Even in such a case, since the recovery process such as acquisition of the failure information is executed by the trap, the reliability can be further improved, and the process by the subsequent other branch process b is executed. Therefore, it is possible to suppress a decrease in processing performance. In particular, by using the VLIW processor to execute the same branch processes a and b almost in parallel with different arithmetic units, it is possible to more effectively suppress a decrease in processing performance.

  Here, it is not necessary to perform the test process using the same instruction for the processes of the duplicated test A and test B described above. Another test instruction that provides the logically same test result may be used in each test process.

  Further, in the above, test A and test B are performed in cycle 2 of FIG. 2, but test A and test B do not need to be performed in the next cycle of process W, and are executed at least after one cycle or more. That's fine. Furthermore, test A and test B do not necessarily have to be executed in the same cycle. The execution order of test A and test B is the same even if test B is executed first. However, the test A needs to be executed in the cycle before the branch process a, and it is only necessary to ensure that the test B is executed in the cycle before the branch process b.

  Furthermore, although the case where the test process is duplicated is described above, the test process may be configured to be triple or more. Thereby, the further improvement of reliability can be aimed at. In such a case, the corresponding branch process is executed for each test process. However, the recovery process, that is, the trap described above may be arranged between any branch processes. It is desirable to arrange in.

  INDUSTRIAL APPLICABILITY The present invention can be applied to uses such as development of a mission critical program that also needs to increase data integrity in a program that requires high performance, and has industrial applicability.

It is explanatory drawing which shows the structure and operation | movement of information processing apparatus. It is explanatory drawing which shows the structure and operation | movement of information processing apparatus. It is a figure which shows the example of coding. It is a figure which shows the example of coding.

Explanation of symbols

70 Information processing apparatus 202 Test A
203 Test B
301 Branch processing a
302 Trap 303 Branch processing b

Claims (8)

A plurality of test processing means for respectively testing the same predetermined processing result;
A plurality of branch processing means for performing branch processing according to the test results by the respective test processing means;
Trap means for executing failure handling processing when the predetermined branch processing means that is executed in preference to the other branch processing means fails to branch;
With
The processing is executed in the priority order of branch processing by the predetermined branch processing means, failure handling processing by the trap means, branch processing by the other branch processing means,
A microprocessor characterized by that.   2. The trap means is executed when the test result by the test processing means corresponding to the predetermined branch processing means is correct but the branch cannot be made in the correct direction. Microprocessor.   3. The microprocessor according to claim 1, wherein the trap means performs processing for acquiring information relating to a failure of the predetermined branch processing means.   4. The microprocessor according to claim 1, wherein branch processing by the other branch processing means is executed after execution of the failure handling processing by the trap means. Equipped with multiple computing units that can operate in parallel,
The branch processing by the predetermined branch processing means and the branch processing by the other branch processing means in one cycle are different from each other in the computing unit, the branch processing by the predetermined branch processing means, and the other branch processing means. 5. The microprocessor according to claim 1, wherein the microprocessor is executed in parallel with a priority order of branch processing according to claim 1. To the microprocessor
A plurality of test processing means for respectively testing the same predetermined processing result;
A plurality of branch processing means for performing branch processing according to the test results by the respective test processing means;
Trap means for executing failure handling processing when the predetermined branch processing means that is executed in preference to the other branch processing means cannot branch.
And realize
A program for causing the microprocessor to execute processing in a priority order of branch processing by the predetermined branch processing unit, failure handling processing by the trap unit, and branch processing by the other branch processing unit. The microprocessor
A plurality of test processing steps for respectively testing the same predetermined processing results, and a plurality of branch processing steps executed in accordance with the test results of each test processing,
Of the plurality of branch processing steps, following the predetermined branch processing step executed in preference to the other branch processing steps, the failure handling processing is performed when the predetermined branch processing step cannot branch. Having a trapping process to perform,
The processing is executed in the priority order of the branch processing by the predetermined branch processing step, the failure handling processing by the trap step, and the branch processing by the other branch processing step.
An information processing method using a microprocessor. 8. The information processing method by a microprocessor according to claim 7 , wherein branch processing by the other branch processing step is executed after execution of the failure handling processing by the trap step.

Images