JP3080028B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to an integrated circuit using MOS transistors in an input / output circuit.
ic Discharge (electrostatic discharge) protection technology.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a typical circuit configuration of an input circuit of an LSI. This input circuit is connected to an internal circuit from an assembling pad 31 through an ESD protection unit, an input unit (in this figure, a CMOS inverter). In this input circuit, high voltage due to external static electricity is weakened by the ESD protection unit,
It is configured not to directly apply to the input unit.

Referring to FIG. 3, the ESD protection unit includes an Nch
It comprises a MOS transistor NM2 and a PchMOS transistor MP2. The gate electrodes of these MOS transistors MN2 and MP2 are both clamped to the source potential and are in the off state. And
When a high voltage is applied by static electricity, a current is generated in these MOS transistors by the occurrence of breakdown or punch-through, or by turning on a diode.
By flowing to the DD or GND (ground) side, Pc
No high voltage is applied to the input section of the next stage including the hMOS transistor MP1 and the NchMOS transistor MN1.

FIG. 5 shows an example of a layout of a conventional ESD protection unit. In FIG. 5, 1 is Pch
The drain of the MOS transistor and the NchMOS transistor, 2 is the source, 3 is the gate, and 5 is the contact. The voltage from the pad (see FIG. 3) is P
chMOS transistor (MP2 in FIG. 3) and NchM
The electric charge is applied to the diffusion layer of the drain 1 of the OS transistor (MN2 in FIG. 3), and the electric charge gradually flows to the source side or the substrate side.

Here, when a voltage is suddenly applied, the charges are not completely removed, and the charges accumulate in the drain 1. If the charge stored in the drain 1 exceeds the allowable amount, the potential of the drain 1 increases. When the potential of the drain 1 exceeds a certain value, the PN junction of the drain 1 is broken. The voltage at this time becomes the ESD withstand voltage.

In order to sufficiently increase the ESD withstand voltage,
It is necessary to accumulate a certain amount of electric charge, and therefore, it is necessary to sufficiently increase the capacity of the diffusion layer of the drain 1.

The capacitance of the diffusion layer of the drain 1 is the sum of the capacitance at the bottom of the diffusion layer, the capacitance at the side surface of the diffusion layer, and the capacitance at the side surface of the gate. For example, in an NchMOS transistor, the diffusion layer bottom area is A · W, the diffusion layer side length is 2A + W, and the gate side length is W (where A is the gate of the drain 1 diffusion layer as shown in FIG. 5). The length along the length (channel length) direction), the diffusion layer bottom surface capacitance per unit area is Cj, the diffusion layer side surface capacitance per unit length is Cjsw, and the gate side surface capacitance per unit length is Cgdo. NchMO of drain 1
The diffusion layer capacitance C of the S transistor is given by the following equation (1).

[0008]

(Equation 1)

For example, at the drain 1 of the NchMOS transistor, W = 100 μm, A = 3 μm, Cj =
1.9 × 10 ⁻⁴ F / m ² , Cjsw = 1.9 × 10 ⁻¹⁰ F
/ M and Cgdo = 2.4 × ^{10 −10} F / m, the diffusion layer capacitance is 0.101 pF.

[0010] For example, Japanese Patent Application Laid-Open No. 57-152160 discloses a circuit to be protected and an input protection circuit having a sufficient effect on electrostatic charging without causing a delay of an input signal. A first input protection device having a resistor R1 on the input path between the input terminal and the input terminal, and a second input protection device having a resistor R2 and being located on the protected circuit side; Has been proposed.

[0011]

In the above prior art described with reference to FIGS. 3 and 5, in order to secure the ESD withstand voltage, it is necessary to secure a diffusion layer capacity for storing charges in a drain portion. It was necessary to increase the drain area. For this reason, the layout area of the ESD protection unit is increased, and the chip size of the LSI is increased.

Further, in order to increase the drain capacitance without increasing the area, it is necessary to change the process, which cannot be easily realized.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has as its object to reduce the layout area of an ESD protection circuit without reducing the effect of ESD protection, and to achieve high integration. It is an object of the present invention to provide a semiconductor device which achieves higher reliability and improved reliability.

[0014]

Means for Solving the Problems A semiconductor device of the present invention for achieving the above object, the ESD protection portion of the input-output circuit MOS
In the transistor, on the drain, a plurality of rectangular or polygonal planar materials made of the same material as the gate electrode
The pattern is formed, the pattern is, the gate and the collector
And a ground potential or a power supply potential.
It is characterized by the following.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. In the semiconductor device of the present invention, in a preferred embodiment, a predetermined planar shape, for example, a rectangular shape pattern made of the same material as the gate electrode is preferably formed on the drain of the MOS transistor constituting the ESD protection unit of the input circuit. A predetermined number is provided, and among the diffusion layer capacities of the drains, the capacitance at the side of the gate increases while the capacitance at the bottom of the diffusion layer decreases, and the capacitance at the diffusion layer of the drain increases as a whole. These patterns are preferably formed in the same step as the gate forming step.

In the embodiment of the present invention, a contact is provided on an upper portion of a pattern formed on a drain of a MOS transistor constituting an ESD protection portion of an input circuit, and the pattern has a source potential (VDD or GND potential) of the MOS transistor. ).

Further, according to another preferred embodiment of the present invention, a MO constituting an ESD protection unit of an input circuit is provided.
A predetermined number of patterns are provided on the drain of the S transistor from the side edge of the gate electrode to the drain side, that is, in a direction substantially perpendicular to the longitudinal direction of the gate electrode. Although the bottom capacity of the layer is reduced, the side capacity of the gate is increased, and the capacity of the diffusion layer of the drain is increased as a whole.

In a preferred embodiment of the present invention, an output MO having an ESD protection function of an output circuit is provided.
On the drain of the S transistor, a predetermined number of patterns having a predetermined planar shape, for example, a rectangular shape, which are preferably made of the same material as the gate electrode, may be provided to increase the diffusion layer capacitance of the drain. A predetermined number of patterns are provided on the drain of the output MOS transistor having the ESD protection function of the output circuit, the patterns protruding from the side edge of the gate electrode to the drain side, that is, in the direction orthogonal to the longitudinal direction of the gate electrode. Alternatively, the configuration may be such that the capacity of the drain diffusion layer increases.

As described above, in the embodiment of the present invention, in the ESD protection unit or the output MOS transistor, the same material as the gate electrode is used so that the area is small and the perimeter is long on the drain simultaneously with the formation of the gate. By forming the pattern, of the diffusion layer capacitance of the drain, the capacitance at the bottom of the diffusion layer is reduced, but the capacitance at the side of the gate is further increased. The area of the drain can be reduced without reduction.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 shows an ESD in one embodiment of the present invention.
It is a layout diagram for explaining a protection part. Referring to FIG. 1, in a semiconductor device according to the present embodiment, in a preferred embodiment, a pattern 4 of the same material as a gate electrode is formed on a drain 1 at the same time as a gate 3 is formed. Set to potential. At this time, of the diffusion layer capacitance of the drain, the capacitance at the bottom of the diffusion layer decreases, but the capacitance at the side of the gate increases. Since the gate side capacitance is larger than the diffusion layer bottom capacitance in the same area,
The overall capacity increases. For this reason, the area of the drain 1 can be reduced without reducing the capacitance of the drain 1.

In the embodiment of the present invention, since the pattern 4 is formed of the same material as that of the gate 3 and in the same manufacturing step as that of the gate formation, no change in the manufacturing process is required. In terms of realization, the area of the ESD protection unit, which cannot be solved by the conventional technology, can be reduced. Examples of the present invention will be described in more detail below.

In the present embodiment, the ESD protection unit is provided as shown in FIG.
As shown in the figure, NchMOS transistors MN2 and P
and a channel MOS transistor MP2.
The gate electrodes of the MOS transistors MN2 and MP2 are both clamped to the source potential and are in the off state.

Referring to the layout diagram of FIG. 1, in this embodiment, an NchMOS transistor and a PchMOS
Simultaneously with the formation of the gate 3 on the drain 1 of the transistor, a total of 49 patterns 4 made of the same material as the gate electrode and having a rectangular shape of a × b are formed.
A contact 5 'is disposed on the upper portion, and the source potential of each transistor, that is, the source potential of the PchMOS transistor MP2 is changed to the power supply potential VDD, Nch
The source potential of MOS transistor MN2 is equal to ground potential GN.
Connect to D.

At this time, the bottom capacitance of the diffusion layer is
, But the gate side surface capacitance increases by the perimeter of the pattern 4.

Referring to FIG. 1, Nch of the ESD protection circuit
For MOS transistors (corresponding to MN2 in FIG. 3)
The capacitance of the drain diffusion layer is obtained as follows.

The bottom area of the diffusion layer is A · W−49 · ab, the side length of the diffusion layer is 2A + W, and the side length of the gate is 2 (a + b) · 49 ten W, so that the diffusion per unit area is The layer bottom capacitance is Cj,
Assuming that the diffusion layer side surface capacitance per unit length is Cjsw and the gate side surface capacitance per unit length is Cgdo, the diffusion layer capacitance Cl of the drain 1 of the NchMOS transistor at this time is given by the following equation (2).

[0028]

(Equation 2)

That is, in this embodiment, the drain capacitance is increased by the following equation (3) as compared with the case where there is no pattern (see the above equation (1)).

[0030]

(Equation 3)

For example, if a = 1.5 μm and b = 1 μm,
When the values of the other parameters are the same as those of the above-described prior art, Nch
The value of the diffusion layer capacitance of the drain of the MOS transistor is
0.146 pF, and the same area as the above-mentioned prior art,
1.45 times the capacitance value is obtained.

As a result, in this embodiment, the drain area required to obtain the same capacitance value as that of the prior art is
1 / 1.45 or about 69% is sufficient.

It should be noted that the diffusion layer capacitance of the drain of the PchMOS transistor constituting the ESD protection unit of the input circuit can be obtained in the same manner as the above-mentioned NchMOS transistor.

By the way, the ESD protection circuit of this embodiment is
It can also be applied to output circuits. FIG. 4 is a diagram illustrating an example of a circuit configuration of the output circuit. Referring to FIG. 4, the output front stage includes a PchMOS transistor MP3 and an NchMO transistor.
An output MOS transistor having an ESD protection function, comprising an S transistor MN3, wherein the drains of the PchMOS transistor MP3 and the NchMOS transistor MN4 are connected to each other.
Input to transistor. The layout of the output MOS transistors MP4 and MN4 having the ESD protection function is basically the same as the layout diagram shown in FIG. However, in this output circuit, referring to FIG. 1, the gate 3 is connected to the output terminal of the output pre-stage in FIG.

Also in this output circuit, in the output MOS transistor having the ESD protection function, referring to FIG. 1, pattern 4 of the same material as the gate electrode formed simultaneously with gate 3 is connected to gate 3. However, these patterns 4 may be connected to GND or power supply VDD.

In FIG. 1, since the capacity of the diffusion layer is increased by the pattern 4 of the same material as the gate electrode formed simultaneously with the gate, the area can be reduced as compared with the case where the pattern 4 is not provided. The specific method of obtaining the numerical value is the same as that described above (see the above equations (2) and (3)).

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a layout diagram of an ESD protection unit according to a second embodiment of the present invention. Referring to FIG. 2, the ESD protection unit according to the present embodiment includes an NchMOS transistor and a Pch
It is composed of MOS transistors (for the circuit configuration, see the ESD protection section in FIG. 3). The gate electrodes of both MOS transistors are clamped at the source potential, and are turned off.

In the present embodiment, a pattern 6 in which the gate 3 is projected on the drain 1 in a direction substantially perpendicular to the longitudinal direction of the gate 3 is formed in a rectangular shape (width d, length c) having a dimension c × d. A total of 99 pieces are formed in size. Here, since the protrusion 6 of the gate is originally connected to the gate 3,
There is an advantage that there is no need to arrange and connect the contacts.

At this time, the capacitance of the bottom surface of the diffusion layer decreases by the area of the protrusion 6 of the gate, but the capacitance of the gate side surface increases by the peripheral length of the protrusion 6.

FIG. 2 shows the NchMOS transistor.
, The capacitance of the drain diffusion layer is obtained as follows.

Since the diffusion layer bottom area is A · W−99 · cd, the diffusion layer side length is 2A + W, and the gate side length is (2c + d) · 99 + W−99 · d, the diffusion per unit area is The layer bottom capacitance is Cj,
Assuming that the diffusion layer side capacitance per unit length is Cjsw and the gate side capacitance per unit length is Cgdo, the diffusion layer capacitance Cl of the drain of the NchMOS transistor at this time is
Is given by the following equation (4).

[0043]

(Equation 4)

That is, in this embodiment, the drain capacitance is increased by the following equation (5) as compared with the case where there is no protrusion pattern (see the above equation (1)).

108c · Cgdo-99 · c · d · Cj (5)

For example, c = 1.5 μm, d = 0.5 μm
When the values of other parameters are the same as in the conventional example, NchTr
The value of the diffusion layer capacitance of the drain is 0.126 pF,
1.24 times the capacitance value can be obtained in the same area. Therefore,
In order to obtain the same capacitance as that of the prior art, in the present embodiment, the drain area is 1 / 1.31, that is, about 80%.
Will be good. The PchMOS transistor of the ESD protection unit is similarly obtained.

[0047]

As described above, according to the present invention,
By increasing the drain capacitance of the MOS transistor of the ESD protection unit of the input circuit or the drain capacitance of the output transistor of the output circuit, the drain area is reduced,
There is an effect that the chip size of the SI can be reduced.

The reason for this is that, in the present invention, a pattern of the same material as the gate electrode having a small area and a long perimeter is formed on the drain at the same time as the gate is formed. This is because the capacitance at the bottom of the diffusion layer decreases, but the capacitance at the side of the gate further increases, so that the capacitance of the diffusion layer at the drain increases as a whole.

[Brief description of the drawings]

FIG. 1 is a layout diagram of an ESD protection unit according to one embodiment of the present invention.

FIG. 2 is a layout diagram of an ESD protection unit according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a circuit configuration of an input circuit including an ESD protection unit.

FIG. 4 is a diagram illustrating a circuit configuration of an output circuit having an ESD protection function.

FIG. 5 is a layout diagram of a conventional ESD protection unit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Drain 2 Source 3 Gate 4 Pattern of the same material as the gate electrode formed simultaneously with gate formation 5 Contact 6 Gate protrusion

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8232-21/8238 H01L 21/822 H01L 27/085-21/092 H01L 29/78 H01L 27 / 04

Claims (6)

(57) [Claims] 1. A MOS transistor of the ESD protection portion of the input and output circuits, on the drain, the planar shape made of the same material as the gate electrode
There plurality of patterns of rectangular or polygonal shape is formed,
The pattern is set to the same potential as the gate, and
A semiconductor device which is set at the same potential as a potential or a power supply potential . 2. A MOS constituting an ESD protection section of an input circuit.
On the drain of the transistor, the planar shape made of the same material as the gate electrode are formed a plurality of patterns <br/> over emissions of rectangular or polygonal shape, wherein the pattern is a gate at the same potential
And the same potential as the ground potential or the power supply potential,
A semiconductor device , wherein the MOS transistor is turned off . 3. A MOS constituting an ESD protection section of an input circuit.
A semiconductor device comprising a predetermined number of patterns on a drain of a transistor, the patterns protruding from a side edge of a gate electrode toward the drain. 4. An output M having an ESD protection function of an output circuit.
On the drain of the OS transistor, Do Ri planar shape of the same material as the gate electrode is a plurality of <br/> pattern of rectangular or polygonal shape is formed, said pattern and said gate electrode
Connected and set to the same potential as the gate potential, or
If the pattern is connected to ground or power,
Or the same potential as a power supply potential . 5. An output M having an ESD protection function of an output circuit.
A semiconductor device, comprising a predetermined number of patterns formed on a drain of an OS transistor and protruding from a side edge of a gate electrode toward the drain. 6. The method according to claim 2, wherein the pattern is formed in the same step as the step of forming the gate.
The semiconductor device according to any one of the above.