JP3076520B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates is related <br/> to the solid-state imaging equipment having a read gate structure of miniaturization possible signal charges.

[0002]

2. Description of the Related Art Conventionally, a solid-state imaging device is provided with a separation region for separating photoelectric conversion units in each pixel from each other and a reading region for reading electric charges accumulated in each photoelectric conversion unit. . These regions are invalid regions in terms of sensitivity, saturation characteristics, and the like. However, when the area of the photoelectric conversion unit is sufficiently large, the influence of the invalid region is small and it is not necessary to consider that much in practical use.

On the other hand, when the miniaturization of the solid-state imaging device is demanded as in recent years, the area of the above-mentioned ineffective region becomes a nonnegligible ratio with respect to the light receiving area. The problem has arisen. In other words, the downsizing of the solid-state imaging device leads to a lack of sensitivity due to a decrease in the light receiving area and a decrease in the incident light amount handling range due to a decrease in the pixel area. Further, at present, in a 1/3 inch class CCD solid-state imaging device, the signal charge amount handling range is about 8 bits.
When subjects of about 0 Lx and 5 Lx exist on the same screen, it is necessary to sacrifice either subject. For example, when the aperture of the lens or the electronic shutter is set to 5000 Lx, the sensitivity is insufficient. 5
When the subject of Lx is not captured and the lens aperture or electronic shutter is adjusted to the subject of 5Lx, the subject of 5000Lx generates a signal charge that exceeds the charge handled by the solid-state imaging device, resulting in overexposure. There is a problem peculiar to shooting in so-called backlight or over-direct light. In order to further expand the incident light handling range, a method of reading out two types of image information having different exposure periods during one field period into an external field-memory or the like has been considered.

[0004]

However, as a problem resulting from the miniaturization of the element, the sensitivity and the saturation characteristics can be improved by increasing the area of the photoelectric conversion unit. The read gates for reading the signal charges from the conversion section both have independent areas for improving the sensitivity and the saturation characteristics. There was a problem of receiving.

The present invention solves the two problems caused by the miniaturization of the device described above, 1) the problem that the sensitivity of the device is reduced, and 2) the problem that the saturated charge amount of the device is reduced. It is an object of the present invention to provide a solid-state imaging device having a new read gate structure capable of reducing the ratio.

[0006]

According to the present invention, the readout gate, which is conventionally provided separately from the pixel separating section, is eliminated, and the pixel separating section is also used for the reading function, thereby improving the actual opening area. In order to improve the sensitivity due to the above, a potential gradient is provided in the photoelectric conversion unit and the read gate in order to completely read from the pixel unit to the transfer unit. Further, a vertical charge transfer means (Vertical Charge Cou
By applying a drive method that reads / transfers the signal charge amount of the two types of exposure time independently for each line to the "pled Device", it is possible to suppress an increase in the circuit scale, for example, by omitting the external field-memory. I do.

According to a first aspect of the present invention, a plurality of unit pixels arranged in a one-dimensional direction in the Y direction or in a two-dimensional direction in the XY direction emit electromagnetic waves or X-rays incident on the unit pixels as signal charges. A photoelectric conversion unit including at least one or more impurities provided for converting the signal charge into a Y-direction, and adjoining the photoelectric conversion unit in the X-direction, and
A charge transfer unit for transferring in the direction, and at a boundary between the photoelectric conversion units adjacent to each other in the Y direction in the solid-state imaging device, a separation function for separating the photoelectric conversion units from each other and the charge from the photoelectric conversion units. first means and reading function of reading rolling signal charges to means is also used provided, the first
Means that at least one or more electrodes are formed on the upper part.
And has a semiconductor portion at the bottom,
The direction in which the semiconductor portion of the first means is directed to the charge transfer means.
In contrast, the solid-state imaging device has a gradient in the impurity concentration distribution .

According to a second aspect of the present invention, the unit pixel includes the unit pixel.
Converts electromagnetic waves or X-rays incident on a pixel into signal charges
At least one or more of the first
A photoelectric conversion unit containing impurities, and
For transferring the signal charges in the Y direction.
A charge transfer means, and a one-dimensional direction in the Y direction.
Or the unit pixels arranged in a two-dimensional direction of XY directions
At the boundary between the photoelectric conversion units adjacent in the Y direction.
Separating means for separating the photoelectric conversion units from each other;
Reading signal charges from the photoelectric conversion unit to the charge transfer means;
Reading means are provided alternately in the Y direction every other one.
The separating means or the reading means is
Read-out means.
Has at least one or more electrodes formed on the top
Having a semiconductor portion below the
The semiconductor part of the means is opposed to the charge transfer means.
And has a gradient in the impurity concentration distribution.
A solid-state imaging device.

According to a third aspect of the present invention, the gradient of the concentration distribution is provided.
The concentration of the first impurity as approaching the charge transfer means.
Degree distribution is higher or reverse polarity to the first impurity
Having the structure 1a in which the concentration distribution of the second impurity is low.
Or from the second impurity to the first impurity
And a 1b structure in which the impurity distribution changes.
This is the solid-state imaging device described above .

According to a fourth aspect of the present invention, there is provided a semiconductor device comprising:
The gradient of the distribution is obtained by at least two or more ion implantations.
The above-described solid-state imaging device is formed.

According to the present invention, despite the downsizing of the image pickup device, the sensitivity is improved and the amount of electric charges handled with respect to the amount of incident light is improved. Also, despite the signal charge readout from the separation unit, there is no afterimage from the photoelectric conversion unit. Readout of signal charges is realized.

[0012]

FIG. 1 shows a first embodiment of the present invention.
This will be described with reference to FIG.

FIG. 46 shows a top view of a conventional CCD solid-state imaging device for comparison. In the conventional CCD structure, as shown in FIG.
diode) is composed of a VCCD 2201 as signal charge transfer means adjacent to the PD 2200, and the VCCD 2201 has a drive pulse φV1 2211 and a drive pulse φV so that four-phase drive pulses are applied.
2; 2212; drive pulse φV3; 2213; drive pulse φV4; 2214. PD; 220
From the photodiode which is 0 to VC which is the vertical transmission means
For reading signal charges from the CD 2201, a read gate 2204 provided for the drive pulse φV1 2211 and the drive pulse φV3 2213 is set. In the conventional CCD structure, as the CCD size becomes smaller, the V pitch: 2205, which is a vertical repetition unit of the pixel size, becomes narrower, and the read gate width: 22
06 also gets smaller. Due to the narrow channel effect caused by the narrowing of the read gate width;
220 from the photodiode which is 200;
A high voltage (for example, 15 V or more) is required for the first drive pulse; 2211 and the third drive pulse;

FIG. 1 shows a first embodiment. In the present embodiment, the unit pixel is a first-layer polysilicon; 101, a first-layer polysilicon;
Layer polysilicon 103; Second layer polysilicon 10
Electrode 4 and photoelectric conversion unit (Photo Diode) PD; 10
5, PD; A drive pulse φV 1; 111 and a drive pulse φV
2; 112, drive pulse φV3; 113, drive pulse φ
V4; 114, a drive pulse φV5; 115, a drive pulse φV6; 116, a drive pulse φV7; 117, and a drive pulse φV8; 118 are applied. Also, a unit pixel; 12
A read gate 107 is provided at the center of one pixel which is 0. If the structure according to the present embodiment is used,
VCCD; When high density in the direction of 100 is required,
Despite the reduction of the V pitch: 109, an almost constant read gate width; 110 can be secured.
Therefore, all pixel readouts that require double density in the vertical direction
In the case of (Progressive Scan) applications or HDTV applications, it is possible to avoid increasing the read voltage due to the narrow channel effect as described above. In the present embodiment, by providing the vertical separation portion 108 between pixels, the same PD pair is always possessed (for example, at the time of reading, the driving pulse φV
7; 117 by applying a read voltage to P
D; 105 and PD; 106 are mixed, and the signal charges are mixed and read out to the VCCD; 100). In this embodiment, there is no problem if the configuration and role of the first polysilicon layer and the second polysilicon layer are reversed. Also, the type of pulse of the applied voltage is φV1 here.
Although eight types of φV8 have been described, φV1 and φV8
5, φV2 and φV6, φV3 and φV7, φV4 and φV8
It is needless to say that by applying the same drive pulse to each of them, even if four or less types of pulses are used, the device functions as a conventional solid-state imaging device. Although the present embodiment has been described using a two-layer polysilicon structure, it is to be added that the present invention can be implemented using a three-layer or more polysilicon structure. PD; 105 and PD; 106
May or may not be connected in the semiconductor substrate below the read gate 107.

FIG. 2 shows a second embodiment. Note that FIG. 2 shows a case where the vertical separation portion 108 existing in FIG.
7, 208. In this embodiment mode, the unit pixel is a first-layer polysilicon; 201, a first-layer polysilicon; 202, a second-layer polysilicon; 203, a second-layer polysilicon; ;
205, PD; 206. VCCD; 20
A drive pulse φV
1, 211; drive pulse φV2; 212, drive pulse φ
V3; 213, drive pulse φV4; 214, drive pulse φV5; 215, drive pulse φV6; 216, drive pulse φV7; 217, and drive pulse φV8; 218 are applied. A readout gate 207 is provided at the center of one pixel which is a unit pixel 223. When the structure according to the present embodiment is used, when it is necessary to increase the density in the direction of the VCCD; 200, it is possible to secure a substantially constant read gate width; 210 despite the reduction of the V pitch: 209. It becomes possible. Therefore, it is possible to avoid an increase in the read voltage due to the narrow channel effect as described above. In the present embodiment, the read gate; 207, the read gate;
Is always provided between PDs in the vertical direction, so that the solid-state imaging device can be configured by shifting the unit pixel; 223 by one PD in the vertical direction. For example, when reading the A_field, a read voltage is applied to the drive pulse φV3; 213 and the drive pulse φV7; 217, so that PD; 220 and PD;
206 and the signal charges stored in the pair PD; 205 and PD; 206 are mixed independently and read out to the VCCD; 200. In the subsequent B_field, the driving pulse φV5; By applying a read voltage to the drive pulse φV1 211, a read method is realized in which signal charges accumulated in the pair PD; 221 and PD 205 are independently mixed and read out to the VCCD 200.

In this embodiment, there is no problem if the configuration and role of the first polysilicon layer and the second polysilicon layer are reversed. Also, here, eight types of applied voltage pulses are described from φV1 to φV8, but φV1 and φV5, φV2 and φV8
6, by applying the same drive pulse to each of φV3 and φV7 and φV4 and φV8, it goes without saying that even if four or less types of pulses are used, they function as a solid-state imaging device as in the related art. Further, the present invention is not limited to this. Although the present embodiment has been described with a two-layer polysilicon structure, it is to be added that the present embodiment can be implemented using a three-layer polysilicon or a four-layer polysilicon structure.

Next, a third embodiment will be described with reference to FIGS.

FIG. 3 is a graph showing the vertical length V of a unit pixel.
It is sectional drawing in the range of 300 pitches. In the figure,
A photoelectric conversion region provided in a semiconductor substrate; a first N layer, which is 301; a second N layer; 306, a third N layer
Layer; 307; fourth N layer; 308; fifth N layer;
9 and a first-layer polysilicon layer 302 and a second-layer polysilicon layer 303 forming a read gate via an oxide film 304.

As described above, the first N layer;
5, a second N layer; 306 and a third N layer; 307 constitute a photoelectric conversion portion, and are formed by performing ion implantation or the like of N-type impurities such as phosphorus divided into three or more times. Is done. The second N layer; 306 is more N than the first N layer;
The third N-layer 307 is set to have a higher N-type impurity concentration than the second N-layer 306. A fourth N layer; 308, a signal charge generated in the semiconductor substrate of the photoelectric conversion region;
This is for forming a read channel for reading in the fifth N layer 309 constituting the CD.

FIG. 4 is a diagram illustrating a cut surface parallel to the semiconductor surface and having a depth of X1-X1 'drawn from the upper surface for the purpose of making it easier to see the impurity distribution inside the semiconductor. As described above, the fifth N layer 309 constitutes a VCCD portion which is a vertical charge transfer means.

FIG. 5 shows a potential distribution at the time of reading out signal charges in the unit pixel shown in FIGS.

Here, the potential distribution inside the semiconductor when a voltage for reading (for example, 15 V) is applied to the first layer of polysilicon 302 is shown. Here, the second N layer; 306 has a higher N-type impurity concentration than the first N layer; 305, and the third N layer; The mold impurity concentration is set to be high. As shown in the figure, in the unit pixel, a first N layer forming a peripheral region of the photoelectric conversion unit; 3
As the read channel formed in the fourth N layer 308 formed below the first polysilicon layer 302 from the region 05 is approached, a monotonous potential gradient is generated inside the semiconductor, as indicated by the arrow. And the drift movement of the signal charge 310 can be performed smoothly.

In the present description, the photoelectric conversion area: 301
From the first N layer; 305 to the third N layer;
Although three types of implantation regions up to 7 are set, even if impurity concentration distribution layers having different concentrations are formed from two types of implantation regions, or three types or more, the impurity concentration distribution layers in the photoelectric conversion unit peripheral region are further increased. Even if a P-type impurity is partially used,
A function of generating a monotonous potential gradient inside the semiconductor as approaching the read channel formed under the first-layer polysilicon; 302, which is a read gate from the photoelectric conversion portion peripheral region. Is added.

Next, a fourth embodiment will be described with reference to FIGS.

FIG. 6 shows the vertical length V of a unit pixel.
It is sectional drawing in the range of the pitch; 400. In the figure,
A photoelectric conversion region provided in a semiconductor substrate; a first N layer 401, which is 401; a fourth N layer; 406, a fifth N layer
A first-layer polysilicon 402 and a second-layer polysilicon 403 forming a read gate via a layer 407 and an oxide film 404 are shown. Here, second-layer polysilicon; 4
03 is a first N layer; 40 in the photoelectric conversion region;
5 covers a partial area or the entire area.

As described above, the first N layer;
Constitutes a photoelectric conversion portion, and N such as phosphorus once
It is formed by performing type impurity ion implantation or the like. A fourth N layer; 406 is a signal charge generated in the semiconductor substrate of the photoelectric conversion region;
In order to form a read channel for reading in the N layer 407;

FIG. 7 is a diagram in which a cut surface at a depth of X2-X2 'parallel to the semiconductor surface is drawn from the upper surface for the purpose of making it easier to see the impurity distribution inside the semiconductor. As described above, the fifth N layer; 407 constitutes a VCCD portion which is a vertical charge transfer means.

FIG. 8 shows a potential distribution at the time of reading out signal charges from the unit pixels shown in FIGS. 6 and 7.

Here, a read voltage (for example, 15 V) is applied to the first polysilicon layer 402;
Second layer polysilicon; 403 also first layer polysilicon;
A potential distribution inside the semiconductor when the same or slightly lower voltage (for example, 13 V) as that applied to 402 is applied is shown. Here, the second-layer polysilicon 403 covers at least a part of the region above the first N-layer 405 in the photoelectric conversion region 401. As shown in the figure, in the unit pixel, a first N layer forming a photoelectric conversion portion peripheral region; a first layer polysilicon from a region of 405; a fourth N layer formed below 402;
As approaching the read channel formed in 6, a monotonous potential gradient is generated inside the semiconductor, which makes it possible to smoothly carry out the drift movement of the signal charge 408 as shown by the arrow.

In this description, the photoelectric conversion area: 401
From the first N layer; 405 to the fourth N layer;
Although four types of injection regions up to 6 were set,
A first-layer polysilicon which is a read gate from the photoelectric conversion unit peripheral region even if it is formed by the same kind of impurity layer having a concentration of more than one kind and further uses a P-type impurity partially in the photoelectric conversion unit peripheral region; It should be added that a function of generating a monotonous potential gradient inside the semiconductor can be realized as the read channel formed below 402 is approached.

Next, a fifth embodiment will be described with reference to FIGS.

FIG. 9 is a cross-sectional view in the case where the unit pixel is cut in the substrate depth direction at a line substantially parallel to the vertical transfer means at a substantially central portion of the unit pixel. V pitch; 500 indicates the length of the unit pixel. In the figure, a first polysilicon layer 502 and a second polysilicon layer 503 of a read gate via a photoelectric conversion region 501 and an oxide film 504 are shown.

FIG. 10 is a diagram in which a cut surface is drawn from the upper surface at a position of X3-X3 'parallel to the semiconductor surface to make it easier to see the impurity distribution inside the semiconductor. Here, a fifth N layer; 507 constitutes a VCCD section which is a vertical charge transfer means. 4th N
Layer; 506 is a photoelectric conversion region; 501, the signal charges generated in the semiconductor substrate of the fifth
Layer; forming a read channel for reading. In the figure, a first N layer; 505, a first polysilicon layer; a fourth N layer formed below 502; a triangular implantation formed below 506 and a first polysilicon layer 501; A P-layer with shape: 508 is shown. In the P layer 508 having a triangular implantation shape, the impurity concentration of the N layer becomes higher toward the fifth N layer 507 forming the transfer path of the vertical transfer means VCCD by the subsequent thermal diffusion process. (For example, 1
Readout voltage +15 applied to 502 electrode
The potential at the time of reading (when V is applied) also increases monotonically, and the drift movement from the reading channel to the vertical transfer means can be performed in a short time.

FIG. 11 shows a bird's-eye view of almost half of the unit pixel.

FIG. 12 shows that in the pixel structure shown in FIGS. 9 and 10, a readout voltage was applied to the first-layer polysilicon 502 (for example, +15 V was applied to the electrode of the first-layer polysilicon 502). 2) shows the potential distribution inside the semiconductor in the case (1). At this time, a signal moved from a region of the first N layer 505 which is a peripheral region of the photoelectric conversion portion to a read channel formed in the fourth N layer formed under the first polysilicon layer 502 from the region of 505 The charge is
Due to the monotonous potential gradient inside the channel generated based on the impurity concentration gradient in the channel, the channel moves in the direction of the arrow using the drift electric field.

In this description, the P layer 508 is assumed to have a triangular implantation shape such as P-type impurity ion implantation of boron or the like, but the fifth N-type implantation shape corresponding to the transfer path of the VCCD is assumed. Layer; a function of generating a monotonous potential gradient inside the read channel formed under the first-layer polysilicon 502 whether it is a sector shape or a trapezoidal shape as long as the width of the implantation region is reduced as it approaches 507. It is emphasized that.

Next, a sixth embodiment will be described with reference to FIGS. 13, 14, 15, and 16. FIG.

FIG. 13 is a cross-sectional view in the case where the unit pixel is cut in the depth direction of the substrate at a substantially central portion of the unit pixel along a line parallel to the vertical transfer means. V pitch; 600 indicates the length of the unit pixel. The figure also shows a first-layer polysilicon layer 602 and a second-layer polysilicon layer 603 of a read gate via a photoelectric conversion region 601 and an oxide film 604.

FIG. 14 is a diagram in which a cut surface is drawn from the upper surface at a position of a depth of X4-X4 'parallel to the semiconductor surface in order to make the impurity distribution inside the semiconductor easier to see. Here, a fifth N layer; 607 constitutes a VCCD portion which is a vertical charge transfer means. 4th N
A layer 606 forms a read channel for reading out signal charges generated in the semiconductor substrate of the first N layer 605 which is a photoelectric conversion region to a fifth N layer 607 constituting the VCCD. In the figure, a first N layer; 605, a first polysilicon layer; a P layer formed under 602;
And a fourth N layer 606 having a triangular implant shape formed under the first polysilicon layer 602. A fourth N layer 606 having a triangular implant shape:
By the subsequent heat diffusion process, the vertical transfer means VCC
Since the impurity concentration of the N-layer becomes higher toward the fifth N-layer 607 forming the transfer path for D, as described later (for example, a first polysilicon layer; The potential potential at the time of reading also increases monotonically, and the drift movement from the first-layer polysilicon 602 serving as the reading gate to the vertical transfer means can be performed in a short time.

FIG. 15 shows a bird's-eye view of almost half of the unit pixel.

FIG. 16 shows a readout voltage applied to the first-layer polysilicon 602 (for example, a readout voltage +15 V applied to the first-layer polysilicon 602 electrode) in the pixel structure shown in FIGS. 3 shows a potential distribution inside the semiconductor in the case. At this time, the first N layer which is a peripheral region of the photoelectric conversion portion; the first polysilicon from the region of 605; the fourth N layer having a triangular implantation shape formed below the first polysilicon layer 602; The signal charge that has moved to the read channel moves using a drift electric field in the direction of the arrow due to a monotonous potential gradient inside the channel generated based on the impurity concentration gradient in the channel.

In the present description, the fourth N layer 606 is assumed to have a triangular implantation shape such as the implantation of N-type impurity ions such as phosphorus, but the fourth N layer 606 corresponds to the transfer path of the VCCD. An N-layer of 5; an inverted fan type or an inverted trapezoidal type as long as the width of the injection region is increased as approaching 607;
It is emphasized that the function of generating a monotonous potential gradient inside the read channel formed below the first polysilicon layer 602 can be realized.

Next, referring to FIGS. 17, 18, 19 and 20,
A seventh embodiment will be described.

FIG. 17 is a cross-sectional view in the case where the unit pixel is cut at a substantially central portion of the unit pixel along a line parallel to the vertical transfer means in the depth direction of the substrate. V pitch; 700 indicates the length of the unit pixel. The figure also shows a first-layer polysilicon layer 702 and a second-layer polysilicon layer 703 of a read gate via a photoelectric conversion region 701 and an oxide film 704.

FIG. 18 is a diagram in which a cut surface is drawn from the upper surface at a position of X5-X5 ′ parallel to the semiconductor surface to make it easier to see the impurity distribution inside the semiconductor. Here, a fifth N layer; 707 constitutes a VCCD portion as a vertical charge transfer means. 4th N
706 and a seventh N layer; 709 is a first N layer which is a photoelectric conversion region; 705 is a signal charge generated in a semiconductor substrate of 705 is read out to a fifth N layer constituting a VCCD; A read channel for reading. In the figure,
A first N layer; 705, a P layer; 708, a fourth N layer;
6, a seventh N-layer; 709 is shown. Fourth N-layer:
Since impurity implantation such as ion implantation is performed so that the impurity concentration of the seventh N layer becomes higher than that of 706,
(As described later, for example, first-layer polysilicon; 702
When a read voltage of +15 V is applied to the first electrode), the potential at the time of reading also increases monotonically, and the drift movement from the first-layer polysilicon 702 as the read gate to the vertical transfer means can be performed in a short time. Become.

FIG. 19 is a bird's-eye view showing almost half of the unit image.

FIG. 20 shows a readout voltage applied to the first-layer polysilicon 702 in the pixel structure shown in FIGS. 17 and 18 (for example, a readout voltage +15 V applied to the electrode of the first-layer polysilicon 702). 3 shows a potential distribution inside the semiconductor in the case. At this time, the first N-layer, which is the peripheral region of the photoelectric conversion portion; the first polysilicon from the region of 705; the fourth N-layer formed below 702; 706 and the seventh N-layer; The signal charge that has moved to the read channel to be formed moves using a drift electric field in the direction of the arrow due to a monotonous potential gradient inside the channel generated based on the impurity concentration gradient in the channel.

In this description, two types of N-type impurity ion implanted layers, that is, a fourth N layer; 706 and a seventh N layer; 709, are assumed. It is emphasized that the function of generating a monotonous potential gradient inside the readout channel can also be exhibited by forming the layer polysilicon below the layer 702 and implanting it gradually into the N-type, so that the potential becomes monotonic. Keep it.

Next, an eighth embodiment will be described with reference to FIGS. 21, 22, 23 and 24. FIG. 21 is a cross-sectional view of a case where the unit pixel is cut in the substrate depth direction at a line substantially parallel to the vertical transfer unit at a substantially central portion. V pitch; 800 indicates the length of the unit pixel. In the figure, the photoelectric conversion region;
801 and oxide film; first layer polysilicon of read gate via 804; 802 and second layer polysilicon; 803
Is shown.

FIG. 22 is a diagram in which the cut surface at the position of the first-layer polysilicon parallel to the semiconductor surface is drawn from the upper surface so that the impurity distribution inside the semiconductor can be easily seen. Here, a fifth N layer; 807 constitutes a VCCD portion as a vertical charge transfer means. 4th N
A layer 806 forms a read channel for reading out signal charges generated in the semiconductor substrate of the first N layer 805 which is a photoelectric conversion region to a fifth N layer 807 constituting the VCCD. In the figure, the first N layer;
806 and a first polysilicon layer 802 are shown. The first-layer polysilicon 802 has a shape corresponding to a trapezoid or a wedge that becomes wider as approaching the fifth N-layer which is a VCCD.
(As described later, for example, first-layer polysilicon; 802
When a read voltage of +15 V is applied to the first electrode), the potential at the time of reading increases monotonically toward the fifth N-layer; 807 due to the narrow channel effect, and the first-layer polysilicon as the read gate: 802
Drift movement from the vertical transfer means to the vertical transfer means can be performed in a short time.

FIG. 23 shows a bird's-eye view of almost half of the unit pixel.

FIG. 24 shows a readout voltage applied to the first-layer polysilicon 802 in the pixel structure shown in FIGS. 21 and 22 (for example, a readout voltage +15 V applied to the electrode of the first-layer polysilicon 802). 3 shows a potential distribution inside the semiconductor in the case. At this time, a signal moved from the region of the first N layer 805 which is a peripheral region of the photoelectric conversion portion to the readout channel formed in the fourth N layer formed under the first polysilicon layer 802 from the region of 805 The charge is
Due to the monotonous potential gradient inside the channel caused by the narrow channel effect created by the shape of the first-layer polysilicon, it moves using a drift electric field in the direction of the arrow.

Next, a ninth embodiment will be described with reference to FIGS.

FIGS. 25 and 26 show an example of a two-dimensional solid-state imaging device in which the element structure shown in FIGS. 9, 10, 11, and 12 employs unit pixels to realize the arrangement shown in FIG. It is.

FIG. 25 is a top view of a solid-state imaging device formed in a two-dimensional array. A part of the device is drawn toward the lower right so that the structure inside can be easily seen. The components are first layer polysilicon; 901, second layer polysilicon; 9
02, PD (Photodiode) which is a photoelectric conversion unit;
A read gate (formed of, for example, a first-layer polysilicon gate and a second-layer polysilicon gate); 904; a read channel (here, an N-layer) formed in a semiconductor below the read gate; 905; P layer for preventing erroneously flowing into the VCCD of the unit pixel adjacent in the horizontal direction; 906, a P layer for defining a transfer channel region of the VCCD; 907, for transferring signal charges in the direction of the arrow VCCD; 908. Unit pixel; 9
00 is indicated by an area indicated by a chain line. In order to drive the two-dimensionally arrayed solid-state imaging device, a driving pulse φV1; 911, a driving pulse φV2; 912, a driving pulse φV3; 913, a driving pulse φV4;
Drive pulse φV5; 915, drive pulse φV6; 91
6, drive pulse φV7; 917, drive pulse φV8; 9
A total of eighteen eight-phase drive pulses are employed.

FIG. 26 is a bird's-eye view of the solid-state imaging device formed into a two-dimensional array. Part of the structure is drawn downward in the figure to make it easier to see the structure inside. Form of this implementation
Oite the state, as mentioned above, the read gate structure is adopted that shown in FIGS. 9, 10, 11, 12, 13-16, 17-20, Figure 21-24 It is needless to say that the pixel structure shown in FIG.

Next, a tenth embodiment will be described with reference to FIGS. 27, 28, 29 and 30.

FIGS. 27, 28 and 29 show signal charge transfer diagrams.
FIG. 30 is a timing chart showing the VC of the photoelectric conversion unit.
An example of a signal charge read / transfer operation of a solid-state imaging device having an eight-phase electrode structure in a CD will be described.

FIG. 27 is a diagram showing a time chart when the solid-state imaging device having the eight-phase electrode structure shown in FIGS. 25 and 26 performs a read / transfer operation in a scanning mode conforming to NTSC. In the figure, the horizontal axis represents time, and the vertical axis represents A-field periods; 1001 and B-field periods;
5 shows a signal charge amount Qsig; Here, an A-field period; TAF1, which is a reading time of the signal charge in 1001, and a B-field period;
TBF, which is the read time of the signal charge in 005
1; 1007 will be described as being set immediately after entering the V-blank period in each field, but it should be emphasized that the present invention does not particularly limit the read time.

FIG. 28 shows an example of a read / transfer operation for mixing two pixels. At the left end, an eight-phase drive pulse (drive pulse φ) applied to the transfer electrode of the VCCD of each pixel.
V1; 1021, drive pulse φV2; 1022, drive pulse φV3; 1023, drive pulse φV4;
Drive pulse φV5; 1025, drive pulse φV6; 10
26, drive pulse φV7; 1027, drive pulse φV
8; 1028), and the flow of a series of signal charge transfer operations using signal charge packets started from the read operation of TAF1; 1003 is followed by time (here, every clock) until the time of TAF16; 1004. It is drawn schematically.

In FIG. 28, black squares indicate signal charge readout; 1014, hatched squares indicate signal charge packets;
1015, open squares indicate barriers; 1016. A-field shown on the left; TAF1; 1 in 1001
3 clocks after the read operation of 003, the pixel;
10 and a pixel; 1011; a pixel; 1012 and a pixel; 101
3 are mixed, and the B-field; 1005 shown on the right side of FIG.
, The pixel; 1010 is not shown in the figure, but the operation of mixing another upper pixel and the pixel; 1013 with another lower pixel is executed.

The same operation is repeated in the B-field; 1005.

In FIG. 29, in FIG. 28, TAF5; 1 where the signal charge packet is minimized after two pixels are mixed.
030 and TAF7; the packet configuration at 1031 is shown. The VCCD lengths 1040 and 1041 corresponding to one image have four VCCD electrodes 1042 as shown in the figure. In the present embodiment, since eight-phase driving is used, a two-pixel unit (eight VCCDs in total)
) Can be driven independently of each other.
As a result, there are six packets of signal charge packets 1015 during signal charge transfer. On the other hand, as shown in FIG. 47, in the conventional transfer method, V
CCD; 2220; VCCD equivalent to one pixel; VCCD electrodes of 2221;
In order to avoid mixing with adjacent signal charge packets at the time of signal charge transfer, the barrier during charge transfer; A group of signal charge packets; 2224 is two. Here, assuming that the area of the VCCD allocated to one pixel is S, the conventional CCD
In this case, 1 / 2S can be secured for signal charge transfer. In this regard, in the present invention, VC corresponding to one pixel
Assuming that the CD length is the same as the conventional one, 6 / 8S is used for signal charge transfer. As a result, in terms of the electrode area for forming the signal charge packet, the area can be increased 1.5 times as much as that of the related art, and as a result, the transferable signal charge amount also increases.

FIG. 30 shows an eight-phase drive pulse group (drive pulse φV1; 102) for enabling this charge transfer.
1, drive pulse φV2; 1022, drive pulse φV3;
1023, drive pulse φV4; 1024, drive pulse φ
V5; 1025, drive pulse φV6; 1026, drive pulse φV7; 1027, drive pulse φV8; 1028)
The timing charts of A-field and B-
In the field, TAF1; TAF1 from 1003
6; up to 1004 and TBF1; 1007 to TBF
1; the period up to 1008 is shown. Where V
H, 1100, VM; 1101, VL; 1102 are assumed to be supplied with, for example, 15 V, 0 V, and -8 V, but are not limited to such a ternary voltage and a binary voltage. It should be added that the signal charge transfer of FIG. 28 is feasible.

Next, referring to FIGS. 31, 32 and 33, the first
1 shows an embodiment.

FIG. 31 is shown in FIGS. An example of a time chart for performing two or more imaging operations with a long accumulation time and a short accumulation time in each field when a solid-state imaging device having an eight-phase electrode structure performs a read / transfer operation in a scanning mode conforming to NTSC. FIG. The purpose of this embodiment is to set two types of long and short storage times during an arbitrary frame period without using an external frame memory.
The object is to image a subject having low illuminance by long-time exposure, to image a subject having high illuminance by short-time exposure, and to estimate the amount of incident light on the subject from the exposure time and the signal charge amount extracted independently.

FIG. 32 shows an example of a read / transfer operation for mixing two pixels according to the time chart of FIG. On the left end, each pixel (pixel; 1230, pixel; 1231, pixel; 1) representing even-numbered rows and odd-numbered rows of the solid-state imaging device
232, pixel; 1233) and the transfer electrodes of the VCCD of each pixel and the eight-phase drive pulse (drive pulse φV1; 1241, drive pulse φV2; 124)
2, drive pulse φV3; 1243, drive pulse φV4;
1244, drive pulse φV5; 1245, drive pulse φ
V6; 1246, drive pulse φV7; 1247, drive pulse φV8; 1248). Also,
The flow of a series of signal charge transfer operations using signal charge packets started from the read operation of TAF1; 1203 is followed by TAF2 (here, every clock).
7; 3 clocks after 1205 are drawn.

Here, in the chart shown in the upper part of FIG. 31, the horizontal axis represents time, and the vertical axis represents A-field period;
1, a B-field period; 1206, a time change of a signal charge amount Qsig 1200 which is photoelectrically converted and accumulated in an arbitrary odd-numbered unit pixel represented by a pixel 1230 with respect to light incident on each of the pixels. In addition, in the lower chart of FIG. 31, pixels located in the next even-numbered row;
31, the signal charge amount Qsi photoelectrically converted and stored.
g; shows a time change of 1219. Hereinafter, for convenience,
A-field period; TAF1; 1203, which is the reading time of the signal charge in 1201, and B-field period; TBF1, which is the reading time of the signal charge in 1206; 1208, are set immediately after the V-blank period of each field. the description proceeds, however, the present onset
Akira It is emphasized that it is not particularly limited to immediately after the V- blank period each reading time.

In the pixel; 1230, TAF1; 1203
After reading out the first exposure period A; 1211 in TAF1 again during the same A-field period
4: At 1204, the second exposure period A; 1212 is read. Further, in this pixel; 1230, TAF1
4; Immediately after the reading in 1204 is completed, signal charge accumulation in the first exposure period B; 1213 for reading in the TBF 14; 1209 of the B-field starts. Here, the first exposure period B; 1213 corresponds to TBF1; 1208.
Are read at the timing of TBF 14; 1209 delayed by ΔT; 1217 from the first exposure period A;
The exposure period is longer by 2ΔT than 1211.

On the other hand, in the pixel 1231, the TAF 14;
After reading out the first exposure period A; 1211 in 1204, the TA is read again during the same A-field period.
In F27; 1205, reading of the second exposure period A; 1221 is performed. In addition, this pixel;
27; Immediately after the reading at 1205 is completed, signal charge accumulation in the first exposure period B; 1222 for reading at TBF1 1208 in the B-field starts. Here, the first exposure period B; 1222 corresponds to TBF1; 1208.
, The exposure period is shorter than the first exposure period A; 1211 by 2ΔT. As a result, a first exposure period B; 1213 and a first exposure period A;
1220, the first exposure period A; 1211 and the first exposure period B; 1222 have the same exposure time, but the first exposure period A; 1211 and the first exposure period B; Only the exposure time is different.

This means that ΔT is equal to the first exposure period A; 1
If it is short enough to be negligible compared to 211, there is no problem, but if it is large enough not to be ignored, it is necessary to virtually align the exposure periods through arithmetic processing for conversion at the time ratio of both.

Here, the second exposure time A; 1212, the second exposure time B; 1214, the second exposure time A; 122
1, the second exposure time B; 1223 are the same ΔT
Is set to have an exposure time of

The description will be made with reference to FIG. here,
A solid square indicates a signal charge readout; 1234, a hatched square indicates a signal charge packet; 1235, and a white square indicates a barrier; 1236.

First exposure period A of pixel 1230; 12
11 is read out to the vertical charge transfer means VCCD at the time of TAF1;
This signal is transferred in the VCCD to the position of the pixel; 1231. At the time of TAF14; 1204, the pixel;
When the signal charges obtained in the first exposure period A 1212 are read out, they are added and mixed in the VCCD.

On the other hand, the signal charges obtained during the second exposure period A;
At time 4, the signal is read out to the vertical charge transfer means VCCD, and this signal is transferred to the pixel;
The signal charges are transferred through the CD, and at the time of TAF 27; 1205, when the signal charges obtained in the second exposure period A; 1221 of the pixel 1231 are read out, they are added and mixed in the VCCD.

The same operation is repeated in B-field; 1206. This makes it possible to make the second exposure period uniform in each of the A-field and the B-field.

Here, the signal charge packets for the signal charges obtained in the first exposure period and the second exposure period are both set to two. However, the present invention is not limited to this number, and is not limited to one. Three or three and one
I'll add things that can be individual. ΔT; 121
5, ΔT; 1216, ΔT; 1217, ΔT; 1218
In FIG. 32, 13 clocks are described in terms of a reference clock. However, it is sufficiently possible to use a variable clock of 13 clocks or more without performing the transfer or by partially using the transfer in the reverse direction. It is emphasized that

FIG. 33 shows an eight-phase drive pulse group (drive pulse φV1; 124) for enabling this charge transfer.
1, drive pulse φV2; 1242, drive pulse φV3;
1243, drive pulse φV4; 1244, drive pulse φ
V5; 1245, drive pulse φV6; 1246, drive pulse φV7; 1247, drive pulse φV8; 1248)
The timing charts of A-field and B-
In the field, TAF1; TAF2 from 1203
7; 1205 after 3 clocks, and TBF1; 12
08 to TBF 27; the period from 1210 to 3 clocks later is shown. Here, VH; 1300, VM;
1301, VL;
Although it is assumed that 0 V and -8 V are supplied, it is added that the signal charge transfer shown in FIG. 32 can be realized without the ternary voltage limited as described above.

Further, a first exposure period A; 1211, 1220 in the A-field, and a V-blank; 120
The second exposure period A during the two periods;
The former is about 240 in terms of the number of horizontal scanning lines, and the latter is about 20. Therefore, the feasible exposure time ratio is about 8% or less.

Next, referring to FIGS. 34, 35 and 36, the first
2 shows an embodiment.

FIG. 34 shows a driving method for aligning the first exposure period A; 1411 and the first exposure period B; 1413 in A-field and B-field in FIGS. It is. The object of the present embodiment is to capture an object having low illuminance by long exposure and increase by short exposure when long and short accumulation times can be set during an arbitrary frame period without using an external frame memory. Image a subject with illuminance,
In order to be able to estimate the amount of incident light on the object from the signal charge amount extracted independently of the exposure time, two long and short exposure periods during the A-field period and two short and long exposure periods during the B-field period are respectively set. Alignment makes it easier to perform later signal processing. In FIG. 35,
An example of a read / transfer operation for performing two-pixel mixing according to the time chart shown in FIG. 34 will be described. At the left end, each pixel (pixel; 14) representing even and odd rows of the solid-state imaging device
30, pixel; 1431, pixel; 1432, pixel; 143
3) and the transfer electrodes of the VCCD of each pixel and the eight-phase drive pulse (drive pulse φV1;
41, drive pulse φV2; 1442, drive pulse φV
3, 1443, drive pulse φV4, 1444, drive pulse φV5, 1445, drive pulse φV6, 1446, drive pulse φV7, 1447, drive pulse φV8, 144.
8) is schematically shown. Here, TAF1; 14
The flow of a series of signal charge transfer operations using signal charge packets starting from the read operation of No. 03 is described with time (here, every clock) up to three clocks after TAF27; 1405.

Here, in the chart shown in the upper part of FIG. 34, the horizontal axis represents time, and the vertical axis represents A-field period;
1, a B-field period; a pixel for light incident during each period of 1406; a signal charge amount Qsig photoelectrically converted and accumulated in an arbitrary odd-numbered unit pixel represented by 1430; Is shown. Also,
The lower chart of FIG. 34 shows a temporal change in the signal charge amount Qsig; 1419 photoelectrically converted and accumulated in the pixel 1431 located in the next even-numbered row. Less than,
For convenience, TAF1 which is the reading time of the signal charge in the A-field period; 1401;
TBF1; 1408, which is the signal charge readout time in the field period;
Although the description will be made assuming that the read time is set immediately after the blank period, it is emphasized that the present invention does not limit each read time particularly immediately after the V-blank period.

In the pixel; 1430, TAF1; 1403
After the reading of the first exposure period A; 1411 is performed, the TAF1 is again read during the same A-field period.
At 4404, the second exposure period A; 1412 is read. Further, in this pixel; 1430, TAF1
4; Immediately after the reading at 1404 is completed, signal charge accumulation in the first exposure period B; 1413 for reading at TBF1 of the B-field; 1408 starts. here,
Since the first exposure period B; 1413 is read at the timing of TBF1; 1408, the first exposure period A;
The same exposure period as 411 can be obtained.

On the other hand, in the pixel 1431, the TAF 14;
After reading out the first exposure period A; 1411 at 1404, the TA is again read during the same A-field period.
In F27; 1405, the second exposure period A; 1421 is read. Further, in this pixel;
27; the TBF of the B-field 14 immediately after the reading at 1405 is completed;
Of the exposure period B; 1422 starts. Here, the first exposure period B; 1422 corresponds to the TBF 14;
Since the data is read at the timing of No. 9, the same exposure period as the first exposure period A; 1411 can be obtained.
As a result, the first exposure period B; 1413, the first exposure period A; 1420, the first exposure period A; 1411, and the first exposure period B; 1422 have the same exposure time.

Further, here, the second exposure time A;
12, the second exposure time B; 1414, the second exposure time A; 1421, and the second exposure time B; 1423 are each set to have the same exposure time ΔT.

The description will be made with reference to FIG. here,
A black square indicates a signal charge readout; 1434, a hatched square indicates a signal charge packet; 1435, and a white square indicates a barrier; 1436.

In the A-field; 1401, the signal charge obtained in the first exposure period A; 1411 of the pixel 1432 is read out to the vertical charge transfer means VCCD at the time of TAF1; The signal is transferred in the reverse direction through the VCCD to the position of pixel; 1431. Then, at the time of TAF14; 1404, the pixel;
When the signal charges obtained from 431 during the first exposure period A; 1420 are read, the two signal charges are added and mixed in the VCCD.

On the other hand, the signal charge obtained in the second exposure period A; 1412 of the pixel 1432 is the TAF 14;
At time 4, the signal is read out to the vertical charge transfer means VCCD, and this signal is transferred to the pixel;
It is transferred in the reverse direction in the CD. And TAF27; 1
At time 405, when the signal charges obtained in the second exposure period A; 1421 from the pixel 1431 are read out, the two signal charges are added and mixed in the VCCD.
Forwarded.

Similarly, in the B-field; 1406, the signal charge obtained in the first exposure period B; 1413 of the pixel 1430 is read by the CCDC as the vertical charge transfer means at the time of TBF1; 1408. This signal is forwarded in the VCCD to pixel 1431. And at the time of TBF14; 1409,
When the signal charges obtained in the first exposure period B; 1422 from the pixel 1431 are read out, the signal charges of both are VC
It is added and mixed in the CD.

On the other hand, the signal charge obtained during the second exposure period B; 1414 of the pixel 1430 is the TBF 14;
At time 9, the signal is read out to the vertical charge transfer means VCCD, and this signal is transferred to the pixel;
It is forwarded in the CD. And TBF27; 1
At time 410, when the signal charges obtained from the pixel 1431 to the second exposure period B; 1423 are read, the two signal charges are added and mixed in the VCCD. The signal charge read out to the VCCD in the B-field is thereafter
The transfer is performed in the reverse direction until TBF 43; 1425, from which the forward transfer is started. Hereinafter, the same operation is repeated for each field.

As a result, in each of the A-field and the B-field, TAF1;
F43; 43 clock period of 1424 and TBF1; 14
In the 43 clock periods from 08 to TBF 43; 1425, the temporal alignment of the order of readout and readout rows is performed, so that the first exposure period and the second exposure period can all be equalized.

In this case, the signal charge packets for the signal charges obtained in the first exposure period and the second exposure period are both set to two. However, the present invention is not particularly limited to this number, and one signal charge packet is used. Three or three and one
I'll add things that are good for individuals. ΔT; 141
5, ΔT; 1416, ΔT; 1417, ΔT; 1418
In FIG. 35, although 13 clocks are described in terms of the reference clock, it is sufficiently possible without limiting to 13 clocks by not performing the transfer or partially using the reverse transfer. Is emphasized. Also,
The timing to enter the forward transfer is TAF43; 1424
In the TBF 43; 1425, the reference clock is converted to the 43rd clock from the first read. However, it is needless to say that the present invention can be realized without being limited to the 43 clock.

FIG. 36 shows an eight-phase drive pulse group (drive pulse φV1; 144) for enabling this charge transfer.
1, drive pulse φV2; 1442, drive pulse φV3;
1443, drive pulse φV4; 1444, drive pulse φ
V5; 1445, drive pulse φV6; 1446, drive pulse φV7; 1447, drive pulse φV8; 1448)
The timing charts of A-field and B-
In the field, TAF1; TAF2 from 1403
7; 3405 after 1405, and TBF1; 14
08 to TBF 27; the period from 1410 to 3 clocks later is shown. Here, VH; 1500, VM;
For example, the voltage of 1501, VL;
Although it is assumed that 0 V and -8 V are supplied, it should be added that the signal charge transfer shown in FIG. 35 can be realized without using such a limited ternary voltage.

Next, a thirteenth embodiment will be described with reference to FIGS.

FIGS. 37 and 38 show FIGS. 9, 10, 11, and 12, respectively.
3 shows an example of a two-dimensional solid-state imaging device in which the element structure shown in FIG. At the time of mixed reading of each ND, in the A-field, the readout gate used as the separation unit by the applied voltage (for example, 0 V) is used in the B-field.
By setting an applied voltage (for example, 15 V), by using as a read gate for mixing and reading signal charges in two adjacent photoelectric conversion units,
The vertical resolution is improved.

FIG. 37 is a top view of a solid-state imaging device formed in a two-dimensional array. A part of the device is drawn toward the lower right so that the structure inside can be easily seen. The components are first layer polysilicon; 1601, second layer polysilicon;
1602, PD; 1620, PD; 1621, PD; 1
622, PD; 1623, PD; 1624, PD; 16
25, PD; 1626, read gate (formed by first and second layer polysilicon gates); 1604, read channel (here, N layer) formed in the semiconductor below the read gate; 1605, P layer for preventing signal charges from erroneously flowing into the VCCD of the unit pixel adjacent in the horizontal direction; 1606, VCCD
A P layer for defining a transfer channel region of
VCCD for transferring signal charges in the direction of the arrow; 16
08. A unit pixel; 1600 is indicated by an area indicated by a chain line. To drive this two-dimensionally arrayed solid-state imaging device, a driving pulse φV1;
1, drive pulse φV2; 1612, drive pulse φV3;
1613, drive pulse φV4; 1614, drive pulse φ
V5; 1615, a drive pulse φV6; 1616, a drive pulse φV7; 1617, and a drive pulse φV8;

FIG. 38 is a bird's-eye view of the solid-state imaging device formed into a two-dimensional array. Part of the structure is drawn downward in the figure to make it easier to see the structure inside. Form of this implementation
In the embodiment, as described above, the read gate structure shown in FIGS. 9, 10, 11, and 12 is employed, but the read gate structure shown in FIGS. 13 to 16, FIGS. 17 to 20, and FIGS. Needless to say, a pixel structure can be used.

Next, referring to FIGS. 39, 40 and 41, the first
A fourth embodiment will be described.

FIGS. 39 and 40 show signal charge transfer diagrams, and FIGS.
Shows a timing chart.
Shows an example of a signal charge read / transfer operation of a solid-state imaging device having an eight-phase electrode structure.

FIG. 39 is a diagram showing a time chart when the solid-state imaging device having the eight-phase electrode structure shown in FIGS. 37 and 38 performs a read / transfer operation in a scanning mode conforming to NTSC. In the figure, the horizontal axis represents time, and the vertical axis represents an A-field period; 1701 and a B-field period;
5 shows a signal charge amount Qsig; Here, an A-field period; TAF1, which is a signal charge readout time in 1701, and a B-field period;
TBF, which is the signal charge readout time at 705
1; 1707 is assumed to be set immediately after entering the V-blank period in each field, but it should be emphasized that the present invention does not particularly limit the read time.

FIG. 40 shows an example of a read / transfer operation for mixing two pixels. At the left end, an eight-phase drive pulse (φV1; 17) applied to the transfer electrode of the VCCD of each pixel
11, φV2; 1712, φV3; 1713, φV4;
1714, φV5; 1715, φV6; 1716, φV
7; 1717, φV8; 1718), and TAF1;
The flow of a series of signal charge transfer operations using signal charge packets started from the read operation of 1703 is followed by time (here, every clock), and the TAF 21;
It is schematically drawn until the time of.

In FIG. 40, black squares indicate signal charge readout; 1720, hatched squares indicate signal charge packets;
1721, a white square indicates a barrier; 1722. A-field shown on the left; TAF1; 1 at 1701
In the read operation of 703, PD;
The signal charges of D; 1621, PD; 1622 and PD; 1623 are mixed respectively, and in the B-field; 1705 shown on the right side of FIG. 40, PD; 1621 and PD;
2. The operation of mixing the signal charges of PD; 1623 and PD; 1624 is executed.

FIG. 41 shows an eight-phase drive pulse group (φV1; 1711, φV2; 1712, φV) for enabling mixing of signal charges in the pixel and subsequent charge transfer.
3: 1713, φV4; 1714, φV5; 1715,
φV6; 1716, φV7; 1717, φV8; 171
8) The timing chart of A-field,
In the B-field, TAF1;
F16; 1704 and TBF1; 1707 to TB
The period from F16 to 1708 is shown. here,
It is assumed that, for example, 15 V, 0 V, and -8 V are supplied to the voltages VH; 1800, VM; 1801, and VL; 1802, but the voltages are not limited to such ternary voltages and binary voltages. It should be added that the signal charge transfer shown in FIG. 40 is feasible.

Next, referring to FIG. 42, FIG. 43 and FIG.
A fifth embodiment will be described.

FIGS. 42 and 43 show signal charge transfer diagrams, and FIGS.
2 shows a timing chart, and shows an example of a signal charge read / transfer operation of the solid-state imaging device in which the VCCD of the pixel portion has an eight-phase electrode structure.

FIG. 42 is a diagram showing a time chart when the solid-state imaging device having the eight-phase electrode structure shown in FIGS. 37 and 38 performs a read / transfer operation in a scanning mode conforming to NTSC. The upper part of the figure shows the time change of the signal charge amount Qsig; 1900 accumulated in the photoelectric conversion units located in odd rows represented by PD; 1960, and the lower part of PD;
1901 shows a time change of the signal charge amount Qsig; 1901 stored in the photoelectric conversion unit located in the even-numbered row represented by 1961. Here, the horizontal axis represents time, and the vertical axis represents an A-field period; 1902 and a B-field period; 1904, the amount of signal charge photoelectrically converted and accumulated in each PD. First, the first part of each field,
ΔT from TBFE; 1906 to TAFS; 1908
-Shut; period of 1907 and TAFE; 191
ΔT-shut from 3 to TBFS; 1915; 19
14, a signal charge sweeping operation period in the substrate direction using a known (VOD; Vertical Overflow Drain) structure, an electronic shutter period A; 1920, an electronic shutter period A; 1930, an electronic shutter period B; 1924, an electronic shutter Period B; 1934 is provided, and the signal charges stored in the PD are swept simultaneously toward the substrate.

Subsequently, the first exposure period A; 1921, the first
Exposure period A; 1931, first exposure period B; 192
5. The signal charge in the first exposure period B; 1935 is T
AF1; 1910 and TBF1: read at 1917. This accumulation period is represented by ΔT−
st; 1909 and ΔT-st; 1916. The signal charges accumulated in the second exposure period A; 1932 and the second exposure period B;
9; 1911 and TBF 9; Rejection period A; 1923, Rejection period A; 1
933, rejection period B; 1927, rejection period B; 1937
The signal charge accumulated in the above is swept toward the substrate by the above-described electronic shutter operation. Here, TAF1 which is the signal charge readout time in the A-field period 1902; 1910 and the B-field period 19
TBF1, which is the signal charge readout time at 04;
Although 1917 is described as being set immediately after entering the V-blank period in each field, it is emphasized that the present invention does not particularly limit the read time.

A series of operations described in FIG. 42 will be described in more detail with reference to FIG.

FIG. 43 shows an example of a read / transfer operation for mixing two pixels.

On the left end, an eight-phase driving pulse (φV1; 1951, applied to the transfer electrode of the VCCD of each pixel)
φV2; 1952, φV3; 1953, φV4; 195
4, φV5; 1955, φV6; 1956, φV7; 1
957, φV8; 1958), and TAF1;
A flow of a series of signal charge transfer operations using a signal charge packet starting from a read operation of 0 is described with time (here, every clock) until a time after 16 clocks.

In FIG. 43, a black square represents signal charge readout; 1967, and a hatched square is a signal charge packet;
1968, open squares indicate barrier; 1969. A-field shown on left; TAF1; 1 in 1902
In the read operation of 910, four consecutive PDs
Are read out simultaneously as a set. For example, PD; 1
960 and PD; 1961 and PD; 1962 and PD; 19
63 are read simultaneously as one unit. In the subsequent read operation of TAF9; 1911, every two consecutive PDs are read simultaneously as one set. For example, PD; 1961, PD; 196
2 are read simultaneously as one unit. At this time, PD that was not read; 1960, PD; 196
The signal charge of No. 3 is swept toward the substrate by the electronic shutter operation performed at the beginning of the B-field period; 1904.

In the B-field; 1904 shown on the right side, at the time of the read operation of the TBF1; 1917, four consecutive PDs are read simultaneously as a set. For example, PD; 1962 and PD; 1963 and PD; 196
4 and PD; 1965 are read simultaneously as one unit. In the read operation of the following TBF 9; 1918, every two consecutive PDs are read simultaneously as one set. For example, PD; 196
3, PD; 1964 are read simultaneously as one unit. At this time, the PD that was not read; 196
1, PD; signal charge of 1962 is B-field period;
It is swept toward the substrate by an electronic shutter operation performed at the beginning of 1904.

FIG. 44 shows an eight-phase driving pulse group (φV1; 1951, φV2; 1952, φV) for enabling mixing of signal charges in the pixel and subsequent charge transfer.
3, 1953, φV4; 1954, φV5; 1955,
φV6; 1956, φV7; 1957, φV8; 195
8) The timing chart of A-field,
In the B-field, TAF1; 1910 to 16
It is shown in the period up to after the clock and the period from TBF1; 1917 to 16 clocks later. Here, VH; 200
It is assumed that, for example, 15 V, 0 V, and -8 V are supplied to the voltages of 0, VM; 2001, and VL; 2002. However, the voltage is not limited to such a ternary voltage and a binary voltage. It is added that the signal charge transfer described in (1) is feasible.

It should be emphasized in this embodiment that the device structure of this embodiment can be used.
That is, it is possible to simultaneously read out the stored charge in the first exposure period and read out the stored charge in the second exposure period in terms of time.

Further, since both the periods ΔT; 1940 and ΔT; 1942 corresponding to the second exposure period A; 1932 and the second exposure period B; 1926 can be changed, ΔT in the A-field and the B-field can be changed. -Shu
While changing t; 1907 and ΔT-shut; 1914, the second exposure period A; 1932 and the second exposure period B;
The period of both ΔT; 1940 and ΔT; 1942 corresponding to 1926 can be changed. Further, here, in the A-field, ΔT-shut; 190
7, the first exposure period A; 1921 and 1
It is also possible to independently change only the period of ΔT-st; 1909 corresponding to 931 and to keep the second exposure period A; 1932 constant. ΔT-st corresponding to 1931; 19
09 and the second exposure period A; ΔT corresponding to 1932; 1
It is also possible to adjust the total exposure period of ΔT-st and ΔT while keeping the ratio of 940 constant. It goes without saying that the same treatment can be performed in the B-field in either case.

Further, the electronic shutter periods A; 1920 and 1930 and the electronic shutter periods B; 1924 and 1935 in the present embodiment can be implemented in the embodiments represented by FIG. 31, FIG. 34 and FIG. It goes without saying that there is something. When an image input device is configured using this embodiment, a mechanical diaphragm mechanism can be eliminated, and a portable TV phone, an in-vehicle camera, an artificial eye, an endoscope, and the like, which are excellent in low power consumption and shock resistance. ,
It goes without saying that the present invention can be applied to an electronic still camera, an image input terminal to a personal computer, and the like.

Next, a sixteenth embodiment will be described with reference to FIG. In FIG. 45 , the driving methods shown in FIGS . 27 to 44 can be adopted.
The solid-state imaging device of this embodiment represented by 8; 2100
And first exposure period A; 1211, 1220, 141
1, 1420, 1921, 1931, second exposure period A; 1212, 1221, 1412, 1421, 193
2. First exposure period B; 1213, 1222, 141
3, 1422, 1925, 1935, second exposure period B; 1214, 1223, 1414, 1423, 192
A counter / timer section 2101 for setting an exposure period such as 6 is shown. Through 2103, the signal output line; timer output line count value or the timer value for setting the respective exposure periods represented by over 21
An external device for processing or recording the video signal transferred through the external device 04; passed to the external device 2102 so that the incident light intensity can be inversely estimated using the count value or the timer value. Can be easily performed. When an image input device is configured using this embodiment, a mechanical diaphragm mechanism can be eliminated, and a portable TV phone, an in-vehicle camera, an artificial eye, an endoscope, and the like, which are excellent in low power consumption and shock resistance. Needless to say, the present invention can be applied to an electronic still camera, an image input terminal to a personal computer, and the like.

[0118]

As described above, in the present invention, the transfer of signal charges is facilitated, and the range of the amount of light to be handled is extended to the high illuminance side.

[Brief description of the drawings]

FIG. 1 is a top view of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a top view of the solid-state imaging device according to the embodiment of the present invention;

FIG. 3 is a sectional view of a unit pixel in a vertical direction according to the embodiment of the present invention;

FIG. 4 is a sectional view of a unit pixel at a depth of X1-X1 ′ in FIG. 3;

FIG. 5 is a potential distribution diagram of a unit pixel according to an embodiment of the present invention.

FIG. 6 is a sectional view of a unit pixel in a vertical direction according to the embodiment of the present invention;

FIG. 7 is a sectional view of a unit pixel at a depth of X2-X2 ′ in FIG. 6;

FIG. 8 is a potential distribution diagram of a unit pixel according to an embodiment of the present invention.

FIG. 9 is a sectional view of a unit pixel in a vertical direction according to an embodiment of the present invention.

FIG. 10 is a sectional view of a unit pixel at a depth of X3-X3 ′ in FIG. 9;

FIG. 11 is a perspective view of a unit pixel according to an embodiment of the present invention.

FIG. 12 is a potential distribution diagram of a unit pixel according to an embodiment of the present invention.

FIG. 13 is a sectional view of a unit pixel in a vertical direction according to an embodiment of the present invention.

FIG. 14 is a unit pixel cross-sectional view at a depth of X4-X4 ′ in FIG. 13;

FIG. 15 is a perspective view of a unit pixel according to an embodiment of the present invention.

FIG. 16 is a potential distribution diagram of a unit pixel according to an embodiment of the present invention.

FIG. 17 is a sectional view of a unit pixel in a vertical direction according to an embodiment of the present invention.

18 is a sectional view of a unit pixel at a depth of X5-X5 ′ in FIG. 17;

FIG. 19 is a perspective view of a unit pixel according to an embodiment of the present invention.

FIG. 20 is a potential distribution diagram of a unit pixel according to an embodiment of the present invention.

FIG. 21 is a unit pixel cross-sectional view in a vertical direction according to an embodiment of the present invention.

22 is a sectional view of a unit pixel at a depth of X6-X6 ′ in FIG. 21;

FIG. 23 is a perspective view of a unit pixel according to an embodiment of the present invention.

FIG. 24 is a potential distribution diagram of a unit pixel according to an embodiment of the present invention.

FIG. 25 is a top view of the solid-state imaging device according to one embodiment of the present invention;

FIG. 26 is a perspective view of a solid-state imaging device according to an embodiment of the present invention.

FIG. 27 is a diagram showing a temporal change of a stored signal charge according to the embodiment of the present invention

FIG. 28 is a signal charge transfer chart according to one embodiment of the present invention.

FIG. 29 is a charge packet diagram according to an embodiment of the present invention.

FIG. 30 is a timing chart of one embodiment of the present invention.

FIG. 31 shows a change with time of an accumulated signal charge according to an embodiment of the present invention.

FIG. 32 is a signal charge transfer chart according to an embodiment of the present invention.

FIG. 33 is a timing chart according to an embodiment of the present invention.

FIG. 34 is a diagram showing a change over time of a stored signal charge according to an embodiment of the present invention.

FIG. 35 is a signal charge transfer chart according to an embodiment of the present invention.

FIG. 36 is a timing chart according to an embodiment of the present invention.

FIG. 37 is a top view of the solid-state imaging device according to an embodiment of the present invention;

FIG. 38 is a perspective view of a solid-state imaging device according to an embodiment of the present invention.

FIG. 39 is a diagram showing a change over time of an accumulated signal charge according to an embodiment of the present invention.

FIG. 40 is a signal charge transfer chart according to one embodiment of the present invention.

FIG. 41 is a timing chart of one embodiment of the present invention.

FIG. 42 is a diagram showing a change over time of a stored signal charge according to an embodiment of the present invention.

FIG. 43 is a signal charge transfer chart of one embodiment of the present invention.

FIG. 44 is a timing chart of one embodiment of the present invention.

FIG. 45 is a configuration diagram of a solid-state imaging device according to an embodiment of the present invention.

FIG. 46 is a top view of the solid-state imaging device according to an embodiment of the present invention;

FIG. 47 is a charge packet diagram according to an embodiment of the present invention.

[Explanation of symbols]

(Photo Diode) PD; 2200, 105, 106, 205, 206, 220, 221, 90
3, 1603, 1620, 1621, 1622, 1623, 1624, 1625, 1626, 1960, 196
1, 1962, 1963, 1964, 1965, 1966 V pitch: 2205, 109, 209, 300, 400, 500, 600, 700, 800 VCCD; 2201, 100, 200, 908, 1608 Read gate: 904, 2204, 107 , 207, 208, 1604 Read channel; 905, 1605 Read gate width; 2206, 110, 210 First layer polysilicon; 101, 102, 201, 202, 302, 402, 502, 60
2, 702, 802, 901, 1601, 2202 Second layer polysilicon; 103, 104, 203, 204, 303, 403, 503, 60
3, 703, 803, 902, 1602, 2203 Drive pulse φV1; 2211, 111, 211, 911, 1021, 1241, 1441,
1611, 1711, 1951 Drive pulse φV2; 2212, 112, 212, 912, 1022, 1242, 1442,
1612, 1712, 1952 Drive pulse φV3; 2213, 113, 213, 913, 1023, 1243, 1443,
1613, 1713, 1953 Drive pulse φV4; 2214, 114, 214, 914, 1024, 1244, 1444,
1614, 1714, 1954 Drive pulse φV5; 115, 215, 915, 1025, 1245, 1445, 1615,
1715, 1955 drive pulse φV6; 116, 216, 916, 1026, 1246, 1446, 1616,
1716, 1956 drive pulse φV7; 117, 217, 917, 1027, 1247, 1447, 1617,
1717, 1957 drive pulse φV8; 118, 218, 918, 1028, 1248, 1448, 1618,
1718, 1958 unit pixel; 120, 223, 900, 1010, 1011, 1012, 1013, 1230, 123
1, 1232, 1233, 1430, 1431, 1432, 1433, 1600 VCCD length equivalent to one image; 1040, 1041, 2220, 2221 oxide film; 304, 404, 504, 604, 704, 804 Vertical separation unit; 108 photoelectric conversion Area; 301, 401, 502, 601, 701, 801 first N layer; 305, 405, 505, 605, 705, 805 second N layer; 306 third N layer; 307 fourth N layer; 308, 406, 506, 606, 706, 806 Fifth N layer; 309, 407, 507, 607, 707, 807 Seventh N layer; 709 Signal charge; 310, 408, 509, 609, 710, 810P Layers: 508, 608, 708, 906, 907, 1606, 1607 Signal charge Qsig; 1000, 1200, 1219, 1400, 1419, 1700,
1900, 1901 signal charge readout; 1014, 1234, 1434, 1720, 1967 signal charge packet; 1015, 2224, 1235, 1435, 1721, 1968 barrier; 1016, 2223, 1236, 1436, 1722, 1969 VCCD electrode; 1042, 2222 A-field period; 1001, 1201, 1401, 1701, 1902 B-field period; 1005, 1206, 1406, 1705, 1904 TAF1; 1003, 1203, 1403, 1703, 1910 TAF5; 1030 TAF7; 1031 TAF9; 1911 TAF14; 1004, 1704 TAF27; 1205, 1405 TAF43; 1424 TBF1; 1007, 1208, 1408, 1707, 1917 TBF9; 1918 TBF14; 1209, 1409 TBF16; 1708 TBF27; 1210, 1410 TBF43; TAFE; 1913 TBFS; 1915 VH; 1100, 1300, 1500, 1800, 2000 VM; 1101, 1301, 1501, 1801, 2001 VL; 1102, 1302, 1502, 1802, 2002 ΔT; 1215, 1216, 1217, 1218, 1415 , 1416, 1417 1418,194
0, 1942 First exposure period A; 1211, 1220, 1411, 1420, 1921, 1931 First exposure period B; 1213, 1222, 1413, 1422, 1925, 1935 Second exposure time A; 1212, 1221, 1412, 1421, 1932 Second exposure time B; 1214, 1223, 1414, 1423, 1926 Rejection period A; 1923, 1933 Rejection period B; 1927, 1937 ΔT-shut; 1907, 1914 ΔT-st; 1909, 1916 electrons Shutter period A; 1920, 1930 electronic shutter period B; 1924, 1934 solid-state imaging device; 2100 counter / timer section; 2101 external device; 2102 timer value output line; 2103 signal output line;

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takao Kuroda 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Yuji Matsuda 1006 Kadoma Kadoma, Kadoma City Osaka Pref. (56) References JP-A-64-37869 (JP, A) JP-A-7-15672 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/30-5 / 335

Claims (18)

(57) [Claims] A plurality of unit pixels arranged in a one-dimensional direction in a Y direction or a two-dimensional direction in an XY direction are provided for converting electromagnetic waves or X-rays incident on the unit pixels into signal charges. A solid-state imaging device, comprising: a photoelectric conversion unit containing at least one or more impurities; and a charge transfer unit that is adjacent to the photoelectric conversion unit in the X direction and transfers the signal charge in the Y direction. In the boundary between the photoelectric conversion units adjacent to each other in the Y direction in the first means, a separation function for separating the photoelectric conversion units from each other and a reading function for reading out signal charges from the photoelectric conversion units to the charge conversion unit are also used. the provided, the first means, the upper, at least one or more electrodes
Is formed and has a semiconductor portion at the bottom.
The semiconductor unit of the first means is provided in the charge transfer means.
A solid-state imaging device having a gradient in a concentration distribution of an impurity in a direction toward the solid-state imaging device. 2. The method according to claim 1, wherein at least one unit pixel is provided for converting electromagnetic waves or X-rays incident on the unit pixel into signal charges.
A photoelectric conversion unit containing a first impurity, and X
And a charge transfer means for transferring the signal charges in the Y direction, wherein the unit pixels are arranged in the one-dimensional direction in the Y direction or the two-dimensional direction in the XY direction. At a boundary between the photoelectric conversion units adjacent to each other in the Y direction, a separating unit for separating the photoelectric conversion units from each other, and a reading unit for reading out signal charges from the photoelectric conversion units to the charge transfer unit are provided every other Y direction. The separation means or the readout means is constituted by a concentration gradient due to impurities, and the readout means is provided at the top with at least one or more electrodes.
It has poles and has a semiconductor part underneath.
The semiconductor portion of the readout means is the charge transfer means
Has a gradient in the impurity concentration distribution in the direction toward
The solid-state imaging device, characterized in that that. 3. The gradient of the concentration distribution is such that the concentration distribution of the first impurity increases as approaching the charge transfer means, or the concentration distribution of the second impurity having a polarity opposite to that of the first impurity decreases. Having the structure of 1a, or
3. The solid-state imaging device according to claim 1 , wherein the solid-state imaging device has a 1b structure in which an impurity distribution changes from the first impurity to the first impurity. Gradient of 4. A concentration distribution of the semiconductor unit according to claim 2, characterized in that it is formed by ion implantation of at least twice, or three solid-state imaging device according. 5. The method according to claim 1, wherein the first and second photoelectric conversion units are located on both sides of the photoelectric conversion unit.
4. The solid-state imaging device according to claim 3 , wherein at least one of the semiconductor portions of the means is formed by at least two or more ion implantations. 6. At least one of the electrodes, at least one of a portion of an adjacent photoelectric conversion unit or the claims 1, characterized in that it is formed so as to cover the entire surface, or 2 solid-state imaging device according . 7. The solid-state imaging device according to claim 6 , wherein a voltage is applied to at least one or more of said electrodes by different driving pulses. 8. The semiconductor portion has at least one delta- or sector-shaped injection region of a P-type impurity, and the width of the delta- or sector-shape becomes narrower as approaching the charge transfer means. 7. The solid-state imaging device according to claim 6, comprising a first readout structure. 9. The semiconductor section has at least one delta- or sector-shaped implantation region of N-type impurities, and the width of the delta- or sector-shaped region increases as the position approaches the charge transfer means. The solid-state imaging device according to claim 6 , further comprising a second readout structure. 10. The semiconductor part has a third read structure in which one or both of the first impurity and the second impurity are formed by ion implantation at least once or more. The solid-state imaging device according to claim 6 . 11. At least one of said electrodes, according to claim characterized by having a broad the fourth reading structure as the width in the Y direction closer to the charge transfer unit of the Y-direction 6
The solid-state imaging device according to any one of the preceding claims. 12. The first, second, and third photoelectric conversion units provided continuously in the Y direction, and a boundary area between the first photoelectric conversion unit and the second photoelectric conversion unit or the first photoelectric conversion unit or the second photoelectric conversion unit. 9. The solid-state imaging device according to claim 8 , wherein the first readout structure is adopted in one of the boundary areas between the second photoelectric conversion unit and the third photoelectric conversion unit. 13. included in the unit pixels, the solid-state imaging device according to claim 1 or 2 transfer electrodes of the charge transfer means, characterized in that it is composed of four. 14. A different drive pulse is applied to each of a total of eight transfer electrodes of said charge transfer means included in two unit pixels continuous in the Y direction. 12. The solid-state imaging device according to item 11 . 15. The electric charge transfer means of two consecutive unit pixels, a maximum of 7 in the eight transfer electrodes.
12. The solid-state imaging device according to claim 11, wherein one signal charge transfer packet is provided below the continuous electrodes. 16. At least two or more signal charge transfer packets are provided for the charge transfer means of two consecutive unit pixels, and at least one signal charge transfer packet is provided between the two or more signal charge transfer packets. The solid-state imaging device according to claim 11 , wherein the potential barrier is provided. 17. A first signal charge packet and a second signal charge packet having a total of eight continuous transfer electrodes for said charge transfer means of a continuous unit pixel A and a continuous unit pixel B, The first signal charge packet includes a first signal charge A generated by the electromagnetic wave or the X-ray signal within the first storage time of the unit pixel A and a second storage time of the unit pixel B. The first signal charge B generated by the electromagnetic wave or the X-ray signal is added and mixed at different read timings, and the second signal charge packet further includes a third accumulation time of the unit pixel A. Within the second signal charge A generated by the electromagnetic wave or the X-ray signal and the electromagnetic wave or the X-ray signal within the fourth accumulation time of the unit pixel B. It made a second signal charge B also solid-state imaging device according to claim 13, wherein the transferred are added and mixed at different read timings from each other. 18. A first signal charge packet and a second signal charge packet having a total of eight continuous transfer electrodes for said charge transfer means of a continuous unit pixel A and a continuous unit pixel B, The first signal charge packet includes a first signal charge A generated by the electromagnetic wave or the X-ray signal within the first storage time of the unit pixel A and a second storage time of the unit pixel B. The first signal charge B generated by the electromagnetic wave or the X-ray signal is added and mixed at different read timings, and the second signal charge packet further includes a third accumulation time of the unit pixel A. Within the second signal charge A generated by the electromagnetic wave or the X-ray signal and the electromagnetic wave or the X-ray signal within the fourth accumulation time of the unit pixel B. Second signal charge B was made but also added and mixed at different read timings from each other,
A set of the first accumulation time and the second accumulation time;
Of the set of the third accumulation time and the fourth accumulation time,
14. The solid-state imaging device according to claim 13, wherein at least one pair has the same accumulation time.