JP3072264U - Computer peripherals - Google Patents

Abstract

(57) [Summary] An inexpensive configuration enables data from a host computer to be reliably received. When a data packet is transmitted from a personal computer to a USB block, the data is stored in a reception buffer of the USB block, an interrupt signal is output to an interrupt processing unit of an MPU, and the data is received by the interrupt processing unit. The data stored in the buffer is read and stored in the work RAM,
An event code having different bit contents corresponding to the storage status of each side of the reception buffer is output to the command analysis unit, the command analysis unit analyzes the command in the data stored in the work RAM, and performs a process according to the analysis result. Will be At this time, the event code from the interrupt processing unit is B
If the event is a plane event, a clear signal for permitting reception is output from the command analysis unit to the USB block, and both sides of the reception buffer are ready for reception.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 The present invention relates to a computer peripheral device having an interface conforming to the USB standard connected to a host computer.

[0002]

[Prior art]

 The connection between the host computer, which is a higher-level device, and its peripheral devices is usually performed via an interface device, and there is a standard called USB (Universal Serial Bus) as a standard for this type of interface device.

A printer as such a peripheral device usually includes a USB block having a multi-sided (here, described as two-sided) receiving buffer, and a microprocessor (hereinafter, referred to as an MPU) for performing various processes. When data packets such as various command data and print data are received via the USB port of the USB block transmitted from the host computer, the received data is transferred to each of the reception buffers of the USB block. Stored in the plane.

At this time, when the reception data is stored on one side of the reception buffer, the data is read out by the MPU, and when the reception data is stored on the remaining side of the reception buffer, the data is transmitted by the MPU. Is read.

In order to prevent data accumulated in the reception buffer from being erroneously destroyed when data is received using a multi-sided reception buffer cyclically, for example, Japanese Patent Application Laid-Open No. 58-170254 discloses As described, a storage unit is provided corresponding to each surface of the reception buffer to indicate the presence or absence of valid data in the reception buffer. When this storage unit is set, a new data is stored in the corresponding reception buffer surface. Prohibit unnecessary writing.

[0006] In this case, for example, new received data is accumulated on the second surface B while valid one frame data is stored in the first surface A reception buffer. When data is written to the A side again after receiving one frame of data, valid data remains on the A side if the display of the storage unit corresponding to the A side indicates "valid data available". Therefore, writing to the A side is prohibited, and new data is written to the A side on the condition that the display of the storage unit corresponding to the A side indicates "no valid data". Therefore, it is possible to prevent the data from being damaged by being overwritten while valid data remains on the side A.

[0007]

[Problems to be solved by the invention]

 However, in order to be described in the above-mentioned publication, if the display unit corresponding to each surface of the reception buffer indicates that “there is no valid data on that surface”, the surface is cleared ( For this purpose, it is necessary to generate a clear signal every time each side of the receiving buffer is cleared. For this purpose, the number of gates for generating the clear signal increases, which complicates the configuration of the entire device. There was a problem.

By the way, Japanese Patent Application Laid-Open No. 1-248731 discloses that if a certain number is held in the reception data buffer so that all of the plurality of reception data buffers do not hold the reception data, it is urgently required. Although it is described that data can always be received by processing, it is necessary to provide a large number of receive data buffers, which increases costs and does not mean that all of these receive data buffers can be used. Poor utilization efficiency

Japanese Patent Application Laid-Open No. 5-46516 discloses a processor that generates an interrupt level corresponding to the number of data stored in a reception buffer stored in a FIFO and receives an interrupt having the highest level. It describes a device that takes in data from a receiving buffer that performs the processing. Further, Japanese Patent Application Laid-Open No. Hei 5-224848 discloses a printing apparatus in which, when print data is transmitted from a plurality of computers at the same time, the print data is received in parallel by a plurality of buffer means. Although described, neither of the inventions described in these publications relates to control of a multi-sided reception buffer in USB.

Therefore, an object of the present invention is to make it possible to reliably receive data from a host computer with an inexpensive configuration.

[0011]

[Means for Solving the Problems]

 In order to achieve the above-mentioned object, the present invention provides a peripheral device of a computer having an interface conforming to the USB standard connected to a host computer, and sequentially receives data from the host computer from the first to the Nth. N (N is a natural number of 2 or more) receiving buffers, an interrupt generating unit that generates an interrupt signal each time the received data is stored in each of the receiving buffers, And a control unit for generating a clear signal for permitting reception in all the reception buffers after the N-th data storage in the reception buffers by the read generation unit is completed.

According to such a configuration, the clear signal is not generated until after the data storage in the N-th reception buffer is completed, so that the number of outputs of the clear signal can be reduced, and for example, the clear signal is not generated. The number of gates can be reduced, and the configuration can be simplified. In addition, the reception buffer is not permitted to receive the next data unless the data storage in the N-th reception buffer is completed. Therefore, the already stored reception buffer data is destroyed by overwriting. Can be prevented.

[0013] In the present invention, the control unit includes: an interrupt processing unit that reads out and processes data stored in the reception buffer every time the interrupt signal is input; A command analysis unit that analyzes the command in the read stored data and generates the clear signal after the analysis is completed.

According to such a configuration, the clear signal is generated from the control unit after the command analysis unit completes the analysis of the command in the data read from the Nth reception buffer.

In the present invention, the interrupt processing unit reads the stored data from each of the reception buffers and generates an event code having different code contents corresponding to each of the reception buffers. The command analyzer recognizes the code content of the event code output after reading the N-th storage data in the reception buffer and generates the clear signal.

According to such a configuration, the command analysis unit clears the event code output from the interrupt processing unit after storing the data in the N-th reception buffer, on condition that the command analysis unit recognizes the content of the event code. Since the signal is generated, the clear signal is not generated until after the data storage to the Nth reception buffer is completed. The number can be reduced, and the destruction of already received data can be prevented.

Further, the present invention is characterized in that the data transmitted from the host computer includes print data, and comprises a printer for printing characters, graphics, and the like based on the print data. According to such a configuration, it is possible to reliably receive and process data transmitted from the host computer without damaging the USB standard, thereby providing a highly reliable printer.

[0018]

[Embodiment of the invention]

 One embodiment in which the present invention is applied to a printer which is a computer peripheral device having an interface conforming to the USB standard will be described with reference to FIGS. 1 to 6. FIG. 1 is a block diagram, FIG. 2 is a partial block diagram, FIG. 3 is an operation explanatory diagram, FIG. 4 is a different partial block diagram, and FIGS. 5 and 6 are operational explanatory diagrams.

As shown in FIG. 1, a personal computer (hereinafter abbreviated as a personal computer) 1 as a host computer includes a USB block 2 and an MPU (microprocessor) 3 as a control unit. The printer is connected by a connector and a cable (both not shown) conforming to the USB standard.

The USB block 2 is composed of an ASIC, and as shown in FIG. 2, a receiving buffer 2a of 64 bytes per side, that is, a first side A side and a second side B side, and 2b, and receives and stores a data packet including command data and print data transmitted from the personal computer 1 via the USB port. Further, the USB block 2 is provided with a 4-byte (32-bit) status register that indicates which of the reception buffers 2a and 2b, A or B, stores the received data. As shown in FIG. 3, the 4-bit data contents from the 0th bit to the 3rd bit indicate the data storage state and the like of the reception buffers 2a and 2b on the A and B sides.

Specifically, the RNXT bit as the third bit indicates a reception buffer plane that can be received and stored next, and the RBS0 bit as the second bit is the reception plane in the A plane as the first plane. This bit indicates the storage state of the buffer 2a. If this bit content is "0", it indicates a state where no data is stored, and if "1", it indicates a state where data is stored.

The RBS1 bit, which is the first bit, indicates the storage state of the reception buffer 2b on the B surface, which is the second surface. If the bit content is “0”, no data is stored; If it is "1", it indicates a state where data is stored.

Further, the RCNT bit, which is the 0th bit, indicates to the personal computer 1 that the data packet from the personal computer 1 has been received with an ACK (response) packet. When a data packet is received from 1, an interrupt signal is output from the USB block 2 and the MPU 3 is interrupted. At the same time, the RCNT bit is set to "1". The process of generating an interrupt signal by the USB block 2 corresponds to an interrupt generation unit.

At this time, the MPU 3 reads out the data stored in the reception buffers 2a and 2b by interrupt processing based on the interrupt signal from the USB block 2, and particularly stores the data in the reception buffer 2b on the B plane which is the last plane. When the data reading is completed, a clear signal is output from the MPU 3 to the USB block 2, whereby the RBS0 bit as the second bit and the RBS1 bit as the first bit are cleared to "0", and the PC 1 It is in a reception permission state in which a new data packet can be received from.

Next, as shown in FIG. 4, each time an interrupt signal is input from the USB block 2, the MPU 3 sequentially reads data stored on each side of the reception buffer, and for example, a work RAM built in the MPU 3. (Not shown), an interrupt processing unit 3a that analyzes commands in the data stored in the work RAM by the interrupt processing unit 3a, performs processing in accordance with the analysis result, and terminates the analysis. A command analyzer 3b for generating a clear signal for permitting reception later.

When the interrupt signal from the USB block 2 is input, the interrupt processing unit 3a reads the status register of the USB block 2 described above, and based on the contents of the RBS0 bit and the RBS1 bit of the status register, It is determined which of the receiving buffers 2a and 2b of the A and B sides should read data.

For example, as shown in FIG. 5, if the RBS0 bit is “1” and the RBS1 bit is “0”, it can be understood that data is stored only on the A side, so that the interrupt processing unit 3a The data stored in the reception buffer 2a on the A side is read. Next, as shown in FIG. 5, the RBS0 bit is set to "1" and the RBS1 bit is set to "1" when the interrupt processing unit 3a reads the status register by the interrupt signal from the USB block 2. Then, since it is known that data is newly stored in the reception buffer 2b on the B side, the data stored in the reception buffer 2b on the B side is read out by the interrupt processing unit 3a.

At this time, even if the personal computer 1 transmits data such that the receiving blocks 2a and 2b on both sides are filled, the data is first stored in the buffer 2a on the A side, and then the B Since the data is stored in the buffer 2a on the A side, the RBS0 bit becomes “1” and the RBS1 bit becomes “0” when the data is stored on the buffer 2a on the A side. When the data is stored in the buffer 2b, the RBS0 bit and the RBS1 bit both become "1". Therefore, as described above, after the data stored in the reception buffer 2a on the side A is read by the interrupt processing unit 3a, the data stored in the reception buffer 2a on the side B is read.

Then, as shown in FIG. 5, when the interrupt processing unit 3a reads the data stored in the reception buffer 2a on the A side, the interrupt processing unit 3a reads the data stored in the reception buffer 2a on the A side. Is output to the command analysis unit 3b and the data stored in the reception buffer 2b on the side B is read out, indicating that the data stored in the reception buffer 2b on the side B has been read out. An event code having bit contents (B-side event in FIG. 5) is output to the command analysis unit 3b.

On the other hand, the command analyzing unit 3b analyzes the command in the data stored in the work RAM by the interrupt processing unit 3a as described above, and the event code (in FIG. 5) from the interrupt processing unit 3a. (A-side event and B-side event), the bit code of the event code indicates that it has read the data stored in the reception buffer 2b of the B-side (B-side event in FIG. 5). Only after recognizing that the RBS0 and RBS1 bits of the status register of the USB block 2 are cleared to "0", a clear signal is output. As a result, both reception buffers 2a and 2b of the USB block 2 can receive data from the personal computer 1.

Next, a series of operations of data reception in the printer will be described. Now, as shown in FIG. 6, when the first data packet (data 1 in FIG. 6) is transmitted from the personal computer 1 to the USB port of the USB block 2, the data 1 is transmitted to the A side of the USB block 2. While being stored in the reception buffer 2a, the RBS0 bit of the status register of the USB block 2 is set to "1", and an interrupt signal is output to the interrupt processing unit 3a of the MPU 3.

When an interrupt signal from the USB block 2 is input to the interrupt processing unit 3 a of the MPU 3, as shown in FIG. 6, the data stored in the reception buffer 2 a on the A side is output by the interrupt processing unit 3 a. Is read and stored in the work RAM, and an event code (A-side event in FIG. 5) having a bit content indicating that the data stored in the reception buffer 2a on the A-side has been read out is output to the command analyzer 3b. Is done.

Based on the A-side event, as shown in FIG. 6, a command in the data from the A-side receiving buffer 2a stored in the work RAM is analyzed by the command analysis unit 3b, and the analysis result is obtained. The corresponding processing is performed. At this time, since the event code received from the interrupt processing unit 3a is an A-side event, a clear signal for permitting reception is not output from the command analysis unit 3b to the USB block 2.

Subsequently, when the second data packet (data 2 in FIG. 6) is transmitted from the personal computer 1 to the USB port of the USB block 2, the data is stored in the reception buffer 2 a on the side A of the USB block 2. Is stored, the data 2 is stored in the reception buffer 2b on the B side in which no data is stored yet, the RBS1 bit of the status register of the USB block 2 is set to "1", and the MP2 An interrupt signal is output to the interrupt processing unit 3a of U3.

When an interrupt signal from the USB block 2 is input to the interrupt processing unit 3 a of the MPU 3, as shown in FIG. 6, the data stored in the reception buffer 2 b on the B side is transmitted by the interrupt processing unit 3 a. Is read and stored in the work RAM, and an event code (B-side event in FIG. 5) having a bit content indicating that the data stored in the reception buffer 2b on the B-side has been read out is output to the command analysis unit 3b. You.

Based on the B-side event, as shown in FIG. 6, a command in the data from the reception buffer 2b on the B-side stored in the work RAM is analyzed by the command analysis unit 3b. While the corresponding process is performed, the event code received from the interrupt processing unit 3a is recognized as a B-side event by the command analysis unit 3b. A clear signal is output, the RBS0 bit and the RBS1 bit of the status register of the USB block 2 are both cleared to "0", and the reception buffers 2a and 2b enter a reception permitting state in which data from the personal computer 1 can be received. .

Therefore, according to the above-described embodiment, since the clear signal is not generated from the command analyzing unit 3b until the data storage in the receiving buffer 2b on the side B is completed, the clear signal of the command analyzing unit 3b is not generated. The number of outputs is small, and as a result, the number of gates for generating a clear signal can be reduced, and the configuration can be simplified.

Also, unless the data is stored in the reception buffer 2b on the side B, reception is not permitted to receive the next data. For example, the reception buffer on the side A already stored The data of 2a can be prevented from being destroyed by overwriting.

In the above-described embodiment, the reception buffer of the USB block 2 is described as having two faces. However, the reception buffer is not particularly limited to two faces, and may be provided with three or more faces. I do not care.

In the above-described embodiment, a case has been described where the computer peripheral device is a printer. However, the peripheral device is not particularly limited to a printer, and may be a scanner or other computer peripheral devices. Of course it is good.

Further, the host computer is not limited to the personal computer 1 as described above.

The present invention is not limited to the above-described embodiment, and various changes other than those described above can be made without departing from the gist of the present invention.

[0043]

[Effect of the invention]

 As described above, according to the first aspect of the present invention, the clear signal is not generated until after the data storage in the N-th receiving buffer is completed. The number of gates for generating a clear signal can be reduced, and the configuration of the entire device can be simplified.

Further, the reception buffer is not permitted to receive the next data unless the data storage in the N-th reception buffer is completed. Can be reliably prevented from being destroyed by being overwritten.

According to the invention of claim 2, after the command analysis unit completes the analysis of the command in the data read from the N-th (last) reception buffer, a clear signal is sent from the control unit. Since it is generated, the number of gates for generating a clear signal can be reduced, and destruction of already received data can be prevented.

According to the invention, the command analysis unit recognizes the contents of the event code output from the interrupt processing unit after the data is stored in the N-th reception buffer. Since the clear signal is generated from the command analysis unit, the clear signal is not generated until after the data storage to the Nth reception buffer is completed, and the number of clear signal outputs is reduced to clear. The number of gates for signal generation can be reduced, and destruction of already received data can be prevented.

According to the invention of claim 4, data transmitted from the host computer can be reliably received and processed without being damaged in accordance with the USB standard, and reliability can be improved. It is possible to provide a high-quality printer.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a partial block diagram of one embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of one embodiment of the present invention.

FIG. 4 is a block diagram of a part of another embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of one embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of one embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 personal computer (host computer) 2 USB block (interrupt generating unit) 2a, 2b receiving buffer 3 MPU 3a interrupt processing unit 3b command analyzing unit

Claims (4)

[Utility model registration claims] 1. USB connected to a host computer
A peripheral device for a computer having an interface conforming to a standard, wherein N (N is a natural number of 2 or more) reception buffers for sequentially storing received data from the host computer from the first to the Nth; An interrupt generation unit for generating an interrupt signal each time the reception data is stored in each of the reception buffers; and all the receptions after the completion of the Nth data storage in the reception buffer by the interrupt generation unit. A control unit for generating a clear signal for permitting reception in a buffer. 2. The control unit includes: an interrupt processing unit configured to read and process data stored in the reception buffer every time the interrupt signal is input; 2. The computer peripheral device according to claim 1, further comprising: a command analysis unit that analyzes a command in the data and generates the clear signal after the analysis is completed. 3. The interrupt processing unit reads the stored data from each of the reception buffers, generates an event code having different code contents corresponding to each of the reception buffers, and the command analysis unit 3. The clear signal is generated by recognizing the code content of the event code output after the data stored in the reception buffer is read out.
A computer peripheral device according to claim 1. 4. The computer according to claim 1, wherein the data transmitted from the host computer includes print data, and comprises a printer that prints characters, graphics, and the like based on the print data. Peripheral devices.