JP3070058B2 - Digital signal processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital signal processor (DSP).

[Prior art and its problems] Digital signal processing devices are used to perform algebraic operations on digital signals to perform filtering, spectral analysis, and the like. Generally, high-speed processing is required, and real-time processing is required. Used in applications. One of basic operations in a digital signal processing device is a product-sum operation, in which a product operation (multiplication) is performed between a signal to be processed and a coefficient, and a sum operation (addition) is performed between intermediate signals. It is often said. In digital filter applications, signals form a time series. In the case of a digital signal processor operating in a microprogram, these coefficients and signals are stored in an arithmetic data memory (coefficient memory, signal memory) incorporated in the digital signal processor, and access to the arithmetic data memory is performed according to the microprogram. Is to be executed. Such a memory access is for an arithmetic operation, and is an internal access performed for the purpose of signal processing of the digital signal processing device.

In many applications, updating and checking computational data,
In order to collect the operation results, it is desirable that the operation data memory can be externally accessed. For this purpose, conventionally, the operation by the microprogram in the digital signal processing device has been interrupted, thereby opening the arithmetic data memory to the outside. As a result, during the interruption of the microprogram for external access, the signal processing has to be interrupted. In other words, such conventional schemes show no ability to change digital signal processing characteristics (e.g., filtering characteristics) on a real-time basis, and applications where interruption of real-time signal processing is unacceptable (e.g., This was a major constraint on electronic musical instrument sound effectors.

Accordingly, an object of the present invention is to provide a digital signal processing device capable of responding to an external memory access request without interrupting digital signal processing.

According to the present invention, there is provided a digital signal processing apparatus having an arithmetic circuit unit having an arithmetic data storage unit and a microprogram operation control circuit unit for controlling an arithmetic operation in the arithmetic circuit unit. An empty time slot defining means for defining, based on the microprogram, an empty time slot in which the arithmetic data storage means is not accessed as part of the arithmetic operation in response to an external access request to the arithmetic data storage means. And when there is an external access request to the operation data storage unit, the access according to the access request is made to the operation data storage unit in the empty time slot defined by the empty time slot definition unit. External access execution means for executing A digital signal processing device is provided.

According to this configuration, when the operation data storage unit is accessed (internal access) as part of the operation according to the microprogram, the access (external access) relating to the external access request is not performed, and the operation is performed based on the microprogram. The external access according to the external access request is executed for the arithmetic data storage means in an empty time slot when the defined arithmetic data storage means is not internally accessed, so that the collision between the internal access and the external access is avoided. In addition, it is possible to respond to an external access request without interrupting the digital signal processing determined by the arithmetic operation.

The calculation data storage means may include a time-series signal storage means for storing a time series of a signal (for example, a signal time series expressing sound) and a coefficient data storage means for storing coefficient data to be multiplied by the signal. In this connection, the external access execution unit executes execution of a write access to the time-series storage unit, execution of a read access, execution of a write access to the coefficient data storage unit, and execution of a read access from outside. It can be done selectively according to the type of request.

In one configuration example, the control circuit means includes a microprogram storage means for storing a microcode sequence as the microprogram, and a sequential repetitive read means for sequentially reading the microcode from the microprogram storage means and repeating the sequence Has,
When the microcode read by the sequential repetitive reading means includes a specific code, the specific code defines the empty time slot by the empty time slot defining means.

The specific code may be expressed by a specific value of a specific one bit in the microcode, or may be expressed by a specific logic function value of a plurality of specific bits in the microcode. Detection of a specific logic function value can be easily realized by gate circuit means.

The microprogram storage means can be realized by a ROM, a RAM, a logic gate circuit or a combination thereof.

In a case where the microprogram storage means is realized by a logic gate circuit or the like, and a relatively complicated digital signal processing is used, a part of a signal (for example, a branch condition signal) from the arithmetic circuit means is returned to the logic gate circuit. Alternatively, the microcode output from the logic gate circuit may be selectively changed by the signal. If the portion of the microcode indicating the empty time slot is changed by the signal to change to a microcode instructing internal access to the arithmetic data storage means, the empty time slot is deleted, and External access is not executed at the timing, but it is surely executed when the next empty time slot is secured. In such a configuration, the empty time slot also depends on the operation result in the operation circuit means.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a digital signal processor (DS) according to this embodiment.
3 shows the configuration of the control unit 100 of P).

The control unit 100 controls the arithmetic unit 200 shown in FIG. 2. The arithmetic unit 200 is, for example, a secondary I-type as shown in FIG.
Function as an IR digital filter. FIG. 3 shows the overall configuration of the system. As will be described later, an external access request from the external access device (CPU) 300 is transmitted to the control unit.
100 receives and executes the calculation operation in the calculation unit 200 without interruption. The purpose of the arithmetic unit 200 is to signal-process a time-series input (for example, a signal time-series representing sound) provided from the time-series generation unit 400 and output the processed signal.

 The signals transmitted and received for the device are as follows.

(A) Information sent from the external access device (CPU) 300 to the control unit 100 EXDI: External data input (bus). As a result, data and addresses are transmitted to the WRAM 42 (FIG. 2) as the time series signal storage means and the KRAM 41 (FIG. 2) as the coefficient data storage means.

CKCD: Data clock. This is a signal for strobe the external write data to the WRAM 42 and the KRAM 41.

CKCA: Address clock. This signal is used to strobe an externally specified address to the WRAM 42 and the KRAM 41.

CKCC: command. This specifies the type of the external access request. The external access request includes a write access and a read access to the WRAM 42, a write access and a read access to the KRAM 41.

(B) Information sent from the control unit 100 to the external access device (CPU) BUSY: busy. This signal is generated in response to an external access request and indicates that the execution of the external access has not been completed.

EXDO: External data output (bus). As a result, the data of the WRAM 42 and the KRAM 41 relating to the external read access are transmitted.

(C) Information CD sent from the control unit 100 to the arithmetic unit 200: data (bus). As a result, external write data to the WARM 42 and the KRAM 41 is transmitted.

 S1, S2, S3: Selector control signal.

 WWR: WRAM42 read / write control signal.

 KWR: KRAM41 read / write control signal.

 WAD: WRAM42 address (bus).

 KAD: KRAM41 address (bus).

 CK1; CK2: Register control clock.

(D) Information sent from the arithmetic unit 200 to the control unit 100 K: KRAM41 data (bus). Thereby, the data read from the KRAM 41 by the external access is transmitted.

W: WRAM42 data (bus). Thereby, the data read from the WRAM 42 by the external access is transmitted.

The digital signal processing device of this embodiment performs digital filtering according to the logical configuration of FIG. 4 on a time-division multiplexing basis with respect to signals of 32 channels at a given time from the external access device (CPU) 300. Given,
An access request for changing, updating, and checking data (coefficients, signals) relating to an arbitrary channel can be accepted and processed on a real-time basis.

More specifically, in the control unit 100 shown in FIG. 1, the data register 8 shown on the left is provided with an external data clock CK.
It operates on a CD, takes in data (24 bits) on the EXDI bus, and outputs it to the CD bus (24 bits). The address register 9 operates at the address clock CKCA, takes in data (7 bits) on the EXDI bus, and outputs it to the CA bus (7 bits). Command register 10 is the command clock CKCC
To take in data (4 bits) on the EXDI bus. The command clock CKCC sets the RS flip-flop 14, generates a BUSY signal, and controls the command decoding gates 15 to 18 coupled to the output of the register 10 with the BUSY signal. Gate 15 is a write instruction signal WWC of WRAM 42,
Gate 16 is write instruction signal KWC for KRAM41, gate 17 is WRA
The read instruction signal WRC of the M42 and the gate 18 generate the read instruction signal KRC of the KRAM 41, respectively. Therefore, in the 4-bit command stored in the command register 10, bit 0 is for WRAM writing, bit 1 is for KRAM writing, bit 2 is for WRAM reading, and bit 3 is for KRAM reading (see FIG. 11). The external access device (CPU) 300 issues a command to set any bit to “1” according to the type of the external access request. D flip-flop 12
Is used to reset the RS flip-flop 14 and release the BUSY signal after the completion of the access according to the external access request.The OR gate 19 of the WWT signal and the KWT signal,
The output of the OR gate 23 which takes the OR of the signal and the KPT signal with the OR gate 21 is taken in at the CK1 clock. The data register 11 is a register for sending WRAM data or KRAM data relating to an external read access request to the outside, and outputs the K bus data or W bus data from the selector 36 controlled by the WRT signal to the output of the D flip-flop # 13. Take in the signal
Output to EXDO bus. D flip-flop 13 is an OR gate
Capture the 21 output at the CK1 clock. The above configuration, that is, the elements 8 to 18, 19 to 21, and 36 constitute an interface between the control unit 100 and the external access device (CPU) 300.

The external access device (CPU) 300 and the control unit 100 are asynchronous, and the control unit 100 operates at its own timing. For this purpose, there is a timing generator 1 from which various timing signals, clock signals, CK1, CK2, CKW, 0ch
Is output. The timing chart of these timing signals is shown in the upper part of FIG. CKW is a clock having a phase relationship of approximately 90 ° with the clock CK1 for strobe of addresses and data, and is used for strobes of the read / write control signals KWR and WWR for the KRAM41 and WRAM42. 0ch
Is a timing signal indicating a zero channel.

The signal CK1 of the output of the clock generator 1 shown in FIG. The purpose of the counter 2 is to generate an address signal of the microprogram ROM 3 and to execute a logical channel number (specifically, KRAM
41 and the upper logical address of the WRAM 42).

As described above, the digital processing apparatus according to the present embodiment processes signals for 32 channels by time division multiplexing (see channel No. in FIG. 8). During one channel time, the lower two bits CT (0) of the 8-bit counter 2;
CT (1) changes to 0, 1, 2, and 3, which becomes the address input of the microprogram ROM3. Therefore, 1
There are four phases per channel, and the number of microcodes (program words) in the microprogram ROM3 is four. The logical channel numbers 0 to 31 are defined by CT (2) to CT (6) of the 8-bit counter 2, and the odd / even sampling period is defined by CT (7) of the most significant bit. The channel number generation function of the counter 2 can save the microcode length and number of the microprogram ROM3. The digital signal processing device logically processes the signal of the corresponding channel during one channel time, processes the signals of 0 to 31 ch during one sampling period, and again processes the signals of 0 to 31 ch in the next sampling period. However, in order to effectively use the resources of the arithmetic unit 200 (FIG. 2), the arithmetic unit 200 processes signals of two channels in parallel (overlapping).
Therefore, a means for converting the logical channel output of the counter 2 into an actual channel number is required. In particular, in the embodiment, the arithmetic access (internal access) to the KRAM 41 as the coefficient data storage means is all performed within the logical channel time, but a part of the arithmetic access to the WRAM 42 as the time-series waveform data storage means is performed. (Specifically, access for writing the operation result to the WRAM 42) occurs in the next logical channel. For this reason, the real address (6 bits) for the internal access to the KRAM 41 is the logical channel numbers CT (2) to CT (6) from the counter 2 and the microprogram ROM3.
The actual channel number (upper WRAM address) for the internal access to the WRAM 42 is the logical channel number CT from the counter 2 although part of the microcode MP (0) and MP (1) from (2) to CT (6) and the previous channel designation bit MP (3) in the microcode of the microprogram ROM3 are formed by adding in the adder 4, and when the previous channel is designated, the actual channel The number is set to (logical channel number -1). Further, as will be described in detail later, the least significant bit of the WRAM address for internal access is a signal CT (7) indicating the sampling period which is the most significant bit of the counter 7 as shown by gates 27, 29 and 28. MP of microcode (2)
And the exclusive-OR output of the microcode and the logical product of the previous channel designation bit MP (3) of the microcode and the 0ch signal indicating the zero channel are formed.

Microcode MP output by microprogram ROM3
Is 8 bits, and the meaning of each bit is as shown in FIG. MP (0) to MP (3) are for forming WRAM and KRAM addresses, and have already been described.

MP (4) is for KRAM access control.
It means that the KRAM 41 is used internally (for arithmetic operation), and when "1", it means that the KRAM 41 can be used for external access. To achieve this,
As shown in FIG. 1, MP (4) is ANDed with an external KRAM write instruction signal KWC by an AND gate 25 to generate a KWT signal, and an external KRAM read instruction signal KRC Is ANDed by the AND gate 26 to generate a KRT signal. After the KWT signal is set in the register 5 by the clock CK1, it is applied to the KRAM 41 as the KRAM write control signal KWR through the AND gate 31 at the timing of the write control clock CKW. The KWT signal and the KRT signal control the KRAM address selector 35 through the OR gate 33. At the time of internal access (KWT = KRT = 0), the internally generated KRAM real address is selected, and at the timing of the clock CK1. The signal is applied to the KRAM 41 from the KRAM address bus KAD through the register 7, and at the time of external access (KWT = 1 or KRT = 1), the bus CA
The external specified address above is provided to the KRAM 41.

MP (5) and MP (7) are for WRAM access control,
(5) When W = 1, WRAM 42 is accessed for internal read, and MP
When (5) = 0 and MP (7) = 1, WRAM 42 is accessed for internal write access. When MP (5) = 1 and MP (7) = 0, WRAM 42 is accessed.
42 is made available for external access.
To realize this, the microcode MP (5) and MP
(7) and the external WRAM read instruction signal WRC are connected to the gate 22.
, A signal WRT is generated in accordance with MP (7) ∧ ▲ ▼ ∧WRC, and MP (5), MP (7) and WWC which is an external WRAM write instruction signal
(7) ∧ and ▲ ▼ ∧ Generates a signal WWT according to WWC. The signal WWT and the WRT control the WRAM address selector 34 through the OR gate 32, and at the time of internal access (WWT = WRT =
In the case of 0), the WRAM real address generated internally is selected and given to the WRAM 42 through the register 6 of the CK1 operation.
At the time of external access (WWT = 1 or WRT = 1), an external instruction address on the bus CA is supplied to the WRAM 42. Furthermore, the signal WWT is input to the OR gate.
Alternatively, after MP (5) is passed and the register 5 is passed, it passes through the AND gate 30 at the timing of the write clock CKW, and
The write control signal 42 is added to the WRAM 42. Further, after the signals WWT and MP (5) have passed through the register 5, the signal 37 becomes a select signal S3 in accordance with ▲ ▼ ∨MP (5) at the gate 37, and as shown in FIG. It is used to control the selector 51 selected as the output register 49 output). Further signal MP
(7) becomes the select signal S1 after passing through the register 5, and controls the selector 52 for selecting either the data from the WRAM 42 or the data (input) from the time series generating section 400 as shown in FIG. Used to do.

The microcode MP (6) is for controlling another selector, and as shown in FIG. 2, AR (register 48 output)
Is a signal S2 for controlling the selector 53 for selecting any one of the zero 0ch.

The arithmetic unit 200 shown in FIG.
M41 and a WRAM 42 for storing a waveform data series are provided as arithmetic data storage means, and the data output of the KRAM 41 is CK
The signal from the register 46 for the CK1 operation passes through the register (KR) 45 for one operation and is output from the register 46 for the CK1 operation in the multiplier 3 (this is the signal from the time series generation unit 400 selected by the selector 52 or the signal from the WRAM 42). Is multiplied with the result, and the result is stored in the register (M
R) Set to 47. The output of register MR is an adder (AD
D) The signal is added to the signal from the selector 53 at 44 (this selects zero 0oh at the time of non-addition and selects the register AR output at the time of addition), and the result is set in the register AR. The output of the register AR48 is set in the output register 49 at the timing of the output clock CK2, is output to the outside, and is returned to the WRAM 42 at the timing when the WRAM data selector 51 selects OR.

FIG. 5 shows a memory map of the KRAM 41. As described above, this embodiment functionally has the second-order IIR digital filter shown in FIG. 4 for 32 channels, so that the coefficient multipliers 101, 102 and 103
Requires 32 sets of coefficients K, b1, and b2 to be used. here,
The microprogram ROM 3 of the control unit 1 (FIG. 1) has a microcode sequence (microprogram) length of 4, and its lower bits MP (0) and (1) indicate the in-channel address of the KRAM 41. The channel number constituting the upper address is the output of the counter 2 as described above.
It is determined by CT (6) to CT (2). These points and microprograms for realizing the second-order IIR digital filter (No. 10
Address) 0 to 3 for 0ch, 4 to 7 for 1ch
Address, and so on, addresses 124 to 127 become for 31ch,
The arrangement in the channel is 0 (MP (0), MP (1) = 00)
For b1 coefficient, 1 for b2 coefficient, 2 for K coefficient, 3 is unused.

The memory map of the WRAM 42 is not represented in one way. Since it is a second-order IIR digital filter of 32ch processing (FIG. 4), it is necessary to prepare both 32ch of the delay element 106 for the previous sample W1 and the delay element 107 for the sample W2 two times before. Therefore, in order to realize this with WRAM42, WRAM
The data number of 42 is 32 × 2 = 64. Micro program
At the level of ROM3, its microcode bit MP
According to (2), the logical address for the sample is determined,
When MP (2) = 0, the previous sample is designated. When MP (2) = 1, the sample is designated two times before. However, if the previous sample W1 and the previous sample W2 were placed at the same physical location (real address) on the WRAM 42, the previous sample W1 from the current sampling cycle is naturally the previous sample W2 from the next sampling cycle. Since it becomes W2, a contradiction arises. Therefore, a mechanism for inverting the position of the previous sample W1 and the sample W2 two times before the previous sample W2 on the WRAM 42 depending on whether the sampling period is odd or even is required. This is the exclusive OR of the logical sample designation bit MP (2) of the microcode in the control unit 1 of FIG. 2 and the most significant bit CT (7) of the counter 2 indicating the odd or even of the sampling period. This is realized by an EOR gate 29. As a result, as shown in (a) and (b) of FIG. 6, at the start of the even sampling period, the previous sample W1 is placed at the address 0 in the channel and the sample W2 is placed twice before the address 1 in the channel. The opposite is true at the start of the sampling period. There are further considerations in addressing the WRAM 42, which are summarized in FIG.
As described above, the control unit 100 processes the arithmetic unit 200 with 2ch overlap, and particularly, writes the arithmetic result to the WRAM 42 (written to the position that becomes the previous sample W1 in the next sampling cycle) in the next logical channel time. (CT
It occurs within (6) -CT (2)). Therefore, as described above, when the operation result is written, the logical channel numbers CT (6) to CT (2) from the counter 2 are added by the adder 4 to the previous channel.
The WRAM actual channel number is formed by subtracting 1 from the designated bit MP (3). Further, the calculation result of the 31st channel occurs at the logical zero channel time of the next sampling period. To cope with this, as shown in FIG. 2, the zero channel time signal 0ch and the previous channel designation bit MP (3)
Are both true, EXO is output at the output of AND gate 27.
An EXOR gate 28 for inverting the output of the R gate 29 again to form a real sample designation bit (WRAM real address LSB) is provided.

FIG. 10 is stored in the microprogram ROM3 of the control unit 100 in FIG. 1 when performing the secondary IIR (infinite impulse response) digital filtering whose logical configuration is shown in FIG. 4 by the arithmetic unit 200 in FIG. And is composed of four microcodes corresponding to four phases per channel. FIG. 12 is a flowchart showing the operation of the arithmetic unit 200 according to the microprogram of FIG. 10, and phases 0 to 3 correspond to 12-0 to 12-3, respectively. FIGS. 13 to 17 show the state of the arithmetic unit 200 in each phase.

Hereinafter, the arithmetic operation will be described in detail.
Then the microcode MP is 00000000, then KR
Both AM41 and WRAM42 are in a read state for internal access. In detail, from the KRAM 41, the current channel No. (in the case of KRAM, the logical channel No. CT (2) to CT (6) of the counter 2)
The coefficient b1 (which is designated by MP (1) = MP (0) = 0) relating to (corresponding to) is extracted and set in the KR register 45. The timing at which the output of the KR register 45 changes to the coefficient b1 data is determined by the clock CK1 of the register 5, the AR register 4
Due to the five clocks CK1, two clocks CK1 (two phases) are shifted (see the timing chart of FIG. 8). The same applies to other registers in the operation unit. From WRAM42, the previous waveform sample related to the current channel No.
W1 (specified by MP (2) = 0) is taken out and set in the WR register 46 through the selector 52 (12 in FIG. 12).
-0). In parallel with the processing related to the current channel,
Processing related to the previous channel is also performed. That is, MR register
KX input from 47 (corresponding to M3 in Fig. 4) and AR register
The result (corresponding to the output A2 of the adder 104 in FIG. 4) obtained by adding the b1W1 + b2W2 passed through the selector 52 from the adder 48 by the adder 44 is represented by A.
Set in R register 48 (accumulator).

In this phase 0, since both the KRAM 41 and the WRAM 42 are used for internal access, external access is not possible.

KRAM41 and WRAM even in phase 1 when microcode MP read from microprogram ROM3 is 0 * 000101
Reference numeral 42 is used for internal read access for operation. That is, the sample W2 related to the current channel is taken out of the WRAM 42 two times before and set in the WR register through the selector 52, and the coefficient data b2 is taken out of the KRAM 41 and set in the KR register. Also, WR register in phase 1
The data W1 and b1 set in 46 and the KR register 45 are multiplied by the multiplier 43 and set in the MR register 47. The operation result of the previous channel set in the AR register 48 (K
(Input × b1W1 + b2W2), that is, the output A2 of the adder 104 in FIG.
Is set in the OR register 49. Therefore, external access is also prohibited in this phase 1.

KR in phase 2 when microcode MP is 11101110
The AM 41 is in the read mode for the operation of the current channel, and the WRAM 42 is in the write mode for the operation of the previous channel. That is, for the current channel, the coefficient K is extracted from the KRAM 41 and set in the KR register 45, and the WR register 46 sets the time series selected by the selector 52 by S1 = 1 based on the microcode MP (7) = 1. Generator 400 (third
Signal is set. Also, KR register 45 and
The coefficient b2 already in the WR register and the sample W2 two times before are multiplied by the multiplier 43 and set in the MR register 47. B1W1 in the MR register 47 (the output M1 of the coefficient multiplier 102 in FIG. 4)
Are transferred to the AR register 48 through the adder 44 (the addend from the selector 53 is zero OH at this time). As the final processing of the previous channel, the OR register
The calculation result (sample) K input + b1W1 + b2W2 from 49 is written to the WRAM 42 through the selector 51. The write address of the WRAM 42 is a place where the sample is stored two times before in the previous channel, so that at the next sampling period, the EXOR gate 29 (FIG. 1) for the WRAM address LSB based on the odd or even sampling period. The inversion operation allows the data at that location to be accessed as the previous sample. In this phase 2, KRAM41,
Since any of the WRAMs 42 is used for an arithmetic operation, execution of an external access is prohibited.

The time slot of phase 3 in which the 8-bit microcode MP is 1001 **** is not used for the operation of either the KRAM 41 or the WRAM 42. This empty time slot
The bit value of bit MP (4) of the microcode that permits external access to KRAM 41 is "1", and WR
This is based on the combination of bit MP (7) = 1 and bit MP (5) = 0 of the microcode that permits external access to AM42. The operation of this phase 3 is
The operation is performed in a part other than the WRAM 42. Specifically, the output K of the KR register 45 and the output “input” of the WR register 46 are multiplied by
Multiply by 43 and set in MR register 47, and
B2W2 set in the register 47 (corresponding to the output M2 of the coefficient multiplier 103 in FIG. 4) is transferred from the AR register 48 to the selector 5
The b1W1 passed through 3 is added to the adder 44, and the result (corresponding to the output A1 of the adder 105 in FIG. 4) is set in the AR register 48.

After the phase 3, the process returns to the phase 0 for the next channel, and a secondary IIR digital filtering process by overlapping time division multiplexing of a plurality of channels (32 channels) is performed. By the way, b1W1 + b2W2 of the AR register 48 and the KX input of the MR register 47 obtained up to the phase 3 are added in the next phase 0 (FIG. 13), and in the next phase 1, the AR register 48 is added to the OR register 49. Then, in the next phase 2, the data is written from the OR register 49 to the WRAM 42, and one sampling cycle for the channel on the arithmetic unit 200 is completed.

The states of KR, WR, MR, AR, and OR for the zero channel are shown below the timing chart of FIG.
For example, b10 represents the coefficient b1 of the zero channel.

As described above, in the phase 3, neither the KRAM 41 nor the WRAM 42 participate in the arithmetic operation, so that the external access can be executed in this empty time slot.

Hereinafter, an operation in response to an external access request from the external access device (CPU) 300 will be described for each case. FIG. 17 shows an external WRAM write access, FIG. 18 shows an external WRAM read access, FIG. 19 shows an external KRAM write access, and FIG. 20 shows an external KRAM read Each flow in the case of access is shown. In each figure, the operation of the external access device (CPU) 300 is shown on the left side, and the operation of the digital signal processing device (100, 200) is shown on the right side.

(A) External WRAM write access In this case, the external access device (CPU) 300 sends write data to the WRAM 42 to the EXDI bus,
CKCD is enabled to "1" (17A-1). As a result, the data register 8 in the interface of the control unit 100 is set to the data on the EXDI bus, and outputs it to the CD bus (17B-1). Furthermore, external access device (CPU)
300 sends a write address to the WRAM 42 to the EXDI bus and enables the address clock CKCA to "1" (17
A-2). As a result, the address register 9 of the control unit 100 is set, and the external instruction address is output to the CA bus. Further, the external access device (CPU) 300 sends a WRAM write command 0001 to the EXDI bus, and sets the command clock CKCC to "1" (17A-3). This allows the command register of the control unit 100
10 is set to 0001, the RS flip-flop 14 is set, and a BUSY signal indicating that processing is in progress is generated. Subsequently, the gate 15 decodes the command and outputs a WRAM write instruction signal.
WWC occurs (17B-3). The WRAM write instruction signal generated on the WWC line is used in an empty time slot of phase 3. That is, when the phase 3 is reached, the microcode MP
Since (7) = 1 and MP (5) = 0 (see FIG. 10), WWC
Gate 23, which has been half-enabled, operates and WW
Generate T signal. This WWT signal (WWT = 1) is the OR gate 3
2 and joins the selector 34.
Select RAM write address, and register 2
Add to 00 WRAM address input. Further, the WWT signal generates S3 = "0" through the gate 37, and the WRAM input selector 51
Causes the external write data on the CD bus to be selected. Furthermore, WWT
The signal passes through OR gate 24, register 5, AND gate 30, and
At the KW timing, a WRAM write control signal WWR is applied to the WRAM. Thus, the externally specified data is written to the externally specified address of the WRAM 42, and the external WRAM writing process is completed. On the other hand, the WWT signal is the OR gate of the interface of the control unit 100.
The D flip-flop 14 is reset through 19 and 23, thereby resetting the RS flip-flop 14 and releasing the BUSY signal. At this time, the gate 15 is set in the prohibited state, and the WRAM write operation is prohibited again (17B-4).

On the other hand, the external access device (CPU) 300 periodically checks the state of the BUSY line after sending the command. The BUSY line becomes active “1” in response to the command response from the RS flip-flop 14, and during that time, the external access device (CPU) 300
Cannot request the next external access (if any) (17A-4). If there are more external access requests, B
This is performed when the status of the USY line becomes “0”. For example, when the WRAM write access is requested again, the processing of 17A-1 or less is executed.

(B) External WRAM read access In this case, since write data is unnecessary, the operation of data transfer corresponding to 17A-1 and 17B-1 in the operation of FIG. 17 is omitted.

18A-1 and 17A-2 operate in the same way, and 18B-1 and 17A
-2 is a similar operation, and is a process of transmitting and receiving a WRAM read address, respectively.

As shown in 18A-2, the external access device (CPU) 300 is E
A WRAM read command 0100 is sent to the XDI bus, CKCC = 1, and in response to this, the state of the command register 10 of the control unit 100 interface changes to 0100, and the gate 17
A read instruction signal WRC is generated and a BUSY signal is generated from the RS flip-flop 14 (18B-2). When the empty time slot of phase 3 is reached, WRC = 1, M
From P7 = 1, MP5 = 0, the output WRT = 1 of gate 22, WWR =
0 (WRAM read mode), WAD = CA (address of external instruction), and the data at the external instruction address of WRAM42 is
Read from WRAM42. The output of the WRAM 42 passes through the K bus and is selected by the selector 36 in the WRT operation. On the other hand, the WRT signal sets the data register 11 via the OR gate and the D flip-flop 13, and outputs the WRAM 42 output from the selector 36.
Output to EXDO bus. In addition, WRT is OR gate 21, 23,
The RS flip-flop 14 is reset via the D flip-flop 12 to release the BUSY signal (18B-3). As a result, the external access device (CPU) 300 detects “0” on the BUSY line, and at that time fetches the WRAM 42 output data on the EXDO bus. 18A if there is an external WRAM read access request
Repeat -1 and below.

(C) KRAM write access from outside 19A-1 and 19A-2 on the external access device (CPU) 300 side
The processing of 19A-3 is such that the information transmitted to the EXDI bus in 19A-1, 19A-2, and 19A-3 is the write coefficient data to the KRAM 41, the address of the coefficient data write to the KRAM 41, Except for the KRAM write command (0010), 17A-1 and 17A- in the external WRAM write access in FIG.
2, 17A-3. The operation of the control unit 100 also
19B-1 is similar to 17B-1, 19B-2 is similar to 17B-2,
19B-3 is the same as 17B-3 except that the gate 16 generates the KRAM write instruction signal KWC instead of the WWC of the gate 15.
In phase 3 (see 19B-4), microcode M
P (4) becomes a value “1” indicating the empty state of the KRAM. Therefore, the signal of KWC = 1 generates the KWT through the gate 25,
Also, the KRAM write signal KWR passes through the register 5 and the AND gate 31.
Is generated, and the CA address can be selected by the selector 35 so that the externally designated KRAM write address is
Give to KRAM41. As a result, the coefficient data externally specified on the CA bus is written to the externally specified address of the KRAM 41. Regarding the release of the BUSY signal, the KWT signal operates similarly to the WWT signal. The operation 19B-4 of the external access device (CPU) 300 for the BUSY signal is the same as before.

(D) External KRAM read access The operation in this case (see FIG. 20) corresponds to 20A-1 corresponding to 18A-1 on the CPU 300 side except that the EXDI information is a coefficient data read address. -2 is EXDI to 18A-2
The information is the same except that the information is a KRAM read command (1000), and the information is the same except that the data fetched from EXA to 20A-3 to 18A-3 is the KRAM read data. Control unit
100 is the same as 18B-2 except that 20B-1 corresponds to 18B-1, and 20B-2 generates the KRAM read instruction signal KRC of gate 18 instead of WRC of gate 17. As shown in 20B-3, when the phase 3 is reached, KRU = 1, KWR = 0, KAD = CA, and K = KRA
As indicated by M (CA), the data at the externally designated address CA of the KRAM 41 is transmitted to the K bus. And selector 3
6. The read KRAM data is output to the EXDO bus through the data register 11. Other points are the same as 18B-3.

In this embodiment, when a sound signal is used as an input signal time series, it can be used as an equalizer or an effector of an audio or electronic musical instrument.In this case, it is possible to dynamically change the sound quality and effect while listening to the sound. It is possible.

The description of the embodiment is finished above, but various modifications and changes can be easily made within the scope of the present invention. For example, the signal processing performed by the digital signal processing device is not limited to filtering, but may be any other desired digital signal processing.

[Effects of the Invention] Finally, effects of the invention described in the claims will be described.

According to the first aspect of the present invention, an empty time slot which is not accessed in the arithmetic operation is defined based on a microprogram which determines the content of signal processing, and an external access to the arithmetic data storage means is executed in the empty time slot. An access request can be freely given from the outside on a real-time basis without interrupting the arithmetic operation in the circuit means, whereby, for example, the characteristics of the digital signal to be processed can be freely adjusted on a real-time basis.

According to the second aspect, any one of write access, read access to the coefficient data storage means, write access to the time series signal storage means, and read access to the time series signal storage means can be performed in an arbitrary empty time slot. Inspection of time series signals can be freely performed.

According to the third aspect, an empty time slot is defined when the microcode sequentially read from the microprogram storage means includes a specific code, so that the configuration of the control circuit means having an external real-time access processing capability is reduced. Can be simplified. Claims 4 and 5 show specific code examples.

[Brief description of the drawings]

FIG. 1 is a block diagram of a control unit of a digital signal processing apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram of a calculation unit controlled by the control unit of FIG. 1, and FIG. FIG. 4 is a diagram showing an overall configuration including a signal processing device, FIG. 4 is a diagram showing a logical configuration of signal processing when performing secondary IIR digital filtering as signal processing in the embodiment, and FIG. 5 is a memory map of the KRAM in FIG. FIG. 6 is a diagram illustrating a memory map of the WRAM of FIG. 2, FIG. 7 is a diagram for explaining addressing for the WRAM, FIG. 8 is a time chart of the operation of the present embodiment, FIG. FIG. 10 is a diagram illustrating the format of microcode stored in the microprogram ROM of FIG. 1; FIG. 10 is a diagram illustrating a microprogram stored in the microprogram ROM for the secondary IIR digital filter of FIG. 4; Fig. 11 FIG. 12 is a view for explaining the format of the command register shown in FIG. 12, FIG. 12 is a flowchart of an arithmetic operation in the present embodiment, FIG. 13, FIG. 14, FIG. 15, and FIG. 17 is a flowchart showing an operation relating to an external WRAM write access, FIG. 18 is a flowchart showing an operation relating to an external WRAM read access, and FIG. 19 is a flowchart showing an operation relating to an external KRAM write access. FIG. 20 is a flowchart showing an operation relating to an external KRAM read access. 1 ... timing generator, 2 ... counter, 3 ... microprogram ROM, 23-26, 30-33 ... gate, 34, 3
5 ... selector, 41 ... KRAM, 42 ... WRAM, 51 ... selector.

Claims (5)

(57) [Claims] 1. A digital signal processing apparatus comprising: arithmetic circuit means provided with arithmetic data storage means; and microprogram operation control circuit means for controlling arithmetic operation in said arithmetic circuit means. Empty time slot defining means for defining, based on the microprogram, an empty time slot that does not access the arithmetic data storage means as part of the arithmetic operation for an access request to the data storage means; External access execution means for executing an access according to the access request to the operation data storage means in the empty time slot defined by the empty time slot defining means when there is an access request to the storage means; A digital signal processor characterized by having Apparatus. 2. The digital signal processing device according to claim 1, wherein said operation data storage means includes a time series signal storage means for storing a time series of the signal, and coefficient data for storing coefficient data to be multiplied by the signal. Storage means, wherein the external access execution means selectively performs write access, read access to the time-series signal storage means, and write access to the coefficient data storage means according to the type of the external access request. A digital signal processing device for performing read access. 3. The digital signal processing device according to claim 1, wherein said control circuit means includes: a microprogram storage means for storing a microcode sequence as said microprogram; and said microcode is sequentially stored from said microprogram storage means. And a sequential repetitive reading means for reading and repeating the sequence. When the microcode read by the sequential repetitive reading means includes a specific code, the microcode read by the empty time slot defining means by the specific code. A digital signal processing device, wherein an empty time slot is defined. 4. The digital signal processing device according to claim 3, wherein said specific code is represented by a specific value of a specific one bit in said microcode. 5. A digital signal processing apparatus according to claim 3, wherein said specific code is represented by a specific logic function value of a specific plurality of bits included in said microcode. .