JP3061737B2 - IC tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester,
More specifically, the present invention relates to a timing correction circuit that can efficiently adjust the timing of each output waveform in a short time or adjust the determination timing of an input waveform from a device under test (hereinafter, a DUT) to a determination comparator.

[0002]

2. Description of the Related Art FIG. 3 shows a schematic configuration of a conventional IC tester. The IC tester uses a test processor (CP
U) 1, a pattern generator (PG) 2 for generating test pattern data [Dp], a rate signal generator (RG) 31 for generating a rate signal [R], and r timing pulse generators ( TG) 32, a multiplexer (MLPX) 4, a programmable delay circuit (DLY) 52 and a waveform formatter (FMT) 51 for skew correction, and a delay circuit (DLY) 54 disposed behind the timing generator 3 A waveform generator 5 having n circuits, a driver unit 6 composed of n drivers (DRV) 61 respectively receiving n outputs [PT] from the waveform generator 5, and I of the device under test (DUT) 10 / O
M (m <n) switches S provided corresponding to the terminals
, A decision circuit 8 composed of m analog comparators (ACOM) 81 and m digital comparators (DCOM) 82 provided corresponding to the I / O terminals, and a register (REG) 91 And control circuit (C
(ONT) 92 and the like.

Here, various pattern data [Dp] generated by the PG 2 are input to the respective FMTs 51. On the other hand, each TG 32 periodically generates and outputs various timing pulses in response to the input of the rate signal [R]. This timing pulse includes an edge pulse [Eg].
And a switching signal [Sk] to the switching circuit section 7 and each D
There is a strobe pulse [STB] (hereinafter, strobe [STB]) for the COM 82. The edge pulse [Eg
], A delay circuit (DL) is provided before and after each FMT 51.
Y) 52, 54 are provided, and the switching pulse [Sk]
And a strobe [STB], a delay circuit (K · DLY) 72 and a delay circuit (S · DLY) 8
2 are provided. (DLY) 52, 54,
K · DLY 72 and S · DLY 83 have the same structure, but are distinguished by prefixing K and S for convenience of explanation.

Each timing pulse is input to the waveform generator 5 through the MPLX 4, and each edge pulse [Eg] is supplied to each FMT 51 through the DLY 52,
By this and the pattern data [Dp], the test waveform [P
T] are respectively generated. Each test waveform [PT] is D
The data is input to the corresponding DRV 61 via the LY 52 and the DUT
These are directly applied to each I pin of
The voltage is applied to the pin through each switch S of the switching circuit unit 7. Here, the FMT 51 selects a timing signal (an edge pulse [Eg] for determining the rising or falling timing of a generated waveform) from the timing generating unit 3, receives a signal from the PG3 as pattern data [Dp], and receives a predetermined signal. Waveform shaping according to the mode, for example, N
Output waveforms such as RZ and RZ are generated.

Each switch S is switched at a predetermined timing by a switching pulse [Sk], and read data [DR] from each I / O pin is transmitted to a corresponding ACOM of the determination unit 8.
The data is binarized (digitized) and input to each DCOM 82. The DCOM 82 receives the expected data [Dk] from the PG2, compares the two, and outputs the result of comparison between the two at the time of input of the strobe [STB]. The comparison result output from each DCOM 82 is output to the control unit (CONT) of the inspection result data processing unit 9.
Under the control of 92, they are stored in predetermined areas of a register (REG) 91, respectively, and are analyzed to
The quality of the DUT 10 is determined for each pin, and the determination result is C
It is sent to PU1. As a result, evaluation data of the DUT 10 is created and output from the CPU 1.

In such an IC tester, a programmable delay line DLY52 for skew correction is provided before and after each driver, particularly in front of each driver, in order to match the output waveform timing of the output terminal. The delay amounts of these delay lines are adjusted to match a predetermined delay amount previously adjusted by the calibration driver and the calibration comparator. Similarly, with respect to the input waveform to the determination comparator receiving the waveform output from the DUT 10, a calibration driver or a driver for generating a delay-adjustable reference waveform and a calibration driver for the strobe [STB] at the determination timing are similarly used. Similar adjustment is performed by a comparator or a comparator for determination.

For example, in the adjustment by the calibration driver and the calibration comparator, first, the calibration comparator receives a waveform generated by the calibration driver through a fixed delay path, and sets a strobe according to the received timing to a programmable delay. This is caused by adjusting with a line. Using the strobe generated in this way as a reference strobe, the programmable delay before each driver is detected by detecting the output waveform with a calibration comparator or judgment comparator so that the waveform of the output terminal of each driver matches the timing of this reference strobe. Adjust the line delay.

[0008]

SUMMARY OF THE INVENTION
As a timing correction circuit of the IC tester, a calibration driver and a calibration comparator are provided for each output, or a driver for generating a delay adjustable reference waveform and a calibration comparator or a comparator for determination are provided at each output terminal. Are connected via a switching switch.
As a result, calibration is performed sequentially for each output terminal. Therefore, it takes time to calibrate the delay time of the reference strobe. Further, since it is necessary to sequentially adjust the delay value of the programmable delay line of each output, there is a problem that it takes too much time to adjust the overall timing. SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem of the prior art, and to provide an IC tester in which a delay time for calibrating a reference strobe can be calibrated in a short time. Another object of the present invention is to provide an IC tester capable of setting a delay time for calibrating a reference strobe and adjusting timing correction of each output waveform in a short time.

[0009]

A feature of the IC tester according to the first aspect of the present invention that achieves the above object is to have a counter that receives a pulse generated at a predetermined cycle and counts it, and receives a strobe. A plurality of variable delay circuits for providing a strobe with a delay time corresponding to the count value of the counter and outputting the strobe;
A reference waveform generating circuit that generates a reference waveform that changes to a W level (hereinafter “L”) or the opposite state in synchronization with a strobe, and is provided corresponding to each of the plurality of variable delay circuits, and each corresponds to the reference waveform. And a plurality of comparators that determine whether the reference waveform is in an “H” state or an “L” state at the timing of receiving the strobes, and Each of the counters is provided in response to the determination result from the corresponding comparator, detects that the determination result has changed, and gives a delay time to the strobe corresponding to the comparator that received the determination result in response to the detection. A plurality of determination result change point detection circuits for stopping the count value, and generating a strobe at a predetermined cycle. Than it is.

The IC tester according to a second aspect of the present invention is characterized in that, in addition to the above-described configuration, a circuit which determines the generation timing of each of a plurality of output waveforms that change from "H" to "L" or the opposite state. Provided for each of the
A counter for receiving and counting pulses generated in a predetermined cycle, each receiving a timing pulse for determining an output waveform generation timing, and giving a delay time corresponding to the count value of the counter to the timing pulse; A plurality of variable delay circuits for outputting, and a plurality of outputs each of which is provided corresponding to each of the plurality of delay circuits and generates an output waveform which is shaped in accordance with a timing pulse output from the corresponding variable delay circuit. A circuit, a reference waveform and each of output waveforms from a plurality of output circuits, and selects one of the output waveforms. When an output waveform is selected, each output waveform is used as an input signal, and a comparator corresponding to the output circuit that generated the input signal. Respectively, and when the reference waveform is selected, this is used as the input signal of the comparator. A selection circuit for sending to each of the comparators, wherein the determination result change point detection circuit is provided for each of the plurality of comparators and receives the determination result from the corresponding comparator. When the change of the judgment result is detected, and when the selection circuit is selecting the reference waveform, the count value of the counter of the variable delay circuit on the strobe side corresponding to the comparator receiving the judgment result is stopped and selected according to the detection. When the output waveform is selected by the circuit, the count value of the counter of the variable delay circuit on the output waveform side corresponding to the comparator that received the judgment result in response to the detection is stopped, and the reference waveform is selected by the selection circuit To generate a strobe at a predetermined cycle, stop the counter of the variable delay circuit on the strobe side, and Ri selects the output waveform is intended to stop the counter of the variable delay circuit of the output waveform is generated at the predetermined period or other predetermined period output waveform side together generate a strobe at a predetermined cycle.

[0011]

As described above, the reference waveform is added to each of the plurality of comparators, and each strobe assigned to each comparator indicating the determination timing, for example, the determination strobe is sequentially delayed at a predetermined cycle in accordance with the clock count value. The determination results of "H" and "L" are continuously obtained at the respective delayed timing positions of each determination strobe. Then, a transition point from “H” to “L” or vice versa is detected from the continuation of the determination result, and the delay time of each determination strobe is set so as to coincide with the transition point. This makes it possible to calibrate the generation timing of each determination strobe and the like. In addition, the delay time set in each of the determination strobes is such that the clock is counted by a counter and the counting is stopped at the time of detection of the change point. Time can be set. This makes it possible to calibrate a large number of decision strobes in a short time. Also, as shown in the configuration of the second invention, the delay time on the timing adjustment side of the output waveform is similarly counted by a counter using the calibrated determination strobe, and the clock of the change point is changed. If the counting is stopped at the time of detection, the timing correction of the output waveform can be easily adjusted in a short time.

[0012]

FIG. 1 is a block diagram mainly showing a waveform generation unit and a judgment unit of an IC tester to which the present invention is applied, and FIG. 2 is an explanatory diagram of a relationship between a timing of a waveform input to a judgment circuit and a judgment result. It is. In FIG. 1, reference numeral 50 denotes a waveform generator, which corresponds to the waveform generator 5 in FIG. FMT51
Is different from the DLY 52 in the configuration of the variable delay circuit 53 in front of the DLY 52. DLY5 behind FMT51
4 may also be changed to the variable delay circuit 53, but the adjustment control of the skew correction becomes complicated. For convenience of explanation, here, the embodiment in which only the front delay circuit 52 is replaced with the variable delay circuit 53 will be described. Will be described. In FIG. 1, a stop control circuit 16 for receiving the determination result of the determination unit 8 is provided, and a changeover switch circuit 11 and a clock generation circuit 15 are provided.
And a reference waveform generation circuit 17. Further, a variable delay circuit 84 having the same calibration as the variable delay circuit 53 is provided instead of the S • DLY 83 in FIG. The reference waveform generation circuit 17 outputs the strobe [ST
B] in response to this occurrence and at this cycle in FIG.
, A reference waveform 18 that shifts from "L" to "H" is generated. Since the overall configuration of the IC tester is as shown in FIG. 3, the other components are indicated by the same reference numerals in FIG. 1 and some of them are omitted.

The FMTs 51 in FIG. 3 are, for convenience of explanation, FMTs 51a, 51b,.
, 51p, and DLYs 54 behind the FMTs 51 are DLYs 54a, 54b,.
, 54n,..., 54p. Also, D
RV61 is also DRV61a, 61b, ..., 61m, 61
, 61p. Similarly, ACOM
81 includes ACOMs 81a, 81b,..., 81m, and DCOM 82 includes DCOMs 82a, 82b,.
It shall consist of 2 m. Here, the output side of the DRVs 61a, 61b,.
The output side of the DRVs 61n,..., 61p corresponds to the I / O dedicated pin. By the way, in the following description, the numbers from which the subscripts a, b, m, n, and p are deleted are used as representatives of the circuits with the respective subscripts.

The variable delay circuit 53 includes 53a, 53b,..., 53m, 53n,.
It consists of 3p. The variable delay circuit 84 for adjusting the timing of the determination strobe [STB] includes variable delay circuits 84a, 84b,..., 84m corresponding to the DCOM 82 described above. The configurations of these variable delay circuits are the same. The variable delay circuits 53a, 53b,..., 53m are delay circuits (DLY) 530a, 530b,.
, 530p and counters 531a, 531b,..., 53 for determining the delay time of each of these delay circuits.
, 531p and the gate circuit 532a,
, 532m, 532n,..., 532p, and each counter 531 (counters 531a, 531
, 531m, 531n,..., 531p) to the respective delay circuits 530 (delay circuits 53).
0a, 530b, ..., 530m, 530n, ..., 530
p), the path of the delay circuit is selected by the received count value, and the delay time determined by the selected path becomes the delay time of the delay circuit 530, and the edge pulse Eg is delayed by that time. Output to FMT51. This delay time is usually equal to the count value times the unit delay time δ (see FIG. 2D).

Gate circuit 532 (gate circuit 532a,
, 532b, ..., 532m, 532n, ..., 532p)
Receives the clock CLK from the clock generation circuit 15 and the control signal from the stop control circuit 16, and sends the clock CLK to the counter 531 to count the clock CLK while the control signal is present. Variable delay circuit 84a,
84b,..., 84m are MPL like the variable delay circuit 53.
840m receiving the original strobe ST from X4, respectively, and a counter 841 for determining the delay time of each of these delay circuits.
, 841m, and gate circuits 842a, 8
, 842m, and each circuit is in the same relationship as the variable delay circuit 6 described above. And
Decision strobes STa, ST delayed as their outputs
, STi,..., STm.

The ACOM 81 binarizes an input signal into a digital value, and provides a DCOM provided corresponding to each value.
, 83m. These circuits are the circuits of the determination unit 8 that makes a determination by comparing the output waveform of the DUT 10 with an expected value as described above. Therefore, the number m of these circuits is provided by the number corresponding to the I / O dedicated pins. Here, the I dedicated pin is
Treat it as the same as or less than the O dedicated pin,
In the case of more than this, it is only necessary to provide a switching circuit and connect each of the ACOMs 81a, 81b,..., 81m at the timing of the time division control. Circuit connections are not shown.

ACOMs 81a, 81b,...
Each of the I / O dedicated pins DRV61a, 61b, ...,
Switch circuit 1 corresponding to each signal from 61m
, 12m. ACOMs 81a, 81b,..., 81m are provided with switches 1 of the switch circuit 11 corresponding to the signals from the DRVs 61n,.
3a, 13b,..., 13k. Furthermore, A
, 81m are the switch circuits 1 corresponding to the signals from the reference waveform generation circuit 17 respectively.
, 14m via the first switch 14a, 14b,..., 14m.

Each ACOM 81 (81a, 81b,..., 8)
1m), when any of the switches 12, 13, 14 connected thereto is turned on, the DRVs 61a, 61b,
, 61m, DRVs 61n,..., 61p, and a reference waveform 18 from a reference waveform generating circuit 17 (FIG. 2).
(c) is selected, and each signal is
Receive in parallel. The switch 12 (switch 1
, 12m), the switch 13 (switches 13a, 13b,..., 13k) and the switch 14 (switches 14a, 14b,..., 14m) are turned on / off in response to a control signal from the CPU 1. Each DCOM 82
(DCOMs 82a, 82b, ..., 82m) are, for example,
Pass (P, pass) when the input binary signal is "H" at the timing of generation of the determination strobe [STB], and fail (F, fail) when it is "L". In response to the determination result, "H" and "L" signals corresponding to the path P and the fail F are generated and sent to the stop control circuit 16.

The stop control circuit 16 sends a gate signal to each of the variable delay circuits 53 and 84 and their gate circuits 532 and 842 in response to a control signal from the CPU 1. A change point detection circuit 160 for detecting a change point of the determination result of shifting from the path P to the fail F and a change point in the opposite direction.
, 160b,..., 160m. Each change point detection circuit 160 is composed of, for example, a two-stage shift register and an exclusive OR circuit that employs an exclusive OR of outputs of flip-flops of each stage, and each stage has “1”, “0”. "0" or "1", the output of the exclusive OR circuit is used as a change point detection output. When a change point is detected in the determination result in any of the change point detection circuits 160, each of the variable delay circuits 53 (variable delay circuits 53a, 53b,..., 53m or variable delay circuits 53n,. Each variable delay circuit 84 (variable delay circuits 84a, 84b,..., 84
m), a gate circuit 532 (gate circuits 532a, 532b,
, 532m or gate circuits 532n, ..., 532
p) or gate circuit 842 (gate circuit 842a,
842b,... 842m) are turned off. As a result, the gate corresponding to the counter at which the change point is detected is closed, the counter 531 or 841 stops counting, and the delay time of the corresponding delay circuit becomes a value set by the count value of the counter.

The timing adjustment is performed by first determining each determination strobe [STB] (determination strobes STa, STb,
(STi,..., STm) are calibrated, and then the timing adjustment of the I / O dedicated pin and the timing adjustment of the I dedicated pin are performed. Either the I / O dedicated pin or the I dedicated pin may be adjusted in timing first. When the timing of each determination strobe [STB] (determination strobes STa, STb,..., STm) is calibrated, each change point detection circuit 160 detects a change point of the path P from the fail F, and is dedicated to I / O. Pin or I
A description will be given below with reference to FIG. 2 assuming that each change point detection circuit 160 detects a change point of the fail F from the path P when adjusting the timing of the dedicated pin. CPU1
The clock generation circuit 15 is started, and a control signal is sent to each switch 14 of the switch circuit 11 to turn them on. Then, the stop control circuit 16 is activated to generate a gate signal to the gate circuit 842 of each variable delay circuit 84, and the reference waveform generation circuit 17 is operated to generate the reference waveform 18 corresponding to the generation cycle of the original strobe ST. Are sequentially generated and added to each ACOM 81.

As a result, as shown in FIG. 2, each time the clock pulse CLK (see FIG. 2A) is received, the value of each counter 841 (see FIG. 2B) is counted up, and the original strobe is generated. Each time, from each ACOM 81 to each DC
The binarized reference waveform 18 input to the OM 82 (FIG. 2)
(See (c)), and the decision strobe [S
TB] are sequentially delayed by δ. Naturally, the original strobe ST before the strobe delay added from the MLPX 4 to each variable delay circuit 84 is determined by the determination strobes STa to STm in the period T of the clock CLK.
(See FIG. 2 (a)) and occur at a predetermined period with a timing such that they are arranged (see FIG. 2 (e)). Each DCOM8
2, since the decision strobe [STB] is received, when the binarized waveform 18 is "H" at the timing of the received decision strobe [STB], the path P
, And if it is "L", a fail F signal is generated (see FIG. 2D). Therefore, the determination result of DCOM 82 for a certain determination strobe STi is FFFP
(See FIG. 2 (d)). The determination strobe STi is composed of the determination strobes STa, STb,..., ST shown in FIG.
m, and the entire strobe is the original strobe ST
2 (e). On the other hand, AC
Since the timings at which the binarized reference waveform 18 applied to the OM 81 is generated are equal, the number of failures F before the path P changes according to the timing (the position) of the determination strobe [STB]. The number F indicates the amount of deviation of the timing of the determination strobe [STB]. Here, each of the DCOM 8
It is assumed that the delay times in wiring paths up to 2 are equal. Also, the output side of each output waveform (changeover switch circuit section 7)
It is assumed that the delay time in the wiring path from the switching terminal of each switch S to each DCOM 82 is also equal. By the way, the above is the rising state of the waveform, but in the falling state, the above determination result is reversed. The detection of the change point is reversed. Furthermore, if the relationship between the path P and the fail F is reversed for the waveform states “H” and “L”, the determination result is also reversed and the detection relationship is also reversed. Therefore, the change point of the determination result is relatively determined.

Here, it is assumed that reference waveform 18 is in a rising state from "L" to "H". Therefore, each determination strobe [STB] (in FIG. 2 (d), the determination strobe ST
i) is matched. In this way, the thresholds TH (“H” and “L”) of the binarized reference waveform 18 (see FIG. 2)
(d), the generation timing of each determination strobe [STB] can be calibrated at a timing substantially matching the position of (d). Thereby, the determination strobes STa to ST
Each determination result for m is obtained for each clock, and each determination result is a result for each δ delay of the reference waveform 18, whereby the timing of each determination strobe [STB] is determined.

Each change point detection circuit 160 detects a change point of the determination result, and stops the gate signal to the gate circuit 842 at the time when each change point is detected according to each detection timing. As a result, the gates of the respective gate circuits 842 are closed in accordance with the respective detection timings, and the respective counters 841 are set to the count values corresponding to the respective timings corresponding to the respective change points. Therefore, the delay time of each delay circuit 84 becomes a timing corresponding to each change point, and each determination strobe [ST
B] is automatically calibrated at the same timing.

Next, the timing of the I / O dedicated pin is adjusted. At this time, each switch 1 of the switch circuit 11
4 is turned off, and each switch 12 is turned on from the CPU 1.
Is transmitted. In this case, it goes without saying that the pattern data [Dp] is also generated at the same cycle as the edge pulse Eg and is added to the FMT 51.
The edge pulse Eg obtained from the timing generator 3 via the MLPX 4 is simultaneously applied to each of the variable delay circuits 53 and P
Edge pulse Eg obtained by delaying a waveform corresponding to the waveform data from G3 in each variable delay circuit 53 in FMT 51
Then, the pattern data [PT] is waveform-shaped and added to the DRV 61 to generate the rising output waveform which changes from "L" to "H" in the same manner as the reference waveform 18 at a predetermined cycle. Let it. Instead of the reference waveform 18 applied to each ACOM 81, this is applied to each ACOM 81 via each switch 12. The predetermined cycle is CL
It may be synchronized with and correspond to the K cycle, but need not be the same. This is because the determination is merely detection of a change point, and an output waveform that is sequentially delayed may be generated. However, when the delay time is rough, the delay should be delayed as much as possible in synchronization with the clock CLK. The output waveform generated in a predetermined cycle has a relationship opposite to that of the reference waveform 18 with respect to the determination strobe [STB]. That is, the determination strobe [ST
B] is fixed, and the output waveform side is sequentially delayed by δ each time it occurs. Therefore, in this case, a change point of the fail F is detected from the path P.

On the other hand, a gate signal is sent from the stop control circuit 16 to the gate circuit 532 of each of the variable delay circuits 53a, 53b,..., 53m, and the calibrated judgment strobe [STB] is sent to each DCOM 82. . Similarly to the above, the change points are detected by the respective change point detection circuits 160, and the respective gate signals are stopped according to the respective detection timings. As a result, the gates of the gate circuits 532 of the variable delay circuits 53a, 53b,..., 53m close at the respective detection timings, and the counters 5 of the variable delay circuits 53a, 53b,.
31 count values are set respectively. Since the delay time of the delay circuit 530 of each of the variable delay circuits 53a, 53b,..., 53m coincides with each change point, and each determination strobe [STB] is calibrated to the same timing. Each of the variable delay circuits 53a, 53b,
, 53m are automatically corrected to a delay time such that the same timing coincides.

Next, the timing of the I dedicated pin is adjusted. At this time, each switch 12 of the switch circuit 11
Is turned off, and a control signal for turning on the switch 13 is transmitted from the CPU 1. Otherwise, each variable delay circuit 5
, 53m are variable delay circuits 53n,
, 53p, and is performed in the same procedure as the timing adjustment of the I / O dedicated pin. As described above, the delay time of each variable delay circuit can be automatically set so that the timing of each output waveform matches.

In the change point detecting circuit for detecting a change point of the judgment result in the embodiment, "H" is passed and "L" is failed. When detecting the falling state, the relationship between the fail and the pass may be reversed. Therefore, the change point detection circuit according to the embodiment detects a change point at which the transition from the path P to the failure F occurs. However, since the determination result is determined by the relationship between the detected logic level and the waveform state, Needless to say, the change point detecting circuit may detect a change point at which the transition from the fail F to the path P occurs.

Further, in the embodiment, the strobe and the edge pulse are generated at a predetermined cycle to obtain the measurement result by one measurement. However, the present invention is further performed at a certain number of measurement cycles, The delay time of each variable delay circuit may be set. In this case, the data of the change point may be collected a plurality of times, and the average value thereof may be set in a counter for setting the delay time. Further, the clock generation circuit 15 in the embodiment can be eliminated by generating the clock CLK from the timing generation unit 3. Further, a clock generation circuit provided inside the timing generation unit 3 can be used.

[0029]

According to the present invention, a reference waveform is applied to each of a plurality of comparators, and each strobe assigned to each comparator indicating its determination timing, for example, the determination strobe is counted by a clock count value at a predetermined period. The determination results of “H” and “L” are continuously obtained at the respective delayed timing positions of the strobes while sequentially delaying according to the following.
Since the change point of "L" is detected and the delay time of each strobe is adjusted to match this change point, a large number of strobe generation timings can be calibrated simultaneously. In addition, the delay time set for each strobe counts the clock with a counter,
Since the counting is stopped at the time of detection of the change point, the delay time can be set for many strobes almost simultaneously. As a result, a large number of strobes can be calibrated in a short time. Similarly, the delay time on the timing adjustment side of the output waveform is also counted by the counter using the strobe calibrated in this manner, and counting is stopped at the time of detection of the change point. Then, the timing correction of the output waveform can be easily adjusted in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram mainly showing a waveform generation unit and a determination unit of an IC tester to which the present invention is applied.

FIG. 2 is an explanatory diagram of a relationship between a timing of an input waveform to a determination circuit and a determination result.

FIG. 1 is a schematic diagram showing an overall configuration of a conventional IC tester.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Test processor (CPU), 2 ... Timing generation part, 3 ... Pattern generator (PG), 4 ... Multiplexer (MLPX), 5 ... Waveform generation part, 6 ... Driver part, 7
... Switching circuit section, 8 ... Judgment section, 9 ... Inspection result data processing section, 10 ... Device under test (DUT), 11 ... Switch circuit, 12, 13, 14 ... Switch, 15 ... Clock generation circuit, 16 ... Stop control Circuit, 17: reference waveform generation circuit, 18: reference waveform, 51, 51a, 51b, 51m,
51n, 51p ... waveform formatter (FMT), 53,
53a, 53b, 53m, 53n, 53p ... variable delay circuits, 61, 61a, 61b, 61m, 61n, 61p ...
Driver (DRV), 84, 84a, 84b, 84m ...
Variable delay circuits, 81, 81a, 81b, 81m... Analog comparators (ACOM), 82, 82a, 82b,
82m ... Digital comparator (DCOM), STB,
STa, STb, STi, STm: determination strobe pulse; 160, 160a, 160b, 160m: change point detection circuit.

Claims (2)

(57) [Claims] A plurality of counters for receiving a pulse generated in a predetermined cycle and counting the number of pulses, receiving a strobe pulse, giving a delay time corresponding to a count value of the counter to the strobe pulse, and outputting the same. A variable delay circuit, a reference waveform generating circuit that generates a reference waveform that changes from a high level to a low level or vice versa in synchronization with the strobe pulse; and a plurality of variable delay circuits provided corresponding to the plurality of variable delay circuits, respectively. Receive a strobe pulse passed through the variable delay circuit corresponding to the reference waveform, and determine whether the reference waveform is in a HIGH level or a LOW level at the timing of receiving the strobe pulse. And a plurality of comparators are provided corresponding to each of the plurality of comparators. Receiving the determination result from the comparator, detecting that the determination result has changed, and counting the count value of the counter for providing a delay time to the strobe pulse corresponding to the comparator having received the determination result in response to the detection. An IC tester comprising: a plurality of determination result change point detecting circuits for stopping the strobe pulse; and generating the strobe pulse at a predetermined cycle. 2. A circuit which is provided in correspondence with each of circuits for determining the generation timing of each of a plurality of output waveforms which change from a HIGH level to a LOW level or vice versa. A plurality of first variable delay circuits each receiving a timing pulse that determines the generation timing of the output waveform, giving a delay time corresponding to the count value of the counter to the timing pulse, and outputting the same. A plurality of first delay circuits each corresponding to each of the plurality of first delay circuits, each of which generates the output waveform whose waveform is shaped in accordance with the timing pulse output from the corresponding first variable delay circuit. An output circuit is provided corresponding to each of the plurality of output circuits, and is generated at the predetermined cycle. A plurality of second variable delays each receiving a pulse or another pulse and counting it, each receiving a strobe pulse, giving a delay time corresponding to the count value of the counter to the strobe pulse, and outputting the same. A strobe pulse provided from each of the plurality of output circuits, the strobe pulse being output from the second variable delay circuit corresponding to the input signal, and receiving the strobe pulse. A plurality of comparators for determining whether the signal waveform is in the HIGH level or the LOW level, and a reference waveform changing from the HIGH level to the LOW level or the opposite state is generated according to the strobe pulse. A reference waveform generating circuit to generate, from the reference waveform and the plurality of output circuits, Receiving each of the output waveforms, selecting one of them, and when selecting the output waveform, sending each output waveform as the input signal to the comparator corresponding to the output circuit that generated it, A selection circuit that, when a reference waveform is selected, sends the reference waveform as the input signal to each of the comparators; and a determination circuit provided corresponding to each of the plurality of comparators, each of which receives a determination result from the corresponding comparator. When the result has changed, the count value of the counter of the second variable delay circuit corresponding to the comparator having received the determination result in response to the detection when the selection circuit has selected the reference waveform. And when the selection circuit is selecting the output waveform, A plurality of determination result change point detection circuits for stopping the count value of the counter of the first variable delay circuit corresponding to the comparator having received the determination result in response to the determination result, and selecting the reference waveform by the selection circuit. Generating the strobe pulse at a predetermined cycle to stop the counter of the second variable delay circuit, selecting the output waveform by the selecting circuit, generating the strobe pulse at a predetermined cycle, and An IC tester for generating a waveform at the predetermined cycle or another predetermined cycle to stop a counter of the first variable delay circuit.