JP3059441B2 - Hadamard converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a Hadamard transformer for performing a Hadamard transform on a predetermined input matrix.

[Prior Art] FIG. 7 shows a general method of using an orthogonal transformer. In general, when performing a matrix operation of n rows and n columns, a buffer 1 for n lines for forming an input matrix is indispensable. The data of this n-line part is orthogonal transform 2
And the conversion result is output to the signal processing unit 3. Therefore, n data for one column are input to the orthogonal transformer 2 at a time.

FIG. 8 shows a configuration example of a conventional orthogonal transformer. Here, a 4 × 4 Hadamard transform is taken as an example for description, and a circuit configuration based on a high-speed Hadamard transform algorithm will be described. Latches 11a to 11p latch input of four elements for one column and output 4 × 4 elements in parallel. 12
Reference numerals a to 12d denote arithmetic units composed of adder / subtractor groups, and reference numeral 13 denotes an output latch. In order to realize this Hadamard transformation, 32 sets of latches and 64 adders / subtracters in the arithmetic units 12a to 12d are required.

Therefore, if each element is an 8-bit input, the output is
It becomes 10 bits, and only 196 pins are used for data input / output pins.
Was difficult. Further, driving the conventional orthogonal transformer required complicated control.

[Problems to be Solved by the Invention] The present invention provides a Hadamard converter that eliminates the above-mentioned drawbacks of the conventional example, reduces the scale of hardware, and performs high-speed arithmetic processing with a simple clock.

Means for Solving the Problems To solve this problem, a Hadamard transformer according to the present invention performs a Hadamard transform on a 2 × 2 input matrix to obtain a 2 × 2 output matrix. , An input means for sequentially inputting element signals arranged in a first direction of the input matrix and sequentially inputting element signals arranged in a second direction orthogonal to the first direction; A set of adder and subtractor for calculating the difference, performing a sum and difference operation between the element signals arranged in the first direction on the element signals input by the input means, A first conversion means for sequentially obtaining two conversion signals arranged in a first direction, and a set of an adder and a subtractor for calculating the sum and difference of the two elements; Select the obtained converted signal The force,
A sum and difference operation between the converted signals arranged in the second direction is performed, and two Hadamard transform coefficients are sequentially output two by two along the second direction, whereby 2 × 2 Hadamard transform coefficients are obtained. And second conversion means for obtaining a conversion coefficient.

A Hadamard transformer having another configuration according to the present invention has a 4 × 4
Hadamard transform is applied to the input matrix of
In a Hadamard transformer that obtains an output matrix of 4,
Input means for sequentially inputting element signals arranged in a first direction of the input matrix and sequentially inputting element signals arranged in a second direction orthogonal to the first direction; An adder and a subtractor for calculation are provided in two stages each of two sets, and the element signal input by the input means is
The sum and difference operations between the element signals arranged in the first direction are calculated by 2
A first conversion means for sequentially obtaining four conversion signals arranged in the first direction, and two sets of adders and subtractors for calculating the sum and difference of the two elements, two stages each; , Selecting and inputting the converted signal obtained by the first converting means, performing a sum and difference operation between the converted signals arranged in the second direction in two steps, and performing the calculation in the second direction. By outputting the four Hadamard transform coefficients sequentially four by four,
Second conversion means for obtaining 4 × 4 Hadamard transform coefficients.

[Example] Hereinafter, an example will be described. In this embodiment, a Hadamard transform will be described as an example.

First, the outline of the Hadamard transform is described. This is a linear transformation using a Hadamard matrix. Here, an example of the Hadamard transform of two rows and two columns is shown. Now, a matrix of 2 rows and 2 columns as shown in FIG. 9A is arranged in a one-dimensional vector X.

That is, X is X = [x ₁₁ , x ₁₂ , x ₂₁ , x ₂₂ ] ^T (1) where T represents a transposed matrix.

Thereto, and Y a result of performing a Hadamard transformation, and the two rows and two columns of the matrix as shown in the FIG. 9 (b) represents a one-dimensional vector using a Hadamard matrix of H ₂ 4 × 4 .

That is, Y is Y = [y ₁₁ , y ₁₂ , y ₂₁ , y ₂₂ ] ^T (2).

From the Hadamard transform equation Becomes

Where the Hadamard matrix H ₂ is It is. Therefore, each element of Y is obtained as follows.

_{y 11 = 1/2 (x} 11 + x 12 + x 21 + x 22) y 12 = 1/2 (x 11 + x 12 -x 21 -x 22) y 21 = 1/2 (x 11 -x 12 -x 21 + x ₂₂ ) y ₂₂ = 1/2 (x ₁₁ −x ₁₂ + x ₂₁ −x ₂₂ ) <First Embodiment> FIG. 1 is a configuration diagram of the orthogonal transformer of the first embodiment. 19
Is a terminal for inputting a clock from outside, 20 and 21 are terminals for taking in data of one column of an input matrix from an external line buffer, for example, two lines buffer, 22a and 22b are latches for latching input data, and 23 is a binomial adder. , 24 are binary term subtractors. 25a to 25e are latches for shifting and latching the output from the adder 23 or the subtractor 24, 26a and 26b are selectors, 27 is a binomial adder, 28 is a binomial subtractor, and 29a and 29b are results. , 30a and 30b are terminals for outputting a result, and 31 is a binary counter.

FIG. 2 is a timing chart showing the operation of the orthogonal transformer of the first embodiment. Each operation will be described according to the timing chart. A clock CLK is supplied from a terminal 19. Vector X from outside according to this clock
Is supplied for one column.

The rise of the first clock, the x ₁₁ as Input 1 from the terminal 20, to force the x ₂₁ from the terminal ₂₁ as Input 2.

The rise of the second clock, latch each element of x _11, x ₂₁ latches 22a, to 22b, to enter the x _12, x ₂₂ from the terminal 20, 21.

The third is the rise of the clock, by adding the latch 22a, the output of 22b contents x _11, x ₂₁ with binomial adder 23 obtains the (x ₁₁ + x _21), and subtracted binomial subtractor 24 (x ₁₁ -x ₂₁₎ the determined at the same time the latch 25a, which latch to 25b, latches x _12, x ₂₂ 22
Latch to a, 22b.

The rise of the fourth clock, the latch 25a, the contents of the output of _{25b (x 11 + x 21)} , (x 11 -x 21) the latch 25c, and latches to 25d, the second term adders 23 and binomial subtractor 24 output (x ₁₂ + x
₂₂ ) and (x ₁₂ −x ₂₂ ) are latched on the latches 25a and 25b. Here, the outputs of the selectors 26a and 26b are selected according to the output signal Sel ₁ of the binary counter 31. The selectors 26a and 26b
l When ₁ is "1", the contents of the latches 25d and 25e are output. Therefore, during this fourth clock, Sel1 is "0" and the latches 25a, 25
c is selected, and the outputs of the selectors 26a and 26b are (x
₁₂ + x _22), a (x ₁₁ + x _21). This output is summed with binomial adder 27, is further 1/2 actually be shifted one to the right, we obtain the _{1/2 (x 11 + x 12 +} x 21 + x 22), 2 Section subtractor 28 Is subtracted and halved to obtain 1/2 (x ₁₁ −x ₁₂ + x ₂₁ −x ₂₂ ).

At the rise of the fifth clock, the contents of the latch 25d (x ₁₁
−x ₂₁ ) is latched on the latch 25 e, and the contents (x ₁₂ + x ₂₂ ) and (x ₁₂ −x ₂₂ ) of the latches 25 a and 25 b are latched on the latches 25 c and 25 d. Further, half of the outputs of the binomial adder 27 and the binomial subtractor 28 obtained during the fourth clock are latched by the latches 29a and 29b and output from the output terminals 30a and 30b.

From the terminal _{30a, 1/2 (x 11 + x} 12 + x 21 + x 22), from the terminal _{30b, 1/2 (x 11 -x 12} + x 21 -x 22) is the result of the Hadamard transform of the vector Y y ₁₁ , y ₂₂
It is nothing less than. In this fifth clock, a binomial adder
27 and the binomial subtractor 28, the output of the latch 25d and 25e, which are selected by the selector 26a, 26b is _{input, 1/2 (x 11 + x 12} -x 21 -x 22) and 1/2 (x ₁₁ −x ₁₂ −x ₂₁ + x ₂₂ ).

Finally, at the rising edge of the sixth clock, these results are latched on the latches 29a and 29b, and y of the output vector Y is calculated.
_12, y ₂₁ as Monads 30a, is outputted from 30b.

When processing the next matrix continuously, the third clock of the processing of the previous matrix may be input from the outside through the terminals 20 and 21 as the first clock. Thus, the conversion process can be continuously performed.

Second Embodiment FIG. 3 is a configuration diagram of an orthogonal transformer according to a second embodiment. 53
a to 53d are terminals for taking in data of one column of the input matrix from the outside, 54a to 54d are latches for latching input data, 55a, 55b, 58a, 58b, 63a, 63b, 71a, 71b are 2 items Adders, 56a, 56b, 59a, 59b, 64a, 64b, 72a, 72b are binomial subtractors, 57a to 57d, 70a to 70d are latches for adjusting timing, and 60a to 60v are binomial adders 55a, 55b, 58a, binomial subtractor
A latch for shifting and latching the output from the first arithmetic unit consisting of 56a, 56b, 59a, 59b, and latches 57a to 57d;
61 and 75 are quaternary counters and decoders for controlling selectors, 62a to 62d are selectors, 70a to 70d are latches for adjusting timing, and 74a to 74d are ones of output matrices.
This is an output terminal that outputs the line.

4A to 4D are timing charts showing the operation of the orthogonal transformer of the second embodiment. Each operation will be described according to the timing chart. Here, the clock signal CLK is not shown in FIG. 3, but is input to each latch and counter. Now, assuming that each element of the input matrix has 8-bit data and the following input matrix is input, a quadrature transformer that performs Hadamard transform of 4 rows and 4 columns will be described as an example. 4 rows 4
The Hadamard matrix H of a column is as in the following equation (6).

An example of the input matrix M in hexadecimal is as follows.

First, referring to FIG. 4A, at the rising edge of the first clock, the four elements (A0,9) of the first column of the matrix M from the terminals 53a to 53d.
2,99,9C) is input. Thereafter, every time the clock advances, the second, third and fourth columns of M are input from the terminals 53a to 53d. Latches 54a to 54d latch the data of the first column of M at the rise of the second clock. Thereafter, every time the clock advances, the second, third and fourth rows are sequentially latched. At this time, binomial adder 5
5a, 55b, the binomial subtractors 56a, 56b respectively
Sum with the row (x _1i + x _2i ), sum of the third and fourth rows (x _3i + x
_4i ), the difference (x _1i −x _2i ) between the first and second rows and the difference (x _3i −x _4i ) between the third and fourth rows are determined.

At the rising edge of the third clock, the results of the first row are latched into latches 57a-57d, and thereafter, as the clock progresses, the second row and the third row are latched successively.
Term adders 58a, 58b and binomial subtractors 59a, 59b, _{respectively, (x 1i + x 2i +} x 3i + x 4i), (x 1i -x 2i + x 3i -x 4i), (x 1i + x 2i -x 3i - x _4i ) and (x _1i −x _2i −x _3i + x _4i ).

Hereinafter, it will move to FIG. 4B. At the rising edge of the fourth clock, the latches 60a to 60d latch the operation results in the first column. The result of the operation in the first column is latch 60e-60 at the rising edge of the fifth clock.
l. Latches 60i to 60e at the rising edge of the sixth clock and 60m to 60P at the rising edge of the seventh clock.

Hereinafter, it will move to FIG. 4C. At the rise of the eighth clock, the
The data in columns 2, 3, and 4 are latches 60g-60s, and the data in rows 3 and 4 at the rising edge of the ninth clock are latches 60t, 60u, and 10th.
At the rising edge of the clock, the data in the fourth row is latched to the latch 60v. Subsequently, the data in the second column is latched to the rising edge of the fifth clock, the data in the third column is latched to the rising edge of the sixth clock, and the data in the fourth column is latched to latches 60a to 60d at the rising edge of the seventh clock. , As well as a latch 60e-6
0h → Latch 60i ~ 60l → Latch 60m ~ Latch 60p → Latch 60
The gear shifts from g to 60s → latch 60t, 60u → latch 60v as the clock advances.

The counter 61 is "0" until the rising edge of the seventh clock.
Hereafter, it is a quaternary counter that counts up at the rising edge every time the clock advances. The output decoded by the decoder 75, the selector selection signal Sel ₂ of 4 bits. When the 4 bit 0th bit th selector signal Sel ₂ is "1", i.e. in the seventh clock, latch 60a, 60e, 60i, selects the output of 60 m. When the first bit is "1", that is, at the eighth clock, the outputs of the latches 60f, 60j, 60n, and 60q are selected. Hereinafter, when the second bit is "1", that is, at the ninth clock, the outputs of the latches 60k, 60o, 60r, and 60t are selected. When the third bit is "1", that is, at the tenth clock, the latch 60p is selected. , 60s,
Select 60u, 60v data.

Each of the data selected in this manner is converted into a binary adder 63a, 63
b and input to the binomial subtractors 64a and 64b to perform addition and subtraction. The output of each arithmetic unit is, for example, the time of the seventh clock, Hereinafter, the process moves to FIG. 4D. The above results are latched into latches 70a-70d. At the rise of the eighth clock, the first data is latched, and simultaneously, the binomial adders 71a and 71b and the binomial subtractors 72a and 72b perform addition and subtraction on the data latched by the latches 70a to 70d. And multiply by 1/4. Actually, it shifts two places to the right. The results are latched by latches 73a to 73d and output from output terminals 74a to 74d. Latch 73
In a to 73d, the first data is latched at the rising edge of the ninth clock. At this time, the contents of the latches 73a to 73d are as follows. Becomes This nothing but the first row _{y 11, y 12, y 13} , y 14 of the output matrix Y after Hadamard transform.

When processing the next matrix continuously, the fifth clock of the processing of the previous matrix is continuously input from the outside to the terminals 53a to 53d as the first clock of the subsequent matrix processing. One column, the result of the previous matrix is output at the rising edge of the next clock after the output is completed, and the first row of the output matrix of the subsequent matrix is continuously output.

Third Embodiment FIG. 5 is a configuration diagram of an orthogonal transformer according to a third embodiment. twenty one
9 is a terminal for inputting a clock from outside. Reference numerals 220 and 221 denote terminals for receiving data for one column of the input matrix from outside, reference numerals 222a and 222b denote latches for latching input data, reference numerals 223 and 227 denote binomial adders, and reference numerals 223 and 228 denote binomial subtractors. 225a to 225c are latches, 226a and 226b are selectors, 229a,
229b is a latch for latching output data, 230a and 230b are terminals for outputting the results latched on the latches 229a and 229b, 231
Is a binary counter.

This embodiment is used, for example, when the clock speed is sufficiently smaller than the delay in the element, or when a slight delay may occur with respect to the input.

FIG. 6 is a timing chart showing the operation of the orthogonal transformer of the third embodiment. Each operation will be described according to the timing chart. A clock CLK is supplied from a terminal 219.

At the rise of the first clock, data x ₁₁ and x ₂₁ for one column of the vector X are input as Input 1 and Input 2 from terminals 220 and 221.

The rise of the second clock, latch 222a, 222b is x _11, x
₂₁ was latch inputs x _12, x ₂₂ from the terminal 220, 221 at the same time.

The rise of the third clock, and output latch 222a, and adds the outputs binomial adder 223 222b a (x ₁₁ + x _21),
The binary term subtractor 224 performs subtraction and outputs (x ₁₁ −x ₂₁ ).

The rise of the fourth clock, the addition result (x ₁₁ + x ₂₁₎ and the subtraction result (x ₁₁ -x _21), latch 225a, and latches to 225b, further binomial adder 223 in addition result (x ₁₂ + x ₂₂₎ ,
The binary term subtractor 224 obtains a subtraction result (x ₁₂ −x ₂₂ ). Here, according to the output signal Sel ₃ of the binary counter 231, the selectors 226a and 226b select and output one of the two inputs. That third selector Between clock 226a, the output contents of 226b, respectively (x ₁₂ + x _22), a (x ₁₁ + x _21). This was entered in binomial adder 227,2 Section subtractor _{228, y 11 = 1/2} (x 11 + x 12 + x 21 + x 22) and _{y 22 = 1/2 (x} 11 -x 12 + x 21 -x ₂₂ ) get.

The fourth clock rising in's in the same manner, y _11, the y ₂₂ output latch 229a, and latches to 229b, the terminal 230a, and simultaneously output from 230b, the binomial adder 227,2 Section subtractor 228 (x ₁₂
−x ₂₂ ) and (x ₁₁ −x ₂₁ ), and y ₁₂ = 1/2 (x ₁₁ + x ₁₂ −x ₂₁ + x ₂₂ ), y ₂₁ = 1/2 (x ₁₁ −x ₁₂ −x ₂₁ + x ₂₂ ) get.

The y _21, y ₁₂ on the rising edge of the fifth clock latch 229a, 229b
And output from terminals 230a and 230b.

As described above, when an orthogonal transformer is created by using such a configuration, there is an effect of greatly reducing the number of cells (the number of gates) on an element or a gate array. Further, the clock speed of the orthogonal transformer may be 1 / n of the pixel clock speed, and the orthogonal transformer can be easily incorporated into another device without using a high-speed clock.

In this embodiment, the Hadamard transform is described as the orthogonal transform. However, it is obvious that the present invention can be easily applied to other orthogonal transforms by modifying the arrangement of the latches and the control of the selector.

[Effects of the Invention] As described above, according to the present invention, the Hadamard transform is performed on a 2 × 2 input matrix, and the sum and difference of two elements are calculated when a 2 × 2 output matrix is obtained. A sum and a difference between element signals arranged in the first direction with respect to the element signals input by the input means, and Are sequentially obtained, one set of an adder and a subtractor for calculating the sum and difference of the two elements are provided, and the conversion signal obtained by the first conversion means is selected. By inputting and performing a sum and difference operation between the converted signals arranged in the second direction, and sequentially outputting two Hadamard transform coefficients two by two along the second direction, 2 × 2 Obtain Hadamard transform coefficients. For this reason, the number of adders / subtractors can be minimized, the scale of hardware can be reduced more than before, and arithmetic processing can be performed at high speed with a simple clock.

Furthermore, the number of cells on the element or gate array The number of gates
The Hadamard converter that can be integrated into an IC can be provided by drastically reducing the power consumption.

According to another aspect of the present invention, an adder for calculating the sum and difference of two elements when performing a Hadamard transform on a 4 × 4 input matrix and obtaining a 4 × 4 output matrix. And two stages of two sets of subtracters, each of which performs a sum and difference operation between element signals arranged in the first direction on the element signals input by the input means in two stages, thereby obtaining the first signal. Four conversion signals arranged in the direction are sequentially obtained, two stages of adders and two subtracters for calculating the sum and difference of two elements are provided, and the conversion signal obtained by the first conversion means is provided. Is selected and input, and a sum and difference operation between the converted signals arranged in the second direction is performed in two stages, and four Hadamard transform coefficients are sequentially output four by four along the second direction. As a result, 4 × 4 Hadamard transform coefficients are obtained. Same effect as the case of the force matrix is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the orthogonal transformer of the first embodiment, FIG. 2 is a timing chart showing the operation of the orthogonal transformer of the first embodiment, and FIG. 3 is a diagram showing the orthogonal transformer of the second embodiment. FIGS. 4A to 4D are timing charts showing the operation of the orthogonal transformer of the second embodiment, FIG. 5 is a structural diagram showing the orthogonal transformer of the third embodiment, and FIG. FIG. 7 is a timing chart showing the operation of the orthogonal transformer of the third embodiment, FIG. 7 is a block diagram showing an example of how to use the orthogonal transformer, FIG. 8 is a diagram showing an example of the configuration of a conventional orthogonal transformer, FIG. The figure shows a 2 × 2 pixel block and its matrix after Hadamard transformation. In the figure, 1 ... line buffer, 2 ... orthogonal transformer, 3 ...
... Signal processing unit, 11a-11p ... Latch, 12a-12d ... Calculator consisting of adder / subtractor, 13 ... Output latch, 19,219 ...
... Clock terminals, 20, 21, 53a to 53d, 60a to 60v, 70a to 70d, 7
3a-73d, 222a, 222b, 225a-225c, 229b ... Latch, 23,2
7, 55a, 55b, 58a, 58b, 63a, 63b, 71a, 71b, 223, 227 ... binomial adder, 26a, 26b, 62a to 62d, 226a, 226b ... selector, 3
1,61,231 ... Counter, 75 ... Decoder, 30a, 30b, 74a
Up to 74d, 230a, 230b ... Output terminals, 24, 28, 56a, 56b, 59b, 64
a, 64b, 72a, 72b, 224, 228... are binomial subtractors.

Claims (2)

(57) [Claims] 1. A Hadamard transformer for performing a Hadamard transform on a 2 × 2 input matrix to obtain a 2 × 2 output matrix, wherein the element signals arranged in a first direction of the input matrix are arranged in parallel with each other. Input means for sequentially inputting element signals arranged in a second direction orthogonal to the first direction; and a set of an adder and a subtractor for calculating the sum and difference of the two elements. First conversion means for performing a sum and difference operation between element signals arranged in the first direction on an input element signal to sequentially obtain two conversion signals arranged in the first direction; And a set of an adder and a subtractor for calculating the sum and difference of the two elements, selecting and inputting the converted signals obtained by the first converting means, and arranging them in the second direction. The sum and difference operations between the converted signals are performed, and A second transformation means for sequentially outputting two Hadamard transform coefficients two by two along two directions to obtain 2 × 2 Hadamard transform coefficients. 2. A Hadamard transformer for performing a Hadamard transform on a 4 × 4 input matrix to obtain a 4 × 4 output matrix, wherein the element signals arranged in a first direction of the input matrix are arranged in parallel with each other. Input means for sequentially inputting element signals arranged in a second direction orthogonal to the first direction; two sets of adders and subtractors for calculating the sum and difference of the two elements; The sum and difference operations between the element signals arranged in the first direction are performed on the element signals input by the input means in two stages, and four converted signals arranged in the first direction are sequentially obtained. A first conversion unit, and two stages of adders and subtracters for calculating the sum and difference of the two elements, each of which has two stages, and selects and inputs the conversion signal obtained by the first conversion unit. , The sum between the converted signals arranged in the second direction and The difference operation is performed in two steps, and the second
And a second transforming means for sequentially outputting four Hadamard transform coefficients four by four along the direction of, thereby obtaining 4 × 4 Hadamard transform coefficients.