JP3057786B2 - Layout verification system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI layout verification system, and more particularly to a large-scale circuit connection verification system.

[0002]

2. Description of the Related Art A layout verification system includes a graphic dimension verification (DRC) and a circuit connection verification (LVS). Generally, layout data is composed of a data set called a cell, and the entire chip is also one cell.

[0003] Each cell is composed of a basic figure called pre-sensitive and lower-order cells as shown in FIGS. The basic figure includes a polygon having coordinates (X1, Y1) to (X6, Y6) as shown in FIG. 5A, and diagonal coordinates (X1, Y) as shown in FIG.
1), a rectangle (rectangle) having (X2, Y2) and coordinates (X1, Y2) having a predetermined path width D as shown in FIG.
Y1) to (X4, Y4) are shown with width lines (passes).

[0004] FIGS. 6 (a) is a layout diagram of a chip that include, but are cells A~D in the chip, this arrangement, as in FIG. 6 (b), in the cell A in the chip A hierarchical structure including cells C and D is shown. As other basic data, as shown in FIGS. 7A and 7B,
There are text and attributes attached to the layout graphic, which have character information and graphic information. That is, the figure
7 (a) to attribute AB is the text AB Figure 7 (b)) is
Here is an example .

FIG. 8 is a flowchart showing the procedure of a conventional circuit connection verification. First, in step 10, the cells to be inspected are hierarchically expanded and divided into only pre-sensitive cells. next,
In step 11, a graphic operation is performed. This graphic operation is executed by combining a logical sum (OR), a logical product (AND), and a logical difference (SUB) among the graphic operations as shown in FIGS. Resistance, M
OS capacitor) figure is created. Further, FIG. 9 (d)
Is performed, and circuit connection information is created.

This circuit connection information is called a netlist. FIG. 10 is a circuit diagram for explaining an example of this netlist. This circuit simulation system SP
The input data of the ICE is as follows.

[0007] M1 VDD AB VDD PMO
SL = 3 W = 20 M2 B A GND GND NMOS L = 2 W
= 10 At this time, if there is an attribute for the text or the node name, the name is output in the netlist, but for nodes that have neither, the node name is automatically created and output.

Finally, in step 13, this net list is compared with a previously prepared net list (normally, circuit simulation data).

[0009] At present, the problem of circuit connection verification is to increase the speed of a large scale. Normally, execution speed is 10 MIPS, main memory procedure is 32
A megabyte computer has a limit of 100,000 transistors and takes about 20 hours to execute. For this reason,
For large-scale layout verification, a method has been adopted in which verification is performed in order from the lower cell using a cell hierarchy.

[0010]

In the above-described conventional circuit connection verification using the layout data hierarchy, each cell does not always correspond to a part (partial circuit) of the prepared circuit, and each cell overlaps. However, there is a problem that an error cannot be found in the state where the error occurs.

An object of the present invention is to provide a layout verification system which can execute accurate circuit verification at high speed by dividing and executing circuit verification while eliminating these drawbacks.

[0012]

Layout verification system configuration of the SUMMARY OF THE INVENTION The present invention includes an extraction means for extracting a specified range of the circuit layout data as a window, the extracted hand
Order cell outer side of the window extracted by the step, dividing means for dividing the inner side of the window as a subordinate cell,
From the node name attribute with the terminal figure on the boundary of each window
A data generating means for nodal information data Ru is generated comprising a circuit verification and circuit verification of the subcells of the upper cell
Performs each division in association with the node information data
And wherein the Rukoto to have a verification means.

[0013]

FIG. 1 is a flowchart for explaining one embodiment of the present invention, and FIG. 2 is a layout diagram for explaining the embodiment of FIG. Here, windows A and B are cut out within the range of the layout specified in advance, and terminal figures C to E having node names (automatically generated) and attributes P. Has been added.

With this configuration, as shown in FIG. 3A, two-layer layout data (FIG. 3C) of lower cells in windows A and B and upper cells outside windows are created. FIG. 3B shows the layout in windows A and B.

In the flow of this embodiment (FIG. 1), the hierarchy is expanded in step 1 and the windows A,
Divide into B. These windows A and B are verified outside the upper cell window in step 3 and inside the lower cell window in step 4. These verifications are performed in the same procedure as in the conventional example (FIG. 8).

In this case, there is a possibility that a plurality of node names are originally given to one node via a terminal graphic. In this case, it is sufficient to prepare a node name correspondence table as shown in the following Table 1 in the equipotential tracking of the upper cell verification (step 3).

[0017]

That is, when a node name text or a node name attribute appears, it is stored in a node (NODE), and when the same potential is found, data (pointer) designating the corresponding text is written in a list (LIST). Attached.

Further, cutout window hollowed out, for example, a logical product of each Purishitibu regarded windows and graphics, it can <br/> be realized by executing a logical difference. In addition, it is assumed that the terminal graphic is included both inside and outside the window.

FIG. 4 is a layout diagram showing a second embodiment of the present invention. Here, the node name text is automatically added to the inside and outside of the window at the window boundary. This implementation
The example has an advantage that it is easy to see even after the window is divided because the example is text as compared with the first example .

[0021]

As described above, according to the present invention, the lower cell is set in the window and the upper cell is set outside the window, and node information data is generated at the boundary of the window to set the window in a range corresponding to the partial circuit. The circuit connection verification can be divided and executed. Normally, about 10 windows are possible. Therefore, if these partial circuits are verified in parallel, it is possible to increase the scale by about 10 times and to speed up the circuit connection verification and to execute at high speed. It has the effect of.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an embodiment of the present invention.

FIG. 2 is a layout diagram for explaining the embodiment of FIG. 1;

FIG. 3 is a layout diagram showing a hierarchical structure of the embodiment of FIG. 1;

FIG. 4 is a layout diagram showing a second embodiment of the present invention.

FIGS. 5A, 5B, and 5C are plan views showing three examples of pre-sensitivity.

FIGS. 6A and 6B are layout diagrams showing a hierarchical structure of layout data.

FIGS. 7A and 7B are layout diagrams showing an example of text and attributes shown in a layout graphic.

FIG. 8 is a flowchart of an example of a conventional circuit connection verification.

FIGS. 9A to 9D are schematic diagrams showing examples of graphic operations.

FIG. 10 is a circuit diagram illustrating input data of an example of a netlist of the circuit simulation system SPICE.

[Explanation of symbols]

 1-4, 10-13 Processing steps A, B Window C, D, E Terminal figure

Claims (2)

(57) [Claims] The method according to claim 1] specified range of the circuit layout data extraction means for extracting as a window, to the extraction means
More extracted upper cell outer side of the window, and dividing means for dividing the inner side of the window as the lower cell, consisting of the nodes name attributed terminal figure on the boundary of each window
A data generating unit that Ru is generated node information data, a circuit verification and circuit verification of the subcells of the upper cell the
Verification performed by dividing each corresponding to the node information data
Layout verification system according to claim Rukoto to have a means. 2. The layout verification system according to claim 1 , wherein the data generation means generates a node name text at each window boundary.