JP3055975B2 - Connection circuit between semiconductor integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection circuit for use in a semiconductor integrated circuit, and more particularly to a connection circuit for connecting an output signal of a CMOS type semiconductor integrated circuit to an input of a bipolar type semiconductor integrated circuit or a MOS type semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional connection circuit between a CMOS semiconductor integrated circuit and a bipolar semiconductor integrated circuit. In FIG. 6, the output buffer 4 of the CMOS type semiconductor integrated circuit is shown.
The output signal of the CMOS level voltage output from 0 is converted into an ECL level voltage of a bipolar semiconductor integrated circuit by using a level conversion element 50 having a bipolar structure, for example, a BiCMOS gate array as a connection circuit, The input was made to the input buffer 60 of the ECL level voltage of the bipolar semiconductor integrated circuit.

[0003]

A conventional connection circuit between a CMOS semiconductor integrated circuit and a bipolar semiconductor integrated circuit has a low operation speed due to a large load on an output circuit, and it is difficult to transmit signals at high speed. There were drawbacks. Also,
Since the level conversion element is used, it is necessary to insert a level conversion element in addition to the two semiconductor integrated circuits, and there is a disadvantage that power consumption increases.

An object of the present invention is to provide a connection circuit between semiconductor integrated circuits that can transmit signals at high speed and consumes less power by eliminating the above-mentioned disadvantages.

[0005]

According to the present invention, a first semiconductor integrated circuit, a second semiconductor integrated circuit, and an output signal of the first semiconductor integrated circuit are input to the second semiconductor integrated circuit. In the connection circuit between the semiconductor integrated circuits having signal propagation means, the signal propagation means is included in the first semiconductor integrated circuit, an input terminal to which an internal signal is input, and a power supply and a ground potential First and second N-channel MOS transistors connected in cascade, a first output terminal extracted from a common connection point of the first and second N-channel MOS transistors, and an input signal input to the input terminal And the first and second N-channel MOs
An output circuit including a first gate voltage circuit that applies gate voltages of opposite phases to the gate of the S transistor; and a first gate circuit of the second semiconductor integrated circuit to which an output terminal of the output circuit is connected. A first terminal resistor having one end connected to the input terminal and the other end connected to the ground potential.

Further, according to the present invention, in the connection circuit between the semiconductor integrated circuits according to the first aspect, the signal propagation means includes:
A reference signal output circuit included in the first semiconductor integrated circuit and having a second output terminal connected to a second input terminal of the second semiconductor integrated circuit and outputting a reference signal can be included.

In the present invention, the reference signal output circuit includes a third N-channel MOS transistor having a drain and a gate connected to the power supply, and a drain connected to a source of the third N-channel MOS transistor. A fourth N-channel MOS transistor having a gate connected to the power supply and a drain connected to the power supply, and a drain connected to the power supply and a gate connected to the third and fourth N-channel MOS transistors.
A fifth N-channel MOS transistor connected to a common connection point of the OS transistors, a drain connected to the source and the second output terminal of the fifth N-channel MOS transistor, a source connected to the ground potential, and a gate connected to the power supply. And a sixth N-channel MOS transistor connected to each other.

Further, the present invention provides a first semiconductor integrated circuit, a second semiconductor integrated circuit, and signal propagation means for inputting an output signal of the first semiconductor integrated circuit to the second semiconductor integrated circuit. In the connection circuit between semiconductor integrated circuits, the signal propagation means is included in the first semiconductor integrated circuit, and is cascaded between an input terminal to which an internal signal is input and a power supply and a ground potential. First and second P-channel MOS transistors, a first output terminal taken out from a common connection point of the first and second P-channel MOS transistors, and an input signal input to the input terminal. A first gate voltage circuit for applying gate voltages of mutually opposite phases to the gates of the first and second P-channel MOS transistors, and a first gate voltage circuit cascaded between the power supply and a ground potential. A and fourth P-channel MOS transistor, the third and fourth P-channel MOS
A second output terminal extracted from the common connection point of the transistors, and an input signal input to the input terminal,
A second gate voltage circuit for applying a gate voltage having the same phase as the gate voltage of the second and first P-channel MOS transistors to the gates of the third and fourth P-channel MOS transistors, respectively. When,
One end is respectively connected to the first and second input terminals of the second semiconductor integrated circuit to which the first and second output terminals of the output circuit are respectively connected, and the other end is connected to the power supply, respectively. And a first and a second terminating resistor.

Further, the present invention provides a first semiconductor integrated circuit, a second semiconductor integrated circuit, and signal propagation means for inputting an output signal of the first semiconductor integrated circuit to the second semiconductor integrated circuit. In the connection circuit between semiconductor integrated circuits, the signal propagation means is included in the first semiconductor integrated circuit, and is cascaded between an input terminal to which an internal signal is input and a power supply and a ground potential. First and second N-channel MOS transistors, a first output terminal extracted from a common connection point of the first and second N-channel MOS transistors, and an input signal input to the input terminal. A first gate voltage circuit for applying gate voltages of opposite phases to the gates of the first and second N-channel MOS transistors; and a third cascade-connected between the power supply and a ground potential. And a fourth N-channel MOS transistor; a second output terminal extracted from a common connection point of the third and fourth N-channel MOS transistors; and an input signal input to the input terminal. The second and first N-channel MOS transistors are respectively connected to the gates of the third and fourth N-channel MOS transistors.
An output circuit including a second gate voltage circuit for applying a gate voltage having the same phase as the gate voltage of the S transistor; and the second semiconductor integrated circuit to which first and second output terminals of the output circuit are connected, respectively. And third and fourth terminating resistors having one end connected to the first and second input terminals and the other end connected to the ground potential, respectively.

In the present invention, the first and second gate voltage circuits preferably include a connection line for directly connecting the input terminal to the gate of one of the MOS transistors, an input having an input to the input terminal and an output having the other MOS transistor. A first inverter circuit connected to the gate of the transistor.

Further, according to the present invention, in the first and second gate voltage circuits, an input is provided to the input terminal and an output is provided to one of the M terminals.
A second inverter circuit connected to the gate of the OS transistor; a third inverter circuit having an input connected to the input terminal; an input being an output of the third inverter circuit and an output being a gate of the other MOS transistor; And a fourth inverter circuit respectively connected to the third inverter circuit.

In the present invention, the first semiconductor integrated circuit is preferably a CMOS type semiconductor integrated circuit, and the second semiconductor integrated circuit is preferably a bipolar type semiconductor integrated circuit.

Further, in the present invention, it is preferable that the first semiconductor integrated circuit is a CMOS type semiconductor integrated circuit and the second semiconductor integrated circuit is a MOS type semiconductor integrated circuit.

In the present invention, it is preferable that the first semiconductor integrated circuit is a MOS type semiconductor integrated circuit, and the second semiconductor integrated circuit is a bipolar type semiconductor integrated circuit.

[0015]

The output circuit in the first semiconductor integrated circuit constitutes a push-pull amplifier, and the terminating resistor determines the input potential of the signal at the input terminal of the second semiconductor integrated circuit. In the case of a MOS transistor, VTN is set as the threshold voltage of the N-channel MOS transistor, and becomes an input potential VIH between (power supply voltage-VTN) and the ground potential. In the case of a P-channel MOS transistor, VTP is set to P The input potential VIL between VTP and the power supply voltage is set as the threshold voltage of the channel MOS transistor.

Accordingly, when the logic levels "1" and "0" are inputted to the input terminal of the output circuit, the logic amplitude of the input signal at the input terminal of the second semiconductor integrated circuit is determined by the N-channel MOS In the case of a transistor, the potential changes from the ground potential to the input potential VIH. In the case of a P-channel MOS transistor, the potential changes from the input potential VIL to the power supply voltage, and the input potential VIH or VIL becomes the threshold value of the input circuit of the second semiconductor integrated circuit. Logic "1" when higher than voltage
Is low, it can be determined that logic "0" has been input.

Further, for example, when the input circuit has first and second input terminals like a differential circuit,
By inputting a reference signal having an intermediate potential of the logic amplitude to the second input terminal by the reference signal output circuit, when the input potential to the first input terminal is higher than the intermediate potential, the logic “1” is output. , When it is low, it can be determined that logic “0” has been input. In this case, instead of the reference signal output circuit, the output circuit and a second output circuit whose output signals have opposite phases are provided, and the output signal is input to a second input terminal. In this case, when the input potential to the positive phase input terminal of the differential circuit is higher than the input potential to the negative phase input terminal, logic “1” is determined, and when it is low, logic “0” is determined.

Therefore, the logic amplitude of the first semiconductor integrated circuit is smaller than the power supply voltage, the rise and fall times are short, and the signal can be propagated at high speed.
Since signals can be propagated without using a level conversion element, power consumption can be reduced.

Furthermore, by using a MOS transistor of the same type as the output circuit as the reference signal generating circuit, the fluctuations in the potentials of the first and second input terminals are inclined in the same direction with respect to manufacturing variations and changes in the use environment. Therefore, they can cancel each other, and stable operation can be performed.

The first and second gate voltage circuits can be configured using one or three inverter circuits depending on the type of transistor pattern of the integrated circuit.

The first semiconductor integrated circuit may be a MOS or CMOS semiconductor integrated circuit, and the second semiconductor integrated circuit may be a bipolar or MOS semiconductor integrated circuit.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

The first embodiment is characterized by N-channel MOS transistors MN1 and MN
2, a push-pull output circuit 10 of a CMOS semiconductor integrated circuit as a first semiconductor integrated circuit including inverter circuits IV1, IV2 and IV3, and an input circuit of a bipolar semiconductor integrated circuit as a second semiconductor integrated circuit 30 and a terminating resistor R connected to the input terminal ID2 of the input circuit 30.

The input terminal ID1 of the output circuit 10 is connected to the input terminals of the inverter circuits IV1 and IV2. The output terminal of the inverter circuit IV1 is connected to the input terminal of the inverter circuit IV3.
And IV3 output terminals are N-channel MOS
Connected to the gates of transistors MN2 and MN1;
The source of N-channel MOS transistor MN2 is connected to the ground potential, the drain of N-channel MOS transistor MN1 is connected to the power supply potential, the source of N-channel MOS transistor MN1 is connected to the drain of N-channel MOS transistor MN2, It is connected to the output terminal OD1 of the MOS type semiconductor integrated circuit. Further, the output terminal OD1 of the output circuit 10 and the input terminal ID2 of the input circuit 30 are connected, and are connected to the ground potential via the terminating resistor R. Here, the inverter circuits IV1, IV
2 and IV3 constitute a gate voltage circuit.

Next, the operation of the first embodiment will be described.

When a logic level "1" is input to the input terminal ID1 of the output circuit 10, the N-channel MOS transistor MN1 is turned on, and the output signal potential of the output circuit 10 becomes (power supply potential-N-channel MOS transistor). MN
1 threshold voltage VTN), but the input circuit 30
The input potential of the input terminal ID2 is the potential VIH between (power supply voltage-VTN) and the ground potential depending on the resistance value of the terminating resistor R.
become.

On the other hand, when a logic level "0" is input to input terminal ID1 of output circuit 10, N-channel MOS transistor MN2 is turned on, and the output signal potential of output circuit 10 drops to the ground potential.

That is, the input terminal ID2 of the input circuit 30
Has a logic amplitude of VIH from the ground potential, the logic "1" when the potential of the input terminal ID2 of the input circuit 30 is higher than the threshold potential of the input circuit 30, and the logic "0" when the potential of the input terminal ID2 is low. Is determined to have been input.

As described above, in the first embodiment, C
An N-channel push-pull circuit is used as an output circuit of a first semiconductor integrated circuit having a MOS structure, and the output circuit is connected to an input circuit of a second semiconductor integrated circuit having a bipolar structure or a MOS structure. The conversion can be made to the level of the second semiconductor integrated circuit having the bipolar structure or the MOS structure without using it.

Further, by making the logic amplitude of the output circuit smaller than the power supply voltage, the rise and fall time becomes shorter, so that the signal can be propagated at a higher speed than in the prior art.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In the second embodiment, as the output circuit 10a,
In the output circuit 10 of the first embodiment shown in FIG. 1, the inverter circuit IV3 is not a gate circuit of the N-channel MOS transistor MN1 but a gate circuit of the N-channel MOS transistor MN2. is there.

The operation of the second embodiment differs from that of the first embodiment only in that an output signal having an opposite phase to that of the first embodiment is output with respect to the level of the input signal input to the input terminal ID1. The same operation as in the embodiment is performed.

In the circuits shown in FIGS. 1 and 2,
Of course, the gate voltage circuit performs the same operation even when the two sides of the inverter circuit directly connect the input terminal ID1 and the gate without the inverter circuit. This is the same in the embodiments described later.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

The third embodiment differs from the first embodiment shown in FIG.
In the case (a), a CMOS semiconductor integrated circuit is used as the first semiconductor integrated circuit in addition to the output circuit 10 and an N-channel MOS transistor MN which is a feature of the present invention.
3, a reference signal output circuit 20 including MN4, MN5 and MN6.

The drain and gate of the N-channel MOS transistor MN3 of the reference signal output circuit 20,
The gate of the channel MOS transistor MN4, the drain of the N-channel MOS transistor MN5, and the gate of the N-channel MOS transistor MN6 are connected to the power supply, and the source of the N-channel MOS transistor MN4 and the N
The source of channel MOS transistor MN6 is connected to the ground potential. The source of N-channel MOS transistor MN3 and the drain of N-channel MOS transistor MN4 are connected to the gate of N-channel MOS transistor MN5.
And the drain of N-channel MOS transistor MN6 are connected to output terminal OD2. The output terminal OD2 is connected to the second input terminal ID3 of the input circuit 30a to which the negative-phase input terminal of the differential amplifier 31 is connected.

Next, the operation of the third embodiment will be described. The operation of the output circuit 10 is the same as that of the first embodiment, and the logical amplitude of the input signal of the input terminal ID2 of the input circuit 30a is between VIH ｛(power supply voltage -VTN) and the ground potential. It becomes potential｝.

Next, in the reference signal output circuit 20, N
The gates of the channel MOS transistors MN3 and MN4 are both connected to the power supply,
3 and MN4 are always in the "ON" state, and the potential of the gate of N-channel MOS transistor MN5 is a potential between (power supply voltage-threshold voltage of N-channel MOS transistor MN3) and the ground potential. It is determined by the resistance ratio between the source-drain electrodes of MN3 and MN4. Similarly, N-channel MOS transistors MN5 and MN6 are both in the "ON" state, and the signal potential of output terminal OD2 is a potential between (power supply voltage-threshold voltage of N-channel MOS transistor MN5) and the ground potential. And the N-channel MOS transistor M
Although determined by the resistance ratio between the source-drain electrodes of N5 and MN6, the potential of the input terminal ID2 of the input circuit 30a is set by setting it to be the intermediate potential of the logical amplitude of the input terminal ID1 of the output circuit 10. A logic "1" can be detected when the potential is higher than the potential of the input terminal ID3, and a logic "0" can be detected when the potential is lower than the potential of the input terminal ID3.

In the third embodiment, the output terminals OD1 and OD2 of the CMOS semiconductor integrated circuit are connected to the input terminals ID2 and ID of the bipolar semiconductor integrated circuit, respectively.
3 and furthermore, the output circuit 10 and the reference signal output circuit 20 of the CMOS semiconductor integrated circuit are all composed of only N-channel MOS transistors. Fluctuations in the potential of the input terminal ID2 and the potential of the input terminal ID3 of the integrated circuit are inclined in the same direction, so that there is an advantage that they can cancel each other.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

The fourth embodiment is characterized in that P-channel MOS transistors MP1, MP2,
MP3 and MP4 and inverter circuits IV11 and IV
The difference between the output circuit 10b of the CMOS type semiconductor integrated circuit as the first semiconductor integrated circuit and the bipolar type semiconductor integrated circuit as the second semiconductor integrated circuit including the elements 12, 13, IV13, IV14, IV15 and IV16. It includes an input circuit 30a including a dynamic amplifier 31, and termination resistors R1 and R2 connected to input terminals ID2 and ID3 of the input circuit 30a, respectively. Here, the differential amplifier 3
One positive-phase input terminal is connected to the input terminal ID2, and the negative-phase input terminal is connected to the input terminal ID3.

The input terminal ID1 of the output circuit 10b
Are connected to the input terminals of inverter circuits IV11, IV12, IV13 and IV14,
12 is connected to the input terminal of the inverter circuit IV15, and the output terminals of the inverter circuits IV11 and IV15 are connected to the P-channel MOS transistor MP1 respectively.
And the gate of MP2, the source of P-channel MOS transistor MP1 is connected to the power supply, the drain of P-channel MOS transistor MP2 is connected to the ground potential, and the drain of P-channel MOS transistor MP1 is the source of P-channel MOS transistor MP2. To the output OD1 of the CMOS semiconductor integrated circuit. The output terminals of inverter circuits IV16 and IV14 are connected to the gates of P-channel MOS transistors MP3 and MP4, respectively, and the source of P-channel MOS transistor MP3 is connected to the power supply.
The drain of the S transistor MP4 is connected to the ground potential, the drain of the P-channel MOS transistor MP3 is connected to the source of the P-channel MOS transistor MP4, and serves as the output terminal OD2 of the CMOS semiconductor integrated circuit. Here, inverter circuits IV11, IV12 and IV15 constitute a first gate voltage circuit, and inverter circuits IV13, IV14 and IV16 constitute a second gate voltage circuit.

The output terminal OD1 of the output circuit 10b
Is connected to the input terminal ID2 of the input circuit 30a, and further connected to the power supply via the terminating resistor R1.
b output terminal OD2 and input circuit ID of input circuit 10b
Are connected, and further connected to a power supply via a terminating resistor R2.

Next, the operation of the fourth embodiment will be described.

The output circuit 10b has four P-channel MOSs.
A push-pull amplifier using transistors is configured. When a logic level “0” is input to the input terminal ID1 of the output circuit 10b, the P-channel MOS transistors MP2 and MP3 are turned on. When the P-channel MOS transistor MP2 is turned on, the signal potential of the output terminal OD1 of the output circuit 10b drops to the threshold voltage VTP of the P-channel MOS transistor MP2, but the input potential of the input terminal ID2 of the input circuit 30a becomes The potential becomes VIL between VTP and the power supply voltage depending on the resistance value of the terminating resistor R1. On the other hand, when the P-channel MOS transistor MP3 is turned on, the output circuit 10b
The signal potential of the output terminal OD2 rises to the power supply potential.

When a logic level "1" is input to input terminal ID1, P channel MOS transistors MP1 and MP4 are turned on. When the P-channel MOS transistor MP1 is turned on, the output terminal OD1
Signal potential rises to the power supply potential. P-channel MO
When the S-transistor MP4 is turned on, the signal potential of the output terminal OD2 becomes the P-channel MOS transistor M
Although the voltage drops to the threshold voltage VTP of P4, the input circuit 30
The input potential of the input terminal ID3a becomes the potential VIL between VTP and the power supply voltage depending on the resistance value of the terminating resistor R2.

That is, the input terminal ID of the input circuit 30a
The logical amplitude of the input signal between 2 and ID3 changes from VIL to the power supply potential.

Input circuit 3 of bipolar semiconductor integrated circuit
0a includes the differential amplifier 31 and the input terminal ID2
The logic "1" is detected when the potential of the input terminal ID3 is higher than the potential of the input terminal ID3, and the logic "0" is detected when the potential of the input terminal ID3 is lower than the potential of the input terminal ID3.

In this way, the propagation signal can be converted to the level of the bipolar semiconductor integrated circuit without using a level conversion element, and the rise and fall times can be reduced by making the logic amplitude smaller than the power supply voltage. By making the length shorter, signal propagation can be performed at higher speed than before.

FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention.

The fifth embodiment is characterized in that N-channel MOS transistors MN11 and MN1 are characterized by the present invention.
2, an output circuit 10c including MN13 and MN14 and inverter circuits IV21, IV22, IV23, IV24, IV25 and IV26, and an input circuit 30a or 30b including a differential amplifier 31 or 32, respectively.
And termination resistors R3 and R4 or R5 and R6.

Here, the output circuit 10c is configured in a CMOS type semiconductor integrated circuit as a first semiconductor integrated circuit, and has an input terminal ID1 and output terminals OD1 and OD2. On the other hand, the input circuit 30a or 30b is configured in a bipolar semiconductor integrated circuit as a second semiconductor integrated circuit, and has input terminals ID2 and ID2, respectively.
3 or ID4 and ID5.

The input terminal ID1 of the output circuit 10c
Is connected to the input terminals of inverter circuits IV21, IV22, IV23 and IV24, and inverter circuit IV2
2 is connected to the input terminal of inverter circuit IV25, and the output terminals of inverter circuits IV21 and IV25 are connected to N-channel MOS transistor MN1 respectively.
1 and the gates of MN12 and N-channel MO
The drain of the S transistor MN11 is connected to a power supply,
The source of N-channel MOS transistor MN12 is connected to the ground potential, and N-channel MOS transistor MN1
1 is connected to the drain of the N-channel MOS transistor MN12 and further connected to the output terminal OD1. The output terminals of inverter circuits IV26 and IV24 are connected to the gates of N-channel MOS transistors MN13 and MN14, the drain of N-channel MOS transistor MN13 is connected to the power supply, and the source of N-channel MOS transistor MN14 is connected to the ground potential. , N-channel MOS transistor MN13 has a source connected to the drain of N-channel MOS transistor MN14 and further connected to output terminal OD2.
Here, inverter circuits IV21, IV22 and IV
25 constitutes a first gate voltage circuit, and inverter circuits IV23, IV24 and IV26 constitute a second gate voltage circuit.

The output terminal OD1 of the output circuit 10c
And the input terminal ID2 of the input circuit 30a or the input circuit 3
0b is connected to the input terminal ID4 of the output circuit 10c and the input terminal ID3 of the input circuit 30a or the input terminal ID5 of the input circuit 30b is connected to the ground potential via the terminating resistor R3 or R5. Connected to the ground potential via the terminating resistor R4 or R6.

Next, the operation of the fifth embodiment will be described.

The output circuit 10c has four N-channel MOSs.
A push-pull amplifier using transistors is configured. When a logical level “1” is input to the input terminal ID1 of the output circuit 10c, the N-channel MOS transistors MN12 and MN13 are turned on. When the N-channel MOS transistor MN12 is turned on, the signal potential of the output terminal OD1 of the output circuit 10c drops to the ground potential. On the other hand, N-channel MOS transistor M
When N13 is turned on, the signal potential of the output terminal OD2 changes from the power supply voltage to the N-channel MOS transistor MN1.
3, but the input potential of the input terminal ID2 of the input circuit 30a is equal to the termination resistance RTN.
With the resistance value of 3, the potential becomes VIH between (power supply potential-VTN) and the ground potential. When a logic level “0” is input to input terminal ID1 of output circuit 10c, N-channel MOS transistors MN11 and MN14 are turned on. N channel MOS transistor MN1
1 is turned on, the potential of the output terminal OD1 rises to (power supply potential−threshold voltage VTN), but the input potential of the input terminal ID2 of the input circuit 30a changes to the terminating resistance R3.
Becomes the potential VIH between (power supply potential-VTN) and the ground potential. When the N-channel MOS transistor MN14 is turned on, the output circuit 10
The signal potential of the output terminal OD2 of c drops to the ground potential.

That is, the input terminal ID of the input circuit 30a
The logic amplitude of the input signal between ID2 and ID3 changes from VIH to the ground potential. The input circuit 30a includes a differential amplifier 31, and detects logic "1" when the potential of the input terminal ID2 is higher than the potential of the input terminal ID3, and detects logic "0" when the potential of the input terminal ID2 is lower than the potential of the input terminal ID3.

In this manner, the propagation signal can be converted to the level of a bipolar or CMOS semiconductor integrated circuit without using a level conversion element, and the logic amplitude can be made smaller than the power supply voltage. As a result, the rise and fall times are shortened, so that the signal can be propagated at a higher speed than before.

The fifth embodiment shows a case where the output circuit 10c is connected to the input circuit 30a or 30b, and shows that the value of the terminating resistor is set according to the connected input circuit. It is a thing.

In the above embodiments, the first semiconductor integrated circuit is a CMOS semiconductor integrated circuit and the second semiconductor integrated circuit is a bipolar semiconductor integrated circuit. And MO
The same applies to the S type.

[0063]

As described above, the present invention provides a CMOS or MOS first semiconductor having a push-pull type output circuit for outputting a positive logic or a negative logic of an input signal input to an input terminal. An output signal of the output circuit is connected to an input terminal of the second semiconductor integrated circuit between the integrated circuit and a MOS-type or bipolar-type second semiconductor integrated circuit, and a power supply or a ground is connected through a terminating resistor. By connecting to a potential and performing signal propagation, there is an effect that signal propagation at different levels can be performed without using a level conversion element. Further, by making the logic amplitude smaller than the power supply voltage, there is an effect that signal propagation can be performed at a higher speed than in the related art. Further, by adding a reference signal generating circuit composed of MOS transistors of the same type as the output circuit, there is an effect that stable signal propagation can be performed without being affected by manufacturing variations of semiconductor integrated circuits or use environment conditions.

Therefore, according to the present invention, with low power consumption,
A connection circuit between semiconductor integrated circuits that can perform higher-speed and more stable signal propagation can be realized, and the effect is great.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a conventional example.

[Explanation of symbols]

10, 10a, 10b, 10c Output circuit 20 Reference signal output circuit 30, 30a, 30b Input circuit 31, 32 Differential amplifier 40 Output buffer 50 Level conversion element 60 Input buffer ID1 to ID5 Input terminals IV1 to IV3, IV11 to IV16, IV21-IV
26 inverter circuits MN1 to MN6, MN11 to MN14 N channel M
OS transistor MP1 to MP4 P channel MOS transistor OD1, OD2 Output terminal R, R1 to R6 Terminating resistor

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masahiro Wakana 5-29-11 Shiba, Minato-ku, Tokyo Inside NEC Telecom System Corporation (72) Inventor Hiroyuki Okamoto 2 Raijin, Yoshioka, Yamato-cho, Kurokawa-gun, Miyagi Prefecture Miyagi NEC Corporation (72) Inventor Kiyohiko Chiba Miyagi Japan (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 19/0175

Claims (10)

(57) [Claims] 1. A semiconductor device comprising: a first semiconductor integrated circuit; a second semiconductor integrated circuit; and signal propagation means for inputting an output signal of the first semiconductor integrated circuit to the second semiconductor integrated circuit. In a connection circuit between integrated circuits, the signal propagation means is included in the first semiconductor integrated circuit, and an input terminal to which an internal signal is input, and first and second cascade-connected between a power supply and a ground potential. Two N-channel MOS transistors, a first output terminal taken out from a common connection point of the first and second N-channel MOS transistors, and an input signal input to the input terminal; An output circuit including a first gate voltage circuit that applies gate voltages of opposite phases to the gate of the second N-channel MOS transistor; and the first circuit connected to an output terminal of the output circuit. A connection circuit between semiconductor integrated circuits, comprising: a first terminating resistor having one end connected to a first input terminal of the two semiconductor integrated circuits and the other end connected to a ground potential. 2. The connection circuit between semiconductor integrated circuits according to claim 1, wherein said signal propagation means is included in said first semiconductor integrated circuit, and a second output terminal is provided in said second semiconductor integrated circuit. A connection circuit between semiconductor integrated circuits, comprising a reference signal output circuit connected to a second input terminal of the circuit and outputting a reference signal. 3. A reference signal output circuit comprising: a third N-channel MOS transistor having a drain and a gate both connected to the power supply; a drain at a source of the third N-channel MOS transistor; and a source at a ground potential. A fourth N-channel MOS transistor having a gate connected to the power supply, and a fifth N-channel having a drain connected to the power supply and a gate connected to a common connection point of the third and fourth N-channel MOS transistors, respectively. M
An OS transistor and a sixth N-channel MOS transistor having a drain connected to the source of the fifth N-channel MOS transistor and a source connected to the second output terminal and a gate connected to the power supply, respectively. 3. A connection circuit between the semiconductor integrated circuits according to 2. 4. A semiconductor device comprising: a first semiconductor integrated circuit; a second semiconductor integrated circuit; and signal propagation means for inputting an output signal of the first semiconductor integrated circuit to the second semiconductor integrated circuit. In a connection circuit between integrated circuits, the signal propagation means is included in the first semiconductor integrated circuit, and an input terminal to which an internal signal is input, and first and second cascade-connected between a power supply and a ground potential. Two P-channel MOS transistors, a first output terminal extracted from a common connection point of the first and second P-channel MOS transistors, and an input signal input to the input terminal; And a first gate voltage circuit for applying gate voltages of opposite phases to the gates of the second and P-channel MOS transistors; and third and fourth cascade-connected between the power supply and a ground potential. A channel MOS transistor, a second output terminal extracted from a common connection point of the third and fourth P-channel MOS transistors, and an input signal input to the input terminal. An output circuit including: a second gate voltage circuit for applying a gate voltage having the same phase as the gate voltage of the second and first P channel MOS transistors to the gate of the P channel MOS transistor; First and second terminals each having one end connected to the first and second input terminals of the second semiconductor integrated circuit to which the first and second output terminals are respectively connected and the other end connected to the power supply, respectively. A connection circuit between semiconductor integrated circuits, comprising: 5. A semiconductor device comprising: a first semiconductor integrated circuit; a second semiconductor integrated circuit; and signal propagation means for inputting an output signal of the first semiconductor integrated circuit to the second semiconductor integrated circuit. In a connection circuit between integrated circuits, the signal propagation means is included in the first semiconductor integrated circuit, and an input terminal to which an internal signal is input, and first and second cascade-connected between a power supply and a ground potential. Two N-channel MOS transistors, a first output terminal taken out from a common connection point of the first and second N-channel MOS transistors, and an input signal input to the input terminal for receiving the first and second N-channel MOS transistors. A first gate voltage circuit for applying gate voltages of opposite phases to the gate of the second N-channel MOS transistor; and third and fourth N-channel transistors cascaded between the power supply and the ground potential A third MOS transistor, a second output terminal extracted from a common connection point of the third and fourth N-channel MOS transistors, and an input signal input to the input terminal. A second gate voltage circuit for applying a gate voltage having the same phase as the gate voltages of the second and first N-channel MOS transistors to the gates of the N-channel MOS transistors, respectively. Third and fourth terminals each having one end connected to the first and second input terminals of the second semiconductor integrated circuit to which the first and second output terminals are respectively connected and the other end connected to the ground potential, respectively. A connection circuit between semiconductor integrated circuits, including a terminating resistor. 6. The first and second gate voltage circuits include a connection line that connects the input terminal directly to a gate of one MOS transistor, an input having the input terminal and the output having a gate connected to the other MOS transistor. The connection circuit between the semiconductor integrated circuits according to claim 1, further comprising a first inverter circuit connected thereto. 7. The first and second gate voltage circuits include a second inverter circuit having an input connected to the input terminal and an output connected to the gate of one MOS transistor, and an input connected to the input terminal. 6. A third inverter circuit having a third inverter circuit having an input connected to the output of the third inverter circuit and an output connected to the gate of the other MOS transistor.
The connection circuit between the semiconductor integrated circuits described in any one of the above. 8. The semiconductor device according to claim 1, wherein said first semiconductor integrated circuit is a CMOS semiconductor integrated circuit, and said second semiconductor integrated circuit is a bipolar semiconductor integrated circuit. Connection circuit between semiconductor integrated circuits. 9. The semiconductor integrated circuit according to claim 1, wherein the first semiconductor integrated circuit is a CMOS type semiconductor integrated circuit, and the second semiconductor integrated circuit is
The connection circuit between semiconductor integrated circuits according to any one of claims 1 to 7, which is an OS-type semiconductor integrated circuit. 10. The semiconductor integrated circuit according to claim 1, wherein the first semiconductor integrated circuit is a MOS semiconductor integrated circuit, and the second semiconductor integrated circuit is a bipolar semiconductor integrated circuit.
The connection circuit between the semiconductor integrated circuits according to any one of the above.