JP3054395B2 - ATM switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ATM (Asynchronou).
s Transfer Mode (asynchronous transfer mode). INDUSTRIAL APPLICABILITY The present invention is suitable for use in an ATM switch requiring a large-scale and high-throughput characteristic used in an ATM switching device. In particular, the present invention relates to a technology for flexibly responding to traffic demand and scalably expanding the entire switch by using a cross-point switch that connects and opens and closes a junction between an input line and an output line with a cross-point LSI.

[0002]

2. Description of the Related Art Conventionally, a crosspoint switch architecture has a structure corresponding to an arrangement position of a cell buffer.
They can be broadly classified into output buffer type switches, input buffer type switches, and input / output buffer type switches.

When the number of switch input lines is M, an output buffer type switch writes cells into a cell buffer arranged on an output line at a speed M times the input line speed. The switch becomes large-scale because it requires a cross-point LSI and a transmission line that operate at M times the size of the above. In particular, if the switch cannot be realized with a one-chip LSI, it is difficult to mount the switch and a large-scale switch cannot be realized. There is.

On the other hand, the input buffer type switch has the advantage that the operation speed inside the switch can be made equal to the input / output line speed because the cell buffer is provided on the input side, and the switch can be easily mounted even if the switch scale is increased. However, in terms of traffic characteristics, there is a case where the throughput and delay characteristics are significantly deteriorated due to a head-of-line blocking effect in which a subsequent cell is not output due to competition between head cells aiming at the same output port.

FIG. 9 is a diagram showing a conventional input / output buffer type cross point switch. Conventionally, in order to increase the scale of a switch, buffers as shown in FIG. 9 are arranged at both input and output portions of the cross point, and the internal operation speed of the switch is twice (2C) the input line speed (C). An input / output buffer type cross point switch that has been raised to a certain extent is employed.

In this switch, a transmission cell is determined by arbitration between cell buffers on the input side.
When the switch scale increases and the number of input lines increases, it becomes impossible to transmit information between input cell buffers within one cell time. Therefore, it is difficult to select a cell transmission buffer by one arbitration.

FIG. 10 is a diagram showing a method of dividing an arbitration range in a conventional input / output buffer type cross point switch. Therefore, as shown in FIG. 10, the arbitration range is divided in the switch, the switching is independently performed in the same group, and the output buffer in the group is written once, and then the output buffer between the groups is output. By performing the cell read control, it is possible to cope with an increase in the switch scale.

[0008]

SUMMARY OF THE INVENTION Such a conventional AT
In the M switch, as shown in FIG. 11, it is necessary to perform output contention control between buffers between blocks aiming at the same output line. FIG. 11 is a diagram for explaining contention control between blocks for transmitting cells to an output line. For example, considering the competitive control of the cell transmission between the block k-1 and the block k + 1, the cell whose output is selected by the cell transmission competition control circuit 10 in the block k-1 is the block k.
The cell is sent to the relay buffer 20 of.

Further, in order to transmit a cell to the downstream block, it is necessary to issue a cell transmission request to the cell transmission competition control circuit 10 in the block k. At this time, the cell transmission competition control circuit 10 in the block k performs contention control between the output buffer 2 of the block k and the relay buffer 20, selects a transmission cell, and further transfers the cell to the relay buffer 20 of the downstream block k + 1. Send out.

[0010] By repeating this process, the cell is transferred to the target output line. When cells are transferred between blocks by such control, complicated control is performed by the cell transmission contention control circuit 10 that determines cell transmission within a block in order to maintain fairness in cell transmission between blocks. Is required.

For example, in order to maintain the fairness of the delay time between blocks, a timer is used to add a time stamp to a cell entering the block, and the cell transmission conflict control circuit 10
Compares the time stamp of the cell in the relay buffer 20 with the time stamp at the head of the output buffer 2, and when the values of the time stamps are different, it is necessary to select the smaller cell as the time stamp. In some cases, it is necessary to perform control to select a transmission cell by applying a weight depending on a block position from upstream to a cell of the relay buffer 20 and a head cell of the output buffer.

For this reason, it is necessary to provide a control circuit for performing complicated contention control for each block, and it is difficult to realize this in an LSI having a small circuit size. In addition, in order to transfer cells output to the target output line between the blocks according to the result of the closed contention control in each block, it is necessary to provide a path for cells transferred from the upstream in the block. However, there is a problem that the circuit becomes complicated.

The present invention has been made in view of such a background, and has as its object to provide an ATM switch which does not require complicated control of cell contention and provision of redundant cell transfer routes. An object of the present invention is to provide an ATM switch capable of expanding the switch size in an asymmetric manner. An object of the present invention is to provide an ATM switch in which traffic characteristics do not change with expansion. An object of the present invention is to provide an ATM switch that can accommodate traffic of various quality of service classes.

[0014]

According to the present invention, an mxn input / output buffer type cross point ATM switch is used as a basic unit switch, and this basic unit switch has an extended output terminal on the extension of the output signal line of the input buffer. It is characterized by having.

Further, according to the present invention, in order to increase the switch scale, an arbitrary number of basic unit switches are connected to extended output terminals to form an m × pn block, and the switch size m × pn blocks are connected in parallel. The present invention is characterized in that q switches are connected to form a crosspoint ATM switch having a switch size of qm × pn.

At this time, m and n are limited by the mounting conditions such as the LSI size, but since the values of p and q can be set arbitrarily, the cross point A of an arbitrary switch size M × N can be set.
The most important feature is that the TM switch can be realized in a scalable manner.

The difference from the conventional technique is that an extended block is connected in parallel, so that no extra cell transfer route is required inside the switch.

The present invention further comprises means for connecting output buffers for the same output line between the blocks in parallel, and for issuing a cell transmission request to each output buffer. The controller for controlling the suspension can have a function of transmitting cells to the output line. At this time, a controller that can programmably determine an output buffer permitting cell transmission from a plurality of output buffers having a cell transmission request for the same output line may be provided.

As described above, since the cell transmission buffer can be determined by a simple buffer selection rule, there is no need for a complicated cell selection control circuit, and an output buffer that permits cell transmission at one time by using one centralized controller is selected. What can be done is very different from the conventional technology.

That is, the present invention is an ATM switch, which is characterized by m input buffers for temporarily storing incoming cells, n output buffers for temporarily storing output cells, A basic unit including a cross point provided at a point where an output signal line of an input buffer and an input signal line of the output buffer intersect in a matrix, and an extended output terminal provided on an extension of the output signal line. The basic unit switches are arranged on the same plane in a cascade of p stages, and the extended output terminals are respectively connected to the inputs of the input buffers of the basic unit switches of the next stage. A basic unit switch plane having means for controlling contention of cells transferred to the same output buffer among the × p output buffers; The q switch planes are arranged in parallel, and the output of the i-th output buffer of the n × p output buffers of each basic unit switch plane is the i-th (≦ n × p) -th output buffer of the other basic unit switch plane. Q connected to the output of the output buffer and connected in parallel
There is a means for assigning a cell transmission right to each of the output buffers. Where i, m, n,
p and q are natural numbers.

The output buffer has means for transmitting a signal indicating that there is a cell to be transmitted in its own buffer, and the means for allocating the cell transmission right respectively comprises a cell transmission right of each output buffer. It may include means for responding to a transmission permission signal or a transmission rejection signal for the signal to be displayed so that the opportunities are equal,
Alternatively, the means for allocating each of the cell transmission rights includes:
The output buffer may include means for responding to a transmission permission signal or a transmission non-permission signal for the signal to be displayed so that the cell transmission opportunity of each output buffer follows a predetermined ratio.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1 and 2, and FIGS. FIG. 1 is a configuration diagram of an ATM switch according to an embodiment of the present invention. FIG. 2 is a configuration diagram of the basic unit switch according to the embodiment of the present invention. FIGS. 4 and 5 are diagrams for explaining cell contention control of the output buffer according to the first embodiment of the present invention. FIG. 6 is a diagram for explaining cell contention control of the output buffer according to the second embodiment of the present invention. Here, a description will be given assuming that m = n = 4, p = 2, and q = 3.

The present invention relates to an ATM switch, which is characterized in that, as shown in FIG. 2, four input buffers 1-1 to 1-4 for temporarily storing incoming cells, and a cell for outputting. Output buffers 2-1 to 2-1 for temporarily storing
2-4, a cross point 3 provided at a point where the output signal lines of the input buffers 1-1 to 1-4 and the input signal lines of the output buffers 2-1 to 2-4 intersect in a matrix. Extended output terminal 4-1 provided on extension of output signal line
1 to 4-4.
As shown in the figure, the basic unit switches 11 are arranged on the same plane in a two-stage cascade, and the extended output terminals 4-1 to 4-4 are connected to the input buffers 1-1 to 1-1- of the next-stage basic unit switch 11.
4 input buffers 1-
Eight output buffers 2 for (1-4) (4 × 2 =)
-1 to 2-8, the same output buffer 2-j (j is 1 to 2)
8) is provided with a basic unit switch plane 12 having an input buffer contention control unit 13 which is a means for performing contention control of cells transferred to any of the eight basic unit switch planes. Three basic unit switch planes 12 are arranged in parallel. The output of the i-th output buffer 2-i of the eight output buffers of each basic unit switch plane 12 is connected to the output of the i-th output buffer 2-i of the other basic unit switch plane 12, respectively. The output buffer contention control unit 14 is a means for allocating a cell transmission right to each of the three output buffers 2-i connected in parallel.

In the first embodiment of the present invention, as shown in FIG. 4, the output buffers 2-i-1 to 2-i-3 indicate when there is a cell to be transmitted in its own buffer. A cell transmission request processing section 15 is a means for transmitting a cell transmission request signal (req), which is a signal to be output to the output buffer.
The transmission response signal (Ack) or the transmission non-permission signal (Nack) is responded to the cell transmission request signal so that the cell transmission opportunities of -3 are even. Further, as shown in FIG. 5, the output buffer contention control unit 14 does not need to give a transmission right to the output buffer 2-i-2 to which the cell transmission request signal has not been transmitted, so that the cell transmission request The transmission right is transferred to the output buffer 2-i-3 to which the signal is being transmitted, and the invalid processing time is reduced.

In the second embodiment of the present invention, as shown in FIG.
-Respond to the transmission permission signal or the transmission non-permission signal with respect to the cell transmission request signal so that the cell transmission opportunities i-1 to 2-i-3 follow the predetermined ratio.

[0026]

(First Embodiment) A first embodiment of the present invention will be described with reference to FIG. FIG. 3 is a configuration diagram of the ATM switch according to the first embodiment of the present invention. In the first embodiment of the present invention, as shown in FIG.
The M switch is a basic unit switch 11, and three basic unit switches 11 are connected to the extended output terminals 4-1 to 4-4 to form a basic unit switch plane 12 having a switch size of 4 × (3 × 4). This is an example in which three basic unit switch planes 12 are connected in parallel to form a (3 × 4) × (3 × 4) extended crosspoint ATM switch.

As shown in FIG. 3, input lines I-1 to I-
4, when cells are input to the first input buffers 1-1 to 1-4, the input buffer conflict control unit 13 of the basic unit switch 11 looks at the destination of each head cell and checks the same output line O The cell output contention control operation is performed only between cells aiming at -k (k is any integer from 1 to 12) to determine an output cell.

When the cell output contention control is completed, the input buffer contention control unit 13 is accommodated in the input buffers 1-1 and 1-3 whose cell outputs have been recognized by the cell output contention control, and in the basic unit switch 11. Input buffers 1-2 and 1-4 containing cells destined for no output line
Is given a cell transmission permission.

The input buffers 1-1 to 1-1 which have obtained the cell transmission permission
1-4 send the cell to the output signal line. FIG. 7 is a diagram showing an address filter provided at the cross point.
As shown in FIG. 7, the address filter 1 is connected to the output signal line.
6, the cell having the destination “1” destined for the output line O- 1 is switched by the address filter 16 to the target outgoing path. The cell of destination "8", which is destined for the output line O-8, is not switched by the address filter 16 of the basic unit switch 11, but is transferred to the next basic unit switch 11 via the extended output terminal 4-1 as it is. Is done.

The cells transferred to the next stage are input buffers 1-1 to 1-4 arranged in the basic unit switch 11 of the next stage.
And is switched through a similar procedure. In this way, 4 × 12 switching is performed.

At this time, the same switching operation is performed on the other two 4 × 12 basic unit switch planes 12. Therefore, as shown in FIG.
The output cells 2-i-1 to 2-i-3 of each basic unit switch plane 12 aiming at −k store the switched cells at the same time.

In the first embodiment of the present invention, in order to enable fair cell transmission between the basic unit switch planes 12,
As shown in FIG. 4, ring arbitration type cell transmission output buffer selection control is employed.

This allots output buffers 2-i-1 to 2-i-3 which can send out cells at each cell time,
Output buffers 2-i-1 to 2-i- waiting for cell transmission permission
When there is a transmission cell in No. 3, the cell transmission right is equally given to each cell, and the cell is transmitted to the output line O-k. When the transmission right comes around, as shown in FIG.
For example, when there is no transmission cell in the output buffer 2-i-2, the transmission right is skipped to the output buffer 2-i-3 of the next-stage basic unit switch plate 12, and the output buffer of the next-stage basic unit switch plate 12 is skipped. 2-i-3 is control for transmitting a cell.

In order to improve the traffic characteristics of the basic unit switch 11 which is an input / output buffer type switch, it is desirable that the operation speed in the basic unit switch 11 be operated at twice or more the input / output line speed.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. In the first embodiment of the present invention, in order to enable fair cell transmission between the basic unit switch plates 12, the output buffers 2-i-1 to 2-i-3 between the basic unit switch plates 12 are read. Although the weights are set to 1: 1: 1, according to the second embodiment of the present invention, since there is a programmable output buffer contention controller 14 for controlling the output buffers 2-i-1 to 2-i-3, The readout weight of each output buffer 2-i-1 to 2-i-3 can be changed to give a priority to cell transmission between the basic unit switch plates 12.

In the example of FIG. 6, the output buffers 2-i-1 to 2-i-1
The readout weights of 2-i-3 were set to 3: 2: 1. According to this, the output buffer 2-i-1 can transmit three cells at one transmission opportunity, and the output buffer 2-i-2 can transmit two cells at one transmission opportunity. The buffer 2-i-3 can transmit one cell at one transmission opportunity.

In FIG. 6A, the output buffer 2-i-1
The transmission right is turned around, and a cell transmission permission signal for three cells is responded to one cell transmission request signal. In FIG. 6B,
The transmission right is transferred to the output buffer 2-i-2, and a cell transmission permission signal for two cells is responded to one cell transmission request signal. In FIG. 6C, the transmission right is transferred to the output buffer 2-i-3, and a cell transmission permission signal for one cell is responded to one cell transmission request signal. In this way, complicated buffer control such as weighted fair queuing is possible. Thus, traffic of different quality of service classes can be accommodated by simple software changes.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a diagram showing an ATM switch expansion configuration according to the third embodiment of the present invention in comparison with a conventional ATM switch expansion configuration. The ATM switch of the present invention can change the switch scale flexibly in response to traffic demand. This example will be described as a third embodiment of the present invention.

As shown in FIG. 8A, in the conventional ATM switch, when the traffic demand accommodated in # 1 to #k increases, or when the connection ground increases,
Add rows and / or columns (dashed line in FIG. 8 (a))
It is necessary to form a matrix configuration by expanding the entire switch.

On the other hand, as shown in FIG. 8B, in the case of the ATM switch of the present invention, the basic unit switch 11
(The hatched portion in FIG. 8B) can easily be expanded. Further, FIG.
In the conventional ATM switch shown in FIG. 8A, the traffic characteristics are changed by expanding the entire switch. In the ATM switch of the present invention shown in FIG. Since it can be handled, there is almost no change in the traffic characteristics.

Further, in the conventional ATM switch shown in FIG. 8A, the change of software related to the cell conflict control is complicated due to the expansion and requires much time, but the ATM switch of the present invention shown in FIG. Then, since the cell contention control is originally simple, it is easy to change the software related to the cell contention control with the extension.

[0042]

As described above, according to the present invention,
Eliminates the need for complicated cell contention control and redundant cell transfer routes, allows the switch size to be expanded asymmetrically, does not change the traffic characteristics associated with the expansion, and provides various services. An ATM switch capable of accommodating quality class traffic can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an ATM switch according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a basic unit switch according to the embodiment of the present invention.

FIG. 3 is a configuration diagram of an ATM switch according to the first embodiment of the present invention.

FIG. 4 is a diagram for explaining cell contention control of an output buffer according to the first embodiment of the present invention.

FIG. 5 is a diagram for explaining cell contention control of an output buffer according to the first embodiment of the present invention.

FIG. 6 is a diagram for explaining cell contention control of an output buffer according to a second embodiment of the present invention.

FIG. 7 is a diagram showing an address filter provided at a cross point.

FIG. 8 is a diagram showing an ATM switch extended configuration according to a third embodiment of the present invention in comparison with a conventional ATM switch extended configuration.

FIG. 9 is a diagram showing a conventional input / output buffer type cross point switch.

FIG. 10 is a diagram showing an arbitration range dividing method in a conventional input / output buffer type cross point switch.

FIG. 11 is a diagram for explaining contention control between blocks for transmitting a cell to an output line.

[Explanation of symbols]

1-1 to 1-M Input buffer 2, 2-1 to 2-N, 2-i-1 to 2-i-3 Output buffer 3 Cross point 4-1 to 4-M Extended output terminal 10 Cell transmission competition control Circuit 11 Basic unit switch 12 Basic unit switch plane 13 Input buffer contention control unit 14 Output buffer contention control unit 15 Cell transmission request processing unit 16 Address filter 20 Relay buffer I-1 to IM Input line O-1 to ON Output line

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Ryusuke Kawano 3-19-2 Nishi Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) Reference JP-A-10-51461 (JP, A) 9-149042 (JP, A) JP-A-63-62432 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28 H04L 12/56

Claims (3)

(57) [Claims] An input buffer for temporarily storing an incoming cell, an n output buffer for temporarily storing an output cell, an output signal line of the input buffer, and an input signal line of the output buffer. A basic unit switch including a cross point provided at a point where the matrix intersects, and an extended output terminal provided on an extension of the output signal line; And the extended output terminals are respectively connected to the inputs of the input buffers of the next-stage basic unit switch, and the cells transferred to the same output buffer among the n × p output buffers for the m input buffers A basic unit switch plane having means for performing conflict control of the above, and q basic unit switch planes are arranged in parallel,
The outputs of the i-th (≦ n × p) -th output buffers of the n × p output buffers of each basic unit switch plane are respectively connected to the outputs of the i-th output buffers of the other basic unit switch planes. An ATM switch comprising means for assigning a cell transmission right to each of q output buffers connected to the ATM switch. Where i, m, n, p, and q are natural numbers 2. The output buffer further comprises means for transmitting a signal indicating that there is a cell to be transmitted in its own buffer, wherein the means for allocating the cell transmission right comprises: 2. The AT according to claim 1, further comprising means for responding to a transmission permission signal or a transmission non-permission signal for the signal to be displayed so that the cell transmission opportunities are equal.
M switch. 3. The means for allocating the cell transmission right respectively responds a transmission permission signal or a transmission non-permission signal to the signal to be displayed so that the cell transmission opportunity of each output buffer follows a predetermined ratio. 3. The ATM switch according to claim 2, including means.