JP3052407B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device provided with a flip-flop type static memory cell having a high resistance load element.

[0002]

2. Description of the Related Art Conventionally, as shown in FIGS. 4A and 4B, for example, this type of semiconductor memory device has first and second driving devices for connecting a gate and a drain crossing each other. High-resistance first and second load resistors R1 respectively connected between the transistors Q1 and Q2 and the drains of the first and second transistors Q1 and Q2 and the power supply terminal (power supply voltage Vcc). , R2, and the first bit line B corresponding to the drain of the first transistor Q1.
1j and between the drain of the second transistor Q2 and the corresponding second bit line B2j and the gates respectively connected to the corresponding word line WL. The third and fourth transistors for transfer gates Q3, Q
Memory cell array areas 2a and 2b in which a plurality of memory cells MC each having a memory cell 4 are arranged in a matrix, and the arrangement of the memory cells adjacent to the outermost memory cells of the memory cell array areas 2a and 2b and extended. The pseudo cell areas 3c and 3d in which pseudo memory cells each having substantially the same structure as the memory cell MC are arranged at the positions where the memory cells are arranged at the time of the
The configuration has an X select circuit area 4 in which an X select circuit and a Y select circuit for selecting a predetermined memory cell MC a and 2b are formed, and Y select circuit areas 5a and 5b.

In the case where memory cells are arrayed on a semiconductor substrate by photolithography, the pseudo cell regions 3c and 3d are formed by simply arranging the memory cells. Since there is a difference in the peripheral pattern density, the exposure condition and the etching rate are different, so the finished dimensions are different between the outermost part and the inner part, and the memory cells in the outermost part are likely to be defective. Can be

Therefore, these pseudo memory cells are for uniformly forming the memory cells MC in the memory cell array regions 2a and 2b, and have no circuit function.

In order to confirm whether or not the memory cells MC in the memory cell array regions 2a and 2b are formed normally, the leakage current characteristics of the storage contacts Na and Nb of the memory cells are determined.
In order to indirectly measure the performance, a dedicated monitor area in which a plurality of measurement memory cells having the same structure as the memory cells are arranged in a specific portion on the semiconductor substrate.

[0006] Since the leakage current per memory cell is relatively small, the number of memory cells in the monitor area is 1000 or more.

[0007]

In the above-described conventional semiconductor memory device, pseudo cell regions 3c and 3d are formed on the outer periphery of the memory cell array regions 2a and 2b, and the storage of the memory cells MC in the memory cell array regions 2a and 2b is further performed. Since the monitor area for measuring the leakage current at the node is formed at a specific portion on the semiconductor substrate, there is a disadvantage that the chip area increases.

An object of the present invention is to provide a semiconductor memory device capable of reducing a chip area.

[0009]

SUMMARY OF THE INVENTION A semiconductor memory device according to the present invention comprises first and second driving transistors for connecting the gate and the drain crossing each other, and the drains of the first and second transistors. First and second load resistors respectively connected between the first transistor and a power supply terminal, and a first transistor corresponding to a drain of the first transistor.
Third and fourth transistors for transfer gates, which are connected between the respective bit lines and between the drain of the second transistor and the corresponding second bit line, and the gates are respectively connected to the corresponding word lines. A memory cell array region in which a plurality of memory cells each having a memory cell array are arranged in a matrix, and a memory cell adjacent to the outermost memory cell of the memory cell array region and extending when the memory cell array is extended. the arrangement is the position, position
A pseudo memory cell in which a pseudo memory cell is disposed in a memory cell , wherein a plurality of pseudo memory cells included in a predetermined portion of the pseudo cell region are respectively connected to first and second transistors of the memory cell. Fifth and sixth transistors having the same structure, dimensions and connection, and third and fourth transistors of the memory cell except that the gate is connected to a predetermined potential point and is always off. A measurement cell including seventh and eighth transistors having the same structure, dimensions and connection, and a third load resistor having one end connected to one of the drains of the fifth and sixth transistors; It is configured by providing a measurement pad commonly connected to the other end of each third resistor.

Further, the third load resistance has a smaller value than the first and second load resistances.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1A and 1B are a plan view and a circuit diagram mainly showing a measuring cell, respectively, of a semiconductor chip according to a first embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory device shown in FIGS. 4A and 4B in that the pseudo cell regions 3c and 3d are located near the Y select circuit regions 5a and 5b. The plurality of included pseudo memory cells are respectively stored in the first and second memory cells MC in the memory cell array region.
And fifth transistors Q5 and Q6 having the same structure, dimensions and connection as the transistors Q1 and Q2, and the memory cell MC except that the gates are respectively connected to the ground potential point.
And eighth transistors Q and Q having the same structure, dimensions and connections as the third and fourth transistors Q3 and Q4.
7, Q8 and one end of a fifth and sixth transistor Q5.
Each of the third resistors R3 is connected to one of the drains of Q6 and has a third load resistor R3 having a smaller resistance value than the first and second load resistors of the memory cell MC.
3 in that a measurement pad 7 commonly connected to the other end of the measurement pad 3 is provided. The measurement cell areas 6a and 6b are
This is the area where 1 is formed.

For example, the power supply voltage Vcc is applied to the measuring pad 7.
When 5V is applied, the transistor Q6 is turned on, the gate potential of the transistor Q5 is at a low level, and the transistor Q5 is turned off. The transistors Q7 and Q8 are off. In this state, the current flowing between the pad 7 and the ground potential point, that is, the leakage current of the storage contact Na of the measurement cell 61 can be measured.

The reason for reducing the resistance value of the load resistor R3 is that if the resistance value is substantially equal to the load resistances R1 and R2 of the memory cell MC, even if a leakage current is present at the storage contact Na (or Nb), the load is reduced. This is because the value of the leakage current is limited by the resistance, and it becomes difficult to detect the leakage current.

In order to form the measuring cell 61 having such a structure, a normal memory cell MC is used as a mask pattern.
On the other hand, it is possible only to eliminate the contact hole for connecting one load resistor and the storage contact, and to eliminate the nitride film pattern for masking the impurity implantation of the other load resistor into the polycrystalline silicon layer.

The patterns of the memory cell MC and the measurement cell 61 are asymmetrical left and right, and generally, the left and right storage contacts Na, N
The junction area and perimeter of b are slightly different, but the leakage currents are also different. For this reason, as shown in FIG. 2, the leakage currents of the left and right storage contacts Na and Nb are alternately measured by the same number, so that an average value can be obtained.

[0018] FIG. 3 is an equivalent circuit diagram of the measuring cell area of the second embodiment of the present invention.

In the measurement cell area of this embodiment, two measurement pads are used, that is, first and second pads 7a and 7b.
Third load resistance R of half of a plurality of measurement cells 61
3 is connected to the drain (storage contact Na) of the corresponding fifth transistor Q5, the other end is commonly connected to the first pad 7a, and the other half of the third load resistor R3 is connected to one end. Connected to the drain (memory contact Nb) of the sixth transistor Q6 to be connected to the second pad 7b.
Are connected in common.

With such a configuration, it is possible to measure the difference in the value of the leakage current caused by the asymmetry of the pattern of the memory cell MC and the measurement cell 61, and to reduce the imbalance of the leakage current based on the result. Thus, the pattern of the memory cell MC can be optimized.

[0021]

As described above, according to the present invention, each pseudo memory cell included in a predetermined portion of a pseudo cell region is provided only to one drain of a driving transistor and the load of the memory cell in the memory cell array region is reduced. Connect one end of a load resistor whose resistance value is smaller than the resistance, connect the gate of the transfer gate transistor to a predetermined potential point, turn off these transistors to make a measurement cell, and connect them in common with the other end of each load resistor In this configuration, a part of the pseudo cell region can be used as a measurement cell region for measuring a leakage current of a storage contact of a memory cell. This eliminates the need for a region and has the effect of reducing the chip area.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor chip according to an embodiment of the present invention and a circuit diagram mainly including a measuring cell of the embodiment.

FIG. 2 is an equivalent circuit diagram of a measurement cell region of the embodiment shown in FIG.

FIG. 3 is an equivalent circuit diagram of a measurement cell region according to a second embodiment of the present invention.

FIG. 4 is a plan view of a semiconductor chip as an example of a conventional semiconductor memory device and a circuit diagram mainly including memory cells of the semiconductor memory device.

[Explanation of symbols]

 1, 1a Semiconductor chip 2a, 2b Memory cell array area 3a-3d Pseudo cell area 4 X select circuit area 5a, 5b Y select circuit area 6a, 6b Measurement cell area 7, 7a, 7b Pad 61 Measurement cell B1j, B2j bits Line Q1-Q8 Transistor R1-R3 Load resistance WL Word line

Claims (3)

(57) [Claims] 1. A driving first and second transistor for connecting a gate and a drain crossing each other, and correspondingly connected between a drain and a power supply terminal of the first and second transistors, respectively. Between the drain of the first transistor and the corresponding first bit line, and between the drain of the second transistor and the corresponding second bit line. A memory cell array region in which a plurality of memory cells each having a third transistor and a fourth transistor for a transfer gate, each of which is connected to a corresponding word line and connected to a corresponding word line, are arranged in a matrix; position in which memory cells are arranged when extended the sequence of adjacent outer and the memory cells of each memory cell of
In a semiconductor memory device having a pseudo cell region in which a pseudo memory cell is disposed, a plurality of pseudo memory cells included in a predetermined portion of the pseudo cell region are respectively connected to first and second transistors of the memory cell. Fifth and sixth transistors having the same structure, dimensions and connection, and third and fourth transistors of the memory cell except that the gate is connected to a predetermined potential point and is always off. A measuring cell including seventh and eighth transistors having the same structure, dimensions and connection, and a third load resistor having one end connected to one of drains of the fifth and sixth transistors; A semiconductor memory device provided with a measurement pad commonly connected to the other end of each third resistor. 2. The semiconductor memory device according to claim 1, wherein said third load resistance is smaller than said first and second load resistances. 3. The measurement pads are first and second pads, and one end of a third load resistor of a half of the plurality of measurement cells is connected to the drain of a corresponding fifth transistor. And the other end is connected in common to the first pad, the other half of the third load resistors are connected in one end to the drain of the corresponding sixth transistor, and the other end is connected in common to the second pad. 2. The semiconductor memory device according to claim 1, wherein: