JP3052232B2 - Driving method and driving circuit for image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method and a driving circuit for an image display device in which one of electrodes arranged in a matrix is used as a scanning electrode, and more particularly to an image using a field emission type cathode. It is suitable for application to a display device.

[0002]

2. Description of the Related Art An electric field applied to a metal or semiconductor surface is 10
^At about ⁹ [V / m], electrons pass through the barrier and emit electrons in a vacuum even at room temperature due to the tunnel effect.
This is called field emission, and a cathode that emits electrons based on such a principle is called a field emission cathode (Fi
eld Emission Cathode). In recent years, it has become possible to realize a surface emission type field emission cathode by making an array of micron-sized field emission cathodes by making full use of semiconductor processing technology. Research and development of display devices are underway.

FIG. 5 shows a field emission cathode called Spindt type (hereinafter referred to as "FEC") which is an example of a field emission cathode produced by a semiconductor processing technique.
Shows a simulated configuration of In this figure, a cathode electrode made of metal such as aluminum is formed on a substrate such as glass by evaporation, and a cone-shaped emitter made of metal such as molybdenum is formed on this cathode electrode. An insulating layer such as a silicon dioxide (SiO ₂ ) film is formed on a portion of the cathode electrode where the emitter is not formed, and a gate is formed thereon. A round opening provided in the gate and the insulating layer The cone-shaped emitter is located in the portion. That is, the tip of the cone-shaped emitter faces the opening provided in the gate.

The pitch between the cone-shaped emitters can be set to 10 μm or less, and tens of thousands to hundreds of thousands of emitters can be provided on one substrate. Furthermore, since the distance between the gate and the tip of the cone of the emitter can be made submicron, by applying a gate-emitter voltage V _GE of only several tens of volts between the gate and the emitter electrode, electrons can be emitted from the emitter. From the field. These field-emitted electrons can be collected by the anode if the anode to which the positive voltage _VA is applied is provided opposite to the gate and is opposed to the gate.

FIG. 4 shows the characteristics of the anode current I _e and the gate-cathode voltage V _{GC of} such an FEC. As shown in this figure, as the gate-cathode voltage V _GC gradually increases, the anode current _Ie starts to flow. The voltage V _{GC at} which the current I _e starts to flow is set to the threshold voltage V _TH
At this time, the electric field between the gate and the cathode is about 10 ⁹
Since the voltage becomes about [V / m], electrons start to be emitted from the emitter. As a result, the anode current _Ie starts to flow to the anode. In general, a voltage of about V _OP shown in the figure, which is considerably higher than the threshold voltage V _TH , is applied between the gate and the cathode. At this time, an anode current I _op flows through the anode.

[0006] Since the anode current obtained from one of the cone-shaped emitters is a small current of about 1 microampere, an FEC that can obtain a desired anode current is obtained by arraying a large number of emitters. In this case, if a phosphor is provided on the anode, a portion of the phosphor of the anode where electrons emitted from the emitter are collected can be emitted. By utilizing such a principle, an image display device using FEC (hereinafter, referred to as FEC)
"FED").

FIG. 6 is a block diagram showing a configuration of a drive circuit of an FED using the above-described principle, and FIG. 7 shows a drive waveform of a gate electrode of this drive device. In FIG. 6, gate data and a shift clock (CLK) are input to a shift register 20.
At 0, the input gate data is sequentially shifted by the shift clock, and is sequentially applied to the respective gate drivers 21-1 to 21-n.

The gate data applied to the gate drivers 21-1 to 21-n is "1" data of one shift clock width generated at the start timing of one frame, and the "1" data is shifted. As a result, the sequence pulses are represented as GT1, GT2, GT3,... GTn in FIG. The pulse width of this order pulse is 1H, which is a period for scanning one horizontal line, and one frame is indicated by nH.

The gate drivers 21-1 to 21-n
Are each configured by a totem-pole type driver made of, for example, a C-MOS as shown in FIG.
-1 to 22-n can be driven at high speed. In this case, a field effect transistor (F
ET) to the source terminal of Tr ₁ is connected to a driving power source V _D, the source terminal of the field effect transistor Tr _2, the bias power source V as swing voltage of the driver is low
_S is connected.

The gate electrodes 22-1 to 22-n are formed in stripes, respectively,
1 drives the gate electrode 22-1, the gate driver 21-2 drives the gate electrode 22-2, and the gate electrodes are sequentially driven in this way, and the final gate electrode 22-n is driven by the final gate driver 21-n. -N is driven.

That is, for example, when gate data is applied to the gate driver 21-1 and this driver is selected, the transistor Tr _{1 of the} gate driver 21-1 is selected.
Is turned on, and the voltage V output from the driver 21-1 is output.
_D is applied to the gate electrode 22-1 to be driven.

When the gate data is transferred to the next gate driver 21-2 and the gate driver 21-1 is not selected, the transistor Tr of the gate driver 21-1 is turned off.
With ₁ is turned off, the transistor Tr ₂ is to become turned on, the bias voltage V _S is supplied to the gate electrode 22-1. The bias voltage Vs is lower than the gate-to-cathode threshold voltage _VTH .

On the other hand, cathode data which is serialized image data is input to the shift register 23, converted into parallel data here, and latched by the latch circuit 24. Therefore, a shift clock (CLK) for cathode data shift is input to the shift register 23. The parallel cathode data latched by the latch circuit 24 at each gate electrode scanning timing (horizontal scanning timing) is stored in the cathode driver 25-
1 to 25-m. This cathode driver 25
By the cathode data applied to -1 to 25-m, the emission of the phosphor provided on the anode (not shown) is simultaneously controlled for one row in units of one pixel, and the gate electrode 22-1 to the gate electrode 22-n When scanned to
One frame image is displayed on the anode.

The cathode electrodes 26-1 to 26-m are formed in stripes, and the cathode driver 25-1 drives the cathode electrode 26-1, and the cathode driver 25-2 operates as the cathode electrode 26-2. , And the final cathode electrode 26-m is driven by the final cathode driver 25-m.

The gate electrodes 22-1 to 22-n and the cathode electrodes 26-1 to 26-m are arranged in a matrix, and at the intersection of the two electrodes, an emitter array E ₁₁ as shown in FIG. _{, E 12 ··· E 21, E} 22 ··· E nm is,
The emitter arrays are formed on the respective cathode electrodes 26-1 to 26-m, and the emitter arrays form pixels of the image display device.

Therefore, the gate drivers 21-1 to 21-21
-N are sequentially selected, and the gate electrodes 22-1 to 22- are sequentially selected.
When n is driven, a predetermined voltage is applied between the gate and cathode electrodes to emit electrons from the emitter array, and the electrons are separated from each other on the gate electrodes 22-1 to 22-n. Not collected on the anode.

The anode is provided with a phosphor, and the electrons emitted from the emitter array, which is a pixel, cause the corresponding phosphor to emit light. Then, as described above, the cathode electrode 26-
Since image data is applied to 1 to 26-m,
The phosphor emits light according to the image data, and as a result, an image is displayed on the phosphor.

In the image display device shown in FIG. 6, the gate electrodes 22-1 to 22-n and the cathode electrode 26 are provided.
Since -1 to 26-m are arranged in a matrix with an insulating layer interposed therebetween, an electrostatic (or insulating layer) capacitance _CC is generated in a portion where both electrodes overlap as shown in the figure. Since the capacitance C _C is repeatedly discharged / charged in accordance with the potential difference between the gate electrode and the cathode electrode, the power supply driving the gate electrode and the cathode electrode is charged / discharged.
Reactive power P _W associated with charging is generated. Since the reactive power P _W increases in proportion to the drive frequency, a reactive power of several tens of watts may be generated in a cathode power supply having a high drive frequency.

Therefore, a drive circuit designed to reduce the reactive power has been proposed (if necessary, Japanese Patent Laid-Open No. 6-20834).
See No. 0 publication. FIG. 9 shows a circuit diagram of this drive circuit. The description of the circuit shown in FIG. 9 will be described with reference to the pulse timing chart supplied to the gate electrode shown in FIG. The shift register 130 has n stages of D-type flip-flops (D-FF) 132 _{1 to} 132 n.
-FFs are connected in cascade, the first stage is supplied with gate data D, and the shift clock CP is supplied to all stages.

[0020] Each stage of the shift register 130 output is input to each combinational logic 133 ₁ ~133n, the output of the combinational logic 133 ₁ ~133n has drives the driver 128 ₁ ~128n totem pole. Drivers 128 _{1 to} 128 n are gate electrodes GT
1 to GTn are respectively driven. The operation of the driving circuit configured as described above will be described. When the output of the D-FF 132 ₁ of the first stage of the shift register 130 is at H level, the output of the inverter 134 ₁ is at L level, 140 ₁ because it is input to 140 ₁
Is also at the L level. L of this inverter 134 ₁
Output transistor T1 ₁ is turned on is driven by the transistor T2 ₁ is turned off by the L output of the AND circuit 140 _1. Therefore, the output gate electrode driving voltage Vls from driver 128 _1, the gate electrode GT1 are selectively driven as shown in FIG. 8 (a).

[0021] next shift clock CP to the shift register 130 is input, only the D-FF132 ₂ outputs the second stage becomes the H level, the same operation is performed,
The gate electrode driving voltage Vls outputted from the driver 128 ₂ as shown in FIG. 8 (b), the gate electrode GT2
Is selectively driven. In this case, the second stage D-FF 132
₂ is used as the second input of the AND circuit 140 ₁ in the first stage. At this time, the H output from the inverter 134 ₁ is input to the first input of the AND circuit 140 ₁ .
Transistor T1 ₁ by H output of the inverter 134 ₁
There is turned off, the transistor T2 ₁ is turned on are driven by H output of the AND circuit 140 _1. Therefore, the driver 128 ₁ outputs a low voltage Vd for setting the gate electrode GT1 to a low level, and the potential of the gate electrode GT1 is set to a low level.

As described above, the period during which the gate electrode GT1 is driven is made equal to the rising width of the shift clock CP, and this period is one horizontal scanning period (1) as shown in FIG.
H). Further, when the next shift clock CP is input to the shift register 130, the third stage D-FF
132 only _three outputs are at H level. As a result, the gate electrode GT3 is selectively driven, and the potential of the gate electrode GT2 is made low by the same operation as described above. Further, at this time, the D-FF132 ₂ outputs the AND circuit 140 ₁ of the output is also L level since the L level.
Then, the H output of the inverter 134 ₁ transistor T1 ₁ is turned off, the transistor T2 ₁ by H output of the AND circuit 140 ₁ is also turned off. Therefore, as shown by the broken line in FIG. 8, the driver 128 ₁ is in a high impedance state, and the gate electrode GT1 is in a floating state.

Such operations are sequentially performed, and each gate electrode is selectively driven once in a period (one frame) until it is selected again, so that the gate electrode is set to the high level state for the 1H period, and the next 1H is performed. During this period, the signal is kept at a low level, for example, ground (GND), and the other periods are in a floating state. Incidentally, when the gate electrode is in a floating state, since the the current path of the charging / discharging of the capacitance C _C is not formed, this period the capacitance C _C
Is not performed, and the reactive power is reduced.

[0024]

However, the conventional driving circuit described above must be controlled so that the circuit becomes a complicated circuit as shown in FIG. 9 and a high impedance state is set for each driver output. For this reason, there is a problem in that although a large number of general-purpose drivers are built in, a one-chip driver that cannot be controlled to a high impedance state for each driver output cannot be employed. Therefore, an object of the present invention is to provide a driving method and a driving circuit of an image display device which can reduce reactive power of a driving power supply even if a one-chip driver in which a large number of general-purpose drivers are incorporated. And

[0025]

In order to achieve the above object, a method and a circuit for driving an image display device according to the present invention provide an image display device having a plurality of gate electrodes and cathode electrodes arranged in a matrix. In driving,
The scan electrodes are driven by a one-chip driver including a plurality of drivers, and all the output states are in a high-impedance state while the one-chip driver is in an inactive state. Further, the one-chip driver in the active state and one in the driving order adjacent to the one-chip driver
The active states of the chip drivers are partially overlapped.

[0026]

According to the present invention, since a floating state is set for each group of scanning electrodes driven by the driver chip, a current path for charging / discharging the capacitance is not formed, and the reactive power can be reduced. it can. Therefore, the power supply capacity for the driver can be reduced, the size can be reduced, and the cost can be reduced. Further, since the active states of the one-chip driver in the active state and the one-chip driver whose driving order is adjacent to the one-chip driver partially overlap, the output level of the final stage in each one-chip driver changes to a low level. After that, a high impedance state can be set.

[0027]

Embodiments of the present invention will be described below. FIG. 1 is a block diagram of an embodiment of a driving device of an image display device embodying the driving method of the present invention. FIGS. 2 and 3 show timing diagrams of the driving device. In FIG. 1, the display 1 is composed of an m × n matrix as shown in FIG. That is, the number of gate electrodes is GT1, G
GTn, T2, GT3,... GTn, and m cathode electrodes C1, C2, C3,. The cathode drivers 2-1, 2-2,..., 2-i are one-chip drivers.
, 2-i are connected in cascade, and the cathode electrodes C1, C2, C3,... Cm are driven.

The gate drivers 3-1, 3-2,.
.., 3-j are also one-chip drivers, and these gate drivers 3-1, 3-2,..., 3-j are also cascaded, and the gate electrodes GT1, GT2,. ing. The control unit (CONT) 4 controls the active state of the gate drivers 3-1, 3-2,..., 3-j, and the gate electrodes are sequentially driven by the activated gate drivers.

Next, the operation of the driving circuit thus configured will be described. The gate data applied to the gate driver 3-1 includes the gate electrodes GT1, GT2,.
... At the start of one frame, the signal is kept at the high level for 1H so that a sequence pulse for driving GTn is generated. Each of the gate drivers 3-1, 3-2.
.. 3-j is configured to be able to drive, for example, 64 gate electrodes. That is, the gate driver 3-1 includes the gate electrodes GT1, GT2,.
, GT128, and the gate driver 3-j drives the gate electrodes GT65, GT66,..., GT128.
−63), GT (n−62),..., GTn.

Gate drivers 3-1, 3-2,... 3
In the case of −j, drive pulses for sequentially driving the 64 gate electrodes are sequentially generated in each driver as shown in FIG. 2, but only during the period in which this sequence pulse is generated, as shown in FIG. Each gate driver 3-1, 3-2, ... 3-
j is set to the active state. The control to make this active state is performed by the control unit 4. Then, during the period of the inactive state, each of the gate drivers 3-1 and 3-
All of the 64 outputs 2, 3,..., 3-j are in a high impedance state.

FIG. 2 shows the manner in which such driving is performed. As shown in FIG. 2A, in the gate driver 3-1, the driving pulse for driving the gate electrode GT1 is one frame. At the start, the signal is kept at the high level for the 1H period, and is kept at the low level for the subsequent 64H period. Then, during the remaining period of one frame, the gate driver 3-1 is in an inactive state, and all its outputs are in a high impedance state. The drive pulse for driving the gate electrode GT2 is at a low level for a 1H period at the start of one frame, at a high level for the subsequent 1H period, and at a low level for the subsequent 63H period. During the remaining period of one frame, all the outputs are similarly set to the high impedance state. Further, a driving pulse for driving the gate electrode GTn is 63H from the start of one frame.
It is kept at the low level during the period, kept at the high level for the following 1H period, and kept at the low level for the following 1H period. And
During the remaining period of one frame, all the outputs are similarly set to the high impedance state.

The gate driver 3-2 whose driving waveform is shown in FIG. 2B and the gate driver 3-n whose driving waveform is shown in FIG.
After all, as shown in FIG.
Are in an active state only during a period from the start of one frame to 65H, the gate driver 3-2 remains inactive for a period of 64H from the start of one frame, and is in an active state only during a period from 65H to 129H. Driver 3-n remains inactive for 64 (n-1) H period from the start of one frame, and is activated only from {64 (n-1) +1} H period to 1H period of the next frame. . Each gate driver sequentially drives 64 gate electrodes during the active period.

Although not shown, the gate electrodes GT1 to GTn and the cathode electrodes C1 to Cm are arranged in a matrix.
As shown in (1), an emitter array is formed on each of the cathode electrodes C1 to Cm, and the emitter arrays respectively form pixels of the image display device. The output circuits of the gate drivers 3-1 to 3-n whose outputs are in three states of a high level, a low level and a high impedance state are totem pole type C-MOS circuits as shown in FIG. ing. Then, any one of the driven gate electrodes GT1 to GTn and the cathode electrode C1
To Cm, a predetermined voltage is applied, and electrons are emitted from the emitter array in the row of the driven gate electrodes GT1 to GTn, and the electrons are spaced apart on the gate electrodes GT1 to GTn. Not collected on the anode.

The anode is coated with a phosphor, and the electrons emitted from the emitter array, which is a pixel, cause the corresponding phosphor to emit light. Here, the cascade-connected cathode driver 2-1 is connected.
The cathode data is supplied to .about.2-i. The cathode data is one line of image data. Each time the gate electrode is selectively driven, image data corresponding to the selectively driven gate electrode is displayed. The light is latched by the cathode drivers 2-1 to 2-i, and light emission is controlled by the latched image data. As a result, when scanning of the gate electrodes GT1 to GTn for one frame is completed, an image of one frame is displayed on the anode.

By the way, in the driving device of the image display device of the present embodiment, the gate drivers 3-1 to 3 formed as one chip are used.
The reason why −j is in the active state for a period of 65H, though it drives 64 gate electrodes, will now be described. Each gate driver 3
-1 to 3-j, 6
The 4H period is a period in which the 64th output is at a high level. In the gate drivers 3-1 to 3-j, 6
Assuming that the active state is set only for the 4H period, the active state is set to the inactive state in the 65H period. Then, since the output level of the 64th line is set to the high impedance state from the 65H period, the driven gate electrode is set to the floating state without falling to the zero level. Accordingly, for example, a high level is held as shown by a two-dot chain line in the column of GT64 in FIG.

When the gate electrode is set to a high level, electrons can be emitted from the emitter array, so that this row emits light. That is, the horizontal line 6
Erroneous light emission occurs every fourth line. Therefore, to prevent this, each of the gate drivers 3-1 to 3-j
In addition to the 64H period, the active state is controlled to be further activated for the 1H period. That is, in the 65H period of the active period, the output of the 64th line is dropped to the zero level. Thereby, erroneous light emission can be prevented. The extended active period is 1
The period is not limited to the H period, and can be 1H or more. However, if it is too long, the reactive power increases, so that 1H is optimal.

As described above, the drive circuit of the image display device of the present invention controls each gate driver constituted by one chip so as to be in the active state or the inactive state, and the active state is adjacent to the gate driver. By controlling the gate drivers to be driven so as to overlap at least for 1H period, a general-purpose one-chip driver can be employed. In this case, the gate electrode connected to the inactive gate driver is in a floating state, so that the reactive power can be reduced.

When the floating state is set,
Under the influence of the cathode electrodes C1 to Cm to which the high-level or low-level image data is supplied, the potentials of the gate electrodes GT1 to GTn are, for example, as shown in FIG.
In some cases, as shown by a dashed line in column 1, there is a case where it gradually rises. When the potential V _ch raised by such a phenomenon exceeds the threshold voltage V _TH shown in FIG. 4, light leaks, so that the low level of the gate electrodes GT1 to GTn is lowered to the ground potential instead of the bias voltage. It is preferred that That is, when the voltage is lowered to the ground potential, the voltage margin for preventing leakage light emission at the gate electrode can be increased.

In the above description, the gate electrode is driven to scan and the one-chip driver is used to drive the gate electrode. However, the present invention is not limited to this. Alternatively, the cathode electrode may be driven by a one-chip driver. One chip driver is 64
Although it has been described that the operation electrodes are driven, the present invention is not limited to this, and may drive 32, 16 or the like operation electrodes.

[0040]

As described above, in the driving circuit of the image display device according to the present invention, since the group of the scanning electrodes driven by the one-chip driver is set to the floating state in the inactive state, the driving circuit is static in the inactive state. Since a current path for charging / discharging the capacitance is not formed, the reactive power can be reduced. Therefore, the power supply capacity of the driver can be reduced, the size can be reduced, and the cost can be reduced.

Further, since the active state of the one-chip driver in the active state and the active state of the driver whose driving order is adjacent partially overlap, the output level of the final stage in each one-chip driver is set to a low level. After the transition, a high impedance state can be set, and erroneous light emission can be prevented. Further, it is possible to eliminate the necessity of creating a complicated drive circuit using individual components as in a conventional drive circuit, and it is possible to use a general-purpose chip, so that the cost can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a driving circuit for driving an image display device according to an embodiment of the present invention.

FIG. 2 is a timing chart of a driving signal of a gate electrode for explaining an operation of a driving circuit for driving an image display device according to an embodiment of the present invention.

FIG. 3 is a timing chart showing an active state and an inactive state of a gate driver for explaining an operation of a driving circuit for driving an image display device according to an embodiment of the present invention.

FIG. 4 is a diagram showing an anode current-gate-cathode voltage characteristic of a field emission cathode.

FIG. 5 is a diagram showing a Spindt-type field emission cathode.

FIG. 6 is a block diagram showing a driving circuit of a conventional image display device.

FIG. 7 is a diagram showing operation waveforms of a conventional gate electrode.

FIG. 8 is a diagram showing another operation waveform of the conventional gate electrode.

FIG. 9 is a block diagram showing another driving circuit of the conventional image display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Display 2-1-2-m Driver of cathode electrode 3-1-3-n Driver of gate electrode 4 Control part

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-6-208340 (JP, A) JP-A-2-184890 (JP, A) JP-A-57-207287 (JP, A) JP-A-4- 75020 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 3/20

Claims (2)

(57) [Claims] 1. An emitter array formed on a stripe-shaped cathode electrode, and a gate arranged above the emitter array and arranged in a direction substantially orthogonal to the cathode electrode group. A display device comprising: an electrode group; a scan driver unit that drives one of the gate electrode group or the cathode electrode group as a scan electrode group and the other as a data electrode group; and a data drive unit. A plurality of one-chip drive means corresponding to a plurality of areas obtained by dividing the display screen; a plurality of one-chip drive means sequentially driving the plurality of one-chip drive means to an active state; It is constituted by control means for controlling the output of the chip drive means to a high impedance state, and At the end of the active period of the one-chip drive means there is a blanking state, at least one scan period
In the meantime, the last scan electrode is controlled to the non-selection state, and the active period of the one-chip drive unit to be driven to the next active state overlaps within the one scan period.
A driving circuit for an image display device, characterized in that the driving circuit is controlled as follows. 2. An emitter array is formed on a cathode electrode formed in a stripe shape, and a gate electrode group is arranged above the emitter array in a direction substantially orthogonal to the cathode electrode group. Scan driver means for driving one of the electrode group or the cathode electrode group as a scan electrode group and driving the other as a data electrode group, and a data drive means, and the scan drive means includes a plurality of divided display screens. region to be divided into a plurality of one-chip drive means for sequentially scanning each scan electrode group corresponding, to drive to sequentially active one chip drive means of said plurality, Inactive
The output of the remaining one-chip drive means has a blanking state controlled to a high impedance state, and, just before the end of the active period of the one-chip drive means are in the active state, at least one run
When the last scan electrode is controlled to the non-selection state during the scanning period,
And controlling the active period of the one-chip drive unit to be driven next to the active state so as to overlap by one scanning period.