JP3050997B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device having a thin film transistor connected to a liquid crystal display element.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a configuration example of a general liquid crystal display module. In FIG. 1, reference numeral 13 denotes a liquid crystal panel in which gate wirings G1, G2... Gn and drain wirings D1, D2... Dm are arranged in a matrix, and a thin film transistor (hereinafter abbreviated as TFT) 1 is provided at each intersection.
1 is provided. Each source electrode of the TFT 11 has a liquid crystal cell capacitor 1 formed by a pixel electrode and a counter electrode.
Two pixel electrodes are connected. The counter electrode is commonly connected to all pixels, and a common voltage Vcom is applied. 1
4 is a horizontal driver and 15 is a vertical driver.

A driving method of a conventional liquid crystal display device as shown in FIG.
No. 59-220793. FIG. 3 is a waveform diagram showing an example of a driving voltage waveform of a conventional liquid crystal display device.

In FIG. 3, Hsync is a signal waveform having a cycle of one horizontal scanning period of a video signal to be displayed.
d1 is a voltage waveform applied to the drain wiring D1, Vg
1, Vg2 and Vg3 are gate wirings G1, G2 and G, respectively.
3 is a voltage waveform applied to No. 3. The liquid crystal needs to be driven by an alternating current in order to prevent deterioration of its characteristics.

Accordingly, the drain wirings D1, D2,.
As the voltage applied to m, the signal voltage on the positive polarity side and the signal voltage on the negative polarity side are alternately applied with the center voltage Vc as a boundary, as represented by Vd1. The gate lines G1, G2,.
An on-voltage Vgon is applied to turn on the TFT connected to each gate wiring, and an off-voltage Vgoff is applied to turn off the TFT otherwise. The ON voltage Vgon is
The gate lines G2, G3,.
n is given only for a gate selection period Ton equal to the horizontal scanning period.

The turned-on TFT writes the signal levels of the drain lines D1, D2... Dm to the liquid crystal cell capacitor 12, thereby changing the voltage applied to the liquid crystal cell capacitor 12 and changing the transmittance of the liquid crystal panel. Thus, an image is displayed.

[0007]

Generally, as described above, a liquid crystal needs to be driven by an alternating current in order to prevent deterioration of display characteristics. Therefore, it is necessary to set the voltage of the pixel electrode with respect to the counter electrode to a positive signal voltage or a negative signal voltage every certain period. In the related art, the ON voltage Vgon of the gate line when the TFT is turned on and the positive signal voltage is written to the pixel electrode is the same as when the negative signal voltage is written to the pixel electrode.

FIG. 4A shows an example of a pixel electrode voltage waveform at the time of writing a positive polarity signal voltage, and FIG. 4B shows an example of a pixel electrode voltage waveform at the time of writing a negative polarity. In FIG. 4, Vd1 indicates a voltage waveform of a drain wiring, Vg1 indicates a voltage waveform of a gate wiring, and Vs1 indicates a voltage waveform of a pixel electrode.

In FIG. 4A, since Vd1 is a positive signal voltage, the gate-drain Vgd + when the ON voltage Vgon is applied to the gate wiring is Vd1 in FIG. 4B.
When d1 is a negative signal voltage, it becomes smaller than the gate-drain Vgd- when the on-voltage Vgon is applied to the gate wiring.

FIG. 5 shows the gate-drain voltage (VGD).
FIG. 6 is a characteristic diagram showing an example of a characteristic of a source current (IDS) with respect to FIG. Thus, the source current increases as the voltage difference between the gate and drain increases. So, for example,
Assuming that the time required for writing 90% of the negative polarity signal voltage to the pixel electrode is Tf and the time required for writing 90% of the positive polarity voltage is Tr, as shown in FIG. The time Tr required for writing the positive polarity signal voltage is longer than the time Tf required for writing the positive polarity signal voltage.

There is no problem in the difference between the times required for writing when the gate selection time Ton is sufficiently longer than the time Tr required for writing the signal voltage level on the positive polarity side.
However, the number of liquid crystal display elements that must be driven per fixed time increases due to the high definition of the liquid crystal panel and the like, and the selection time Ton of one gate wiring is reduced to the time Tr required for writing the positive signal voltage. In the case where it is necessary to make it shorter, a write failure occurs at a positive signal voltage.

In the above prior art, due to the difference in the time required for writing the positive signal voltage and the negative signal voltage, it is impossible to achieve an alternating current between the positive signal voltage and the negative signal voltage centering on the common electrode Vcom. In such a case, phenomena such as flicker and image sticking occur, and the image quality deteriorates.

An object of the present invention is to overcome the problems of the prior art and to increase the number of liquid crystal display elements which must be driven per fixed time due to the high definition of the liquid crystal panel. It is an object of the present invention to provide a liquid crystal driving device which enables AC driving with a positive signal voltage and a negative signal voltage centered on an electrode Vcom so that image quality does not deteriorate.

[0014]

In order to achieve the above object, according to the present invention, the sum of the application time of the positive signal voltage and the application time of the negative signal voltage of the drain wiring is set to twice the horizontal scanning period of the signal source. Under the condition of maintaining, the application time of the positive polarity signal voltage of the drain wiring was made longer than the application time of the negative polarity signal voltage. Accordingly, the length of time for applying the ON voltage of the gate wiring is changed depending on whether the voltage of the drain wiring is a positive signal voltage or a negative signal voltage.

[0015]

According to the present invention, if the total value of the negative signal voltage writing time length of the TFT and the positive signal voltage writing time length is equal to or less than two horizontal scanning periods of the signal source, the positive signal voltage writing time length is reduced. Even if it is longer than one horizontal scanning cycle, it can be covered by making the negative polarity signal voltage writing time length shorter than one horizontal scanning cycle, so that the TFT can correctly write the negative polarity voltage and the positive polarity voltage. Therefore, it is possible to prevent a change in the center voltage (DC voltage component) of the pixel electrode due to the defective writing of the positive polarity voltage.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram schematically showing a circuit configuration of a liquid crystal display device as one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a control circuit which forms a signal necessary for driving a liquid crystal panel from a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock, display data, and the like sent from a signal source. Are applied to the horizontal driver 14 and the vertical driver 15 as they are.

The horizontal driver 14, the vertical driver 15, and the liquid crystal panel 13 are the same as the conventional ones, and have already been described. Here, in the present invention, a clock CLK1 synchronized with the horizontal scanning cycle, for example, a horizontal synchronization signal Hsync or the like is extracted from the control circuit 1,
Input to the frequency dividing circuit 2. The output of the divide-by-2 circuit is the first
Is input to the monostable circuit 3 and the second monostable circuit 4.

First monostable circuit 3 and second monostable circuit 4
Are synthesized by the logic circuit 5. The output of the logic circuit 5 is input to each of the horizontal driver 14 and the vertical driver 15 as a horizontal clock CLK2.

FIG. 6 shows an example of the operation waveform of each part in the embodiment of FIG. In FIG. 6, the signal a is the output of the divide-by-2 circuit 2, and if the cycle of the clock CLK1 is 1H (one horizontal scanning cycle), the cycle of the signal a is 2H. The first
Is a circuit that forms a pulse at the rising edge of the input signal a, and the output of the monostable circuit 3 is at the “H” level for a predetermined period (Tb) from the rising of the input signal a, like the signal b. A waveform is obtained.

The second monostable circuit 4 is, for example, a circuit that forms a pulse at the falling edge of the input signal a, and the output of the second monostable circuit 4 is a predetermined signal from the falling of the input signal a like the signal c. During the period (Tb), a waveform having the “H” level is obtained. When these signals b and c are input to the logic circuit 5 which is a NOR circuit, the output becomes a waveform CLK2 shown in FIG. Note that the pulse widths Tb and Tc of the signals a and c can be arbitrarily set by the circuit constants of the first monostable circuit 3 and the second monostable circuit 4.

In FIG. 6, Vd1 is an example of the output voltage waveform of the horizontal driver 14 shown in FIG.
6 is an example of a voltage waveform applied to the oscilloscope. Drain wiring D1, D
As for the voltage waveform applied to Dn, a positive signal voltage and a negative signal voltage are alternately applied at the center voltage Vc as represented by Vd1.

Here, in the present invention, the CLK2 is used as an output voltage switching signal of the horizontal driver 14. Accordingly, in the present invention, as represented by the voltage waveform Vd1, a driving method in which the time length for applying the positive signal voltage to the drain wirings D1, D2. Become.

Here, in the present invention, the writing time length of the positive polarity signal voltage of the pixel electrode voltage is Tr, the writing time length of the negative polarity signal voltage is Tf, and the positive polarity signal voltage of the drain wirings D1, D2. Assuming the time length Ton + to be applied and the time length Ton- to apply the negative signal voltage,

On condition that Ton +> Tr Ton−> Tf is satisfied, the following equation is established.

(Ton +) + (Ton −) = 2H (Ton +)> (Ton−)

Vg1, Vg2, and Vg3 in FIG. 6 are examples of output voltage waveforms of the vertical driver 15 shown in FIG. 1, and are examples of voltage waveforms applied to the gate lines G1, G2, and G3. Vgon is the voltage for turning on the TFT, and Vgoff is T
This is a voltage for turning off the FT. The TFT writes the voltage of the drain line to the pixel electrode when the voltage of the gate line is the ON voltage Vgon.

The vertical driver 15 includes a gate wiring G
The on-voltage Vgon is sequentially applied to 1, G2... Gn.
In this embodiment, the CLK2 is used as the shift clock of the vertical driver 15. Therefore, as shown in FIG.
The application time length of the ON voltage Vgon of Vg1 and Vg3 is Ton +, Vg
The application time length of the ON voltage Vgon of No. 2 is Ton-. In addition,
In the next field, since voltages of opposite polarities are written to the pixel electrodes, the application time length of the ON voltage Vgon of Vg1 and Vg3 is Ton-, and the application time length of the ON voltage Vgon of Vg2 is Ton +.
Becomes

FIG. 7 shows a voltage change of the pixel electrode when the above voltage is applied. In FIG. 7, the same symbols as those in FIG. 6 indicate the same voltages. Vs1 indicates a pixel electrode voltage waveform when a positive signal voltage is written, and Vs2 indicates a pixel electrode voltage waveform when a negative signal voltage is written. Also, T
r is the writing time length of the positive polarity voltage, and Tf is the writing time length of the negative polarity voltage.

In this embodiment, as shown in FIG. 7, even if the writing time length Tr of the positive polarity voltage is longer than one horizontal scanning period (1H), the time required for writing the positive polarity voltage can be made longer than before. Therefore, flicker, image sticking, and the like caused by the defective writing of the positive polarity can be prevented, and the image quality can be improved. Further, in order to drive the liquid crystal panel in consideration of the gate delay, CLK2 given to the horizontal driver may be delayed by the gate delay.

FIG. 8 is a block diagram showing a configuration example of a horizontal driver that can be used in this embodiment. FIG. 9 shows FIG.
FIG. 6 is a waveform chart showing an example of a signal waveform of each part of the horizontal driver of FIG.
Please refer to FIG. 8 and FIG.

The horizontal driver shown in FIG. 8 comprises an address register 30, a first latch circuit 31, a second latch circuit 32,
It comprises a third latch circuit 33 and a voltage selection circuit 34. The address register 30 receives a clock CLK0 such as a dot clock synchronized with a pixel, and designates an address of the first latch circuit 31 which uses display data as input data.

The contents of the display data change for each pixel, and the contents are indicated by data D00, D01... D0m in the first row, data D10, D11. Pm are output data of the first latch circuit 31, and P0 is data D00, D10... Dm of the first column.
.., Dm1,... Dm1,..., Dm1,.

The output data P0, P0,
Pm are input data of the second latch circuit 32. When the data P0, P1... Pm have the display data of the first row, the third latch circuit of the next stage is synchronized with the clock signal CLK1. 33. Here, CLK1
And CLK2 are the same as the signals of the same names in FIGS. 1 and 6, and the description thereof will be omitted.

In the conventional configuration having only the first latch circuit 31 and the second latch circuit 32, the display data of 1H or more cannot be continuously output.
Is newly provided. The third latch circuit 33 latches the output data Q0, Q1,..., Qm of the second latch circuit 32 at the timing of the clock signal CLK2, and the output data becomes like R0, R1,. The output data R0, R1,.
Rm selects a positive output voltage level and a negative output voltage level.

The first latch circuit 31, the second latch circuit 32 and the third latch circuit 33 each require n pieces of display data if the display data is n bits. In the color display, there are red, blue, and green display data.
Two systems are required.

A voltage selection circuit 34 per one output of the horizontal driver mainly has a plurality of switches, each of which receives a voltage (V1... Vk) as an input and whose output terminals are commonly connected, as shown in FIG. It is composed of an element 35 and the like. With the control signals W1 to Wk formed from the n-bit display data through a decoder, a level shifter, and the like, only one of the plurality of switch elements 35 is selected and turned on to obtain a necessary voltage level.

In FIG. 9, the output of the voltage selection circuit 34 is used as it is as the output of the horizontal driver of FIG.
If a higher driving capability is required, a buffer amplifier may be connected to the voltage selection circuit 34, and the output of the buffer amplifier may be used as the output of the horizontal driver.

FIG. 11 is a block diagram showing another example of the configuration of the horizontal driver that can be used in this embodiment. The address register 30 and the first latch circuit 3 of the horizontal driver of FIG.
The first and second latch circuits 32 are similar to the horizontal driver of FIG.

In the horizontal driver shown in FIG. 11, the output data of the second latch circuit 32 is input to the pulse width modulator 41,
A pulse width corresponding to the display data is formed. The output of the pulse width modulator 41 determines the sampling timing of the S / H circuit / output circuit 42. S / H circuit / output circuit 42
As the input voltage, a voltage having a sawtooth waveform or a stepwise waveform is used. FIG. 12 shows a configuration example of the S / H circuit / output circuit 42 of FIG.

Referring to FIG. Wn is a signal from the pulse width modulator 41 in FIG. This signal Wn and C
A signal for determining the sampling timing of the S / H circuit (sample and hold circuit) SH1 using the logic circuits 53 and 54 from the signal obtained by dividing LK2 by 2 by the divide-by-2 circuit 51 and the sampling of the S / H circuit SH2 And a signal for determining the timing.

S / H circuit (sample hold circuit) SH
1 and SH2 are composed of analog switches 21 and 22, hold capacitors 23 and 24, and buffer circuits 25 and 26. The analog switch 21 includes a logic circuit 53
The analog switch 22 is turned on and off by the output signal of the logic circuit 54.
Controlled off.

Further, the output of the buffer circuit 25 is switched by the output signal of the divide-by-2 circuit 51,
6 outputs the output signal of the divide-by-2 circuit 51 to the inverter 52.
Is switched by the inverted signal. Note that the buffer circuits 25 and 26 do not need to be always in a driving state.
The driving state may be set for a certain period, and the high-impedance state may be set for other periods by a control signal or the like.

FIG. 13 is a waveform diagram showing an example of sampling and output timing of the S / H circuit. In FIG.
in is a sawtooth voltage having a period of 2H. SH1 indicates the sampling and output timing of the S / H circuit on the positive polarity side, and SH2 indicates the sampling and output timing of the S / H circuit on the negative polarity side.

The output signal Wn of the pulse width modulator 41 shown in FIG. 11 is at the H level, and the signal Lin obtained by dividing CLK2 by two.
When e is at L level, SH1 performs sampling, and W1
SH2 performs sampling when both n and Line are at the H level. The sampling time length is the same for SH1 and SH2. SH2 is in the output state when Line is at the L level, and SH1 is in the output state when Line is at the H level.

Here, by setting the sampling time length equal to or less than the negative output time length, the positive output time length can be obtained by subtracting the negative output time length from 2H. With the above configuration of the horizontal driver, the number of latch circuits and the number of input voltages can be reduced as compared with the horizontal driver of FIG.

In the configurations shown in FIGS. 11 and 12, it is assumed that the sampling time length of the S / H circuit is equal to or shorter than the negative output time length. As shown in FIG.
Three H circuits are required. FIG. 15 shows an example of the sampling / output timing of the S / H circuit at this time.

In FIG. 14, the S / H circuits A, B, and C have a format of sequentially sampling and sequentially outputting. Also,
The same drive can be performed by using the S / H circuits A and B for positive polarity and the S / H circuit C for negative polarity. Further, an analog horizontal driver using analog data as an input voltage requires 1H for sampling, and thus requires three or more S / H circuits.

For the vertical driver, the pulse width can be changed by using the shift clock CLK2 whose timing is shifted, so that it is not necessary to adopt a special configuration and usage method. Therefore, a conventional vertical driver, for example, a Hitachi LCD driver LSI data book P
HD66107 described in 274 to 292 can be used.

[0049]

As described above, according to the present invention, T
Even if the positive voltage writing time length of the FT takes one horizontal scanning cycle or longer, by increasing the length of time that the TFT is turned on at the time of positive voltage writing, the writing rate of the positive voltage can be reduced. Can be made the same as the writing rate. Therefore, it is possible to prevent flicker, image sticking, and the like caused by poor voltage writing of the positive polarity.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a circuit configuration of a liquid crystal display device as one embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a general liquid crystal display module.

FIG. 3 is a waveform diagram showing an example of a drive voltage waveform of a conventional liquid crystal display device.

FIG. 4 is a waveform diagram showing an example of a conventional liquid crystal drive voltage waveform and pixel electrode voltage writing timing.

FIG. 5 is a characteristic diagram showing a relationship example of a source current with respect to a gate-drain voltage of a TFT.

FIG. 6 is a waveform chart showing an example of operation waveforms of each part in the embodiment of FIG. 1;

FIG. 7 is a waveform diagram showing an example of a liquid crystal driving voltage waveform and a pixel electrode voltage writing timing according to the present invention.

FIG. 8 is a block diagram illustrating a configuration example of a horizontal driver according to an embodiment of the present invention.

FIG. 9 is a waveform chart showing an example of a signal waveform of each part of the horizontal driver of FIG. 8;

FIG. 10 is a circuit diagram showing an example of a voltage selection circuit in the horizontal driver of FIG.

FIG. 11 is a block diagram illustrating another configuration example of the horizontal driver according to the embodiment of the present invention.

FIG. 12 is a circuit diagram showing an example of an S / H circuit in the horizontal driver of FIG.

13 is a waveform diagram showing an example of sampling and output timings of the S / H circuit of FIG.

14 is a circuit diagram showing another specific example of the S / H circuit in the horizontal driver of FIG.

15 is a waveform chart showing an example of sampling timing and output timing in the S / H circuit of FIG.

[Explanation of symbols]

D1, D2 ... Dn ... drain wiring, G1, G2 ... Gm ...
Gate wiring, Vg1, Vg2, Vg3 ... gate wiring voltage,
Vd1: Drain wiring voltage, 1: control circuit, 2: frequency dividing circuit, 3, 4: monostable circuit, 5: logic circuit, 11 ...
Thin film transistor (TFT), 12: liquid crystal cell capacity, 1
DESCRIPTION OF SYMBOLS 3 ... Liquid crystal panel, 14 ... Horizontal driver, 15 ... Vertical driver, 33 ... Address register, 31-33 ... Latch circuit, 34 ... Voltage selection circuit, 41 ... Pulse width modulator, 42
... S / H circuit and output circuit, 35.
22, 45 ... analog switches, 23, 24, 46 ... hold capacity, 25, 26, 47 buffer circuits

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-322216 (JP, A) JP-A-63-95420 (JP, A) JP-A-5-94157 (JP, A) JP-A 64-64 57296 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 3/36 G02F 1/133 525 H04N 5/66 102

Claims (5)

(57) [Claims] 1. A gate wiring and a drain wiring are arranged in a matrix, a gate electrode of a transistor disposed at an intersection thereof is connected to the gate wiring, a drain electrode is connected to the drain wiring, and a source electrode is connected to the source electrode. A liquid crystal panel formed by connecting a liquid crystal forming a capacitor; a vertical drive circuit for applying a voltage for controlling on / off of the transistor to the gate wiring; and a positive voltage and a negative voltage as signal voltages to the drain wiring. And a horizontal drive circuit that alternately applies a negative voltage temporally. In the liquid crystal display device, the length of time during which the positive voltage is applied to the drain wiring is defined as the length of time during which the negative voltage is applied. The length is longer than the length and at least the transistor is turned on while a positive voltage is applied to the drain wiring. The length of the application time for applying the ON voltage to the gate wiring is longer than the length of the application time for applying the ON voltage to at least the gate wiring while the negative voltage is applied to the drain wiring. A liquid crystal display device characterized by being lengthened. 2. A gate wiring and a drain wiring are arranged in a matrix, and a gate electrode of a transistor disposed at an intersection thereof is connected to the gate wiring, a drain electrode is connected to the drain wiring, and a source electrode is connected to the source wiring. A liquid crystal panel formed by connecting a liquid crystal forming a capacitor; a vertical drive circuit for applying a voltage for controlling on / off of the transistor to the gate wiring; and a positive voltage and a negative voltage as signal voltages to the drain wiring. A liquid crystal display device comprising a horizontal drive circuit for alternately applying an active voltage alternately in time, a clock having a horizontal scanning cycle of a video signal to be displayed is represented by C
When LK1 is set, the clock CLK1 is fetched and frequency-divided by two, and the frequency-divided circuit divides the frequency by two, and the rising edge of the frequency-divided clock from the frequency-divided circuit is detected to form and output a first pulse. A first monostable circuit, a second monostable circuit that detects a fall of the divided-by-2 clock and forms and outputs a second pulse, and captures the first and second pulses. A logic circuit that performs a logical operation of both, and outputs the result as a clock CLK2. The horizontal drive circuit and the vertical drive circuit take in the clocks CLK1 and CLK2, respectively. Is applied longer than the time during which the negative voltage is applied, and accordingly, the time during which the positive voltage is applied to the drain wiring is reduced. At least, the length of time during which an on-voltage for turning on the transistor is applied to the gate wiring is applied, and while the negative voltage is applied to the drain wiring, the on-voltage is applied to at least the gate wiring. A liquid crystal display device characterized in that the application time is longer than the application time. 3. The liquid crystal display device according to claim 1, wherein the polarity of the voltage of the drain wiring is inverted each time a selected gate wiring changes, and the voltage of two adjacent gate wirings is changed. The sum of the lengths of the respective application times when the transistor ON voltage is applied is composed of two horizontal scanning periods of the video signal to be displayed, and the sum when the transistor ON voltage is applied to the gate wiring. A liquid crystal display device wherein the polarity of the voltage of the drain wiring is inverted for each frame of a video signal to be displayed. 4. The liquid crystal display device according to claim 2, wherein said horizontal drive circuit inputs a dot register synchronized with video data to be displayed and a shift register which inputs video data to be displayed. A first data latch circuit (31) for latching the input video data at an address designated by the output of the shift register, and the clock CLK1 having one horizontal scanning cycle of video data to be displayed as a clock input; The output of the first data latch circuit is fetched and held for one horizontal scanning period, and the second latch circuit (32) and the output CLK2 of the logic circuit are used as clock inputs, that is, display is to be performed. Occurs twice every two horizontal scanning periods of video data. The interval is a pulse that alternates between long and short intervals. By the column as a clock input, receives the output of said second latch circuit, the repetition of the long intervals and short intervals, a third latch circuit for holding the captured output (3
3) A liquid crystal display device comprising: 5. The liquid crystal display device according to claim 2, wherein the horizontal drive circuit receives a shift register (30) that inputs a dot clock synchronized with video data to be displayed, and inputs video data to be displayed. A first data latch circuit (31) for latching the input video data at an address designated by the output of the shift register, and the clock CLK1 having one horizontal scanning cycle of video data to be displayed as a clock input; A second latch circuit (32) which takes in an output of the first data latch circuit and holds the data for one horizontal scanning period, and output data of each stage of the second latch circuit which are input and output, respectively. A pulse width modulator (41) for outputting a pulse having a pulse width corresponding to data; Divide-by-2 circuit, a first gate circuit that opens a gate by the output of the divide-by-2 circuit to take in the output of the pulse width modulator, and a gate by a negative output of the divide-by-2 circuit. Open to capture the output of the pulse width modulator
, A first switch closed by an output of the first gate circuit while sampling a given sawtooth wave and holding the same in a first capacitance, and an output of the second gate circuit , While sampling a given sawtooth wave and holding it in a second capacitance
, A first buffer circuit that extracts a signal held in the first capacitor by an output of the divide-by-2 circuit and outputs the extracted signal as a first pulse, and a second buffer circuit that outputs a second signal by a negative output of the divide-by-2 circuit. And a second buffer circuit for taking out the signal held in the capacity of the second data and outputting it as a second pulse, wherein the first pulse and the second pulse are obtained by repeating two horizontal scanning periods of the video data. The first pulse is a pulse having a positive polarity at intervals longer than one horizontal scanning cycle.
A liquid crystal display device comprising: an output circuit (42) for outputting each of the pulses as negative pulses at intervals shorter than one horizontal scanning cycle.