JP3046601B2 - Common-mode noise removal circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] With regard to an in-phase noise elimination circuit, an object of the invention is to provide an in-phase noise elimination circuit that suppresses the generation of its own noise component. Detecting a voltage difference between a voltage resulting from the superposition of the components and a reference voltage, and applying a current having a magnitude corresponding to the voltage difference between a pair of terminals of the first set and a pair of terminals of the second set. A first output drive circuit having one terminal of each of the first set and the second set as an input, and a second output drive circuit having the other terminal of each of the first and second sets as an input. An in-phase noise elimination circuit that supplies a noise suppression current to each of the pair of signal lines by an output driving circuit, wherein a first circuit connected between the pair of terminals of the first pair; A second circuit connected between a pair of terminals; The circuit and the second circuit each form a main current path and a sub current path by connecting a plurality of transistors in series. Each of the main and sub current paths has a pair of transistors having different polarities. The base of the transistor of the first polarity is connected to the collector of the transistor of the first polarity in the main current path, and the base of the transistor of the second polarity in the sub current path is connected to the collector of the transistor of the second polarity in the main current path. Connecting the main current path of the first circuit between the pair of terminals of the first set and connecting the main current path of the second circuit between the pair of terminals of the second set. The base current of the transistor of the first polarity in each of the main current paths of the first circuit and the second circuit is supplied from a common constant current source, and the transistor of the second polarity in the main current path of the first circuit is supplied. Connect the pair of signal lines to the base Rutotomoni, characterized by being configured to supply the reference voltage to the base of the second transistor of opposite polarity of the main current path of the second circuit.

[Industrial applications]

The present invention relates to a common-mode noise elimination circuit, for example, to a common-mode noise elimination circuit used for a subscriber circuit of an exchange.

In general, in various systems in which analog circuits and digital circuits coexist (for example, the above-mentioned exchanges), the influence of radiation noise from digital circuits cannot be ignored, and this is a problem especially when the noise is superimposed on analog inputs. .

Therefore, the analog input is transmitted by two balanced wires, and the receiving end removes the common-mode voltage component of the two balanced wires. This is because the signal voltages (original transmission information) transmitted through the balanced two wires have an antiphase relationship, while noise and the like have an inphase relationship. Hereinafter, this noise or the like may be referred to as in-phase noise.

[Conventional technology]

2. Description of the Related Art A conventional in-phase noise elimination circuit as shown in FIGS.
Reference).

In FIG. 2, each of the two balanced lines A and B is connected to the input terminals a and b of the common-mode voltage detection / control circuit 1, and the common-mode voltage detection / control circuit 1 inputs the signals to the input terminals a and b. one-phase component of the signal to detect the voltage generated by superimposing, and outputs current that changes according to the voltage _{(i c, i a, i} e, i f) from terminal c~f respectively, current i _c, and a pair of i _d
The pair of i _e and _if changes complementarily. Note that ic is a current input to the terminal c, id is a current taken out from the terminal d, and a pair of terminals c and d in a pair relationship.
Are referred to as a first pair of terminals for convenience. Similarly,
ie is a current input to the terminal e, and if is a current taken out from the terminal f. The pair of terminals e and f in the pair relationship are referred to as a second pair of terminals for convenience. In FIG. 3 showing a specific configuration of the common-mode voltage detection / control circuit 1, a voltage appearing at a connection point (a) connecting the outputs of a pair of current mirror circuits 2a and 2b is a signal of two balanced two wires. Corresponds to the voltage generated by superimposing the in-phase components. If the balanced two lines do not include common-mode noise, the outputs of the current mirror circuits 2a and 2b are canceled out, and no voltage appears at the point (a). At this time, since the match between the current i ₁ flowing through the resistor R ₁ and the current i ₂ flowing through the resistor R _2, and i _c and i _e and i _d
i _f are equal, and therefore these currents i _c , i _e , i _d , i _f
There second view of a pair of output drive circuit 3a to the input, 3b of the operational amplifier 4a, 4b, the transistors Q _1a, do not drive the Q _1b, line A, the noise suppression current I _A to B, I _B is not supplied .

On the other hand, if the balanced two-wire contains common-mode noise, a voltage of a certain magnitude appears at the point (a), and the base current of one of the transistors Q _2a and Q _2b of the common-mode voltage detection / control circuit 1 increases. , I ₁ , i ₂ are unequal, so i _c , i _e ,
i _d, the balance of i _f collapses, op 4a of FIG. 2, 4b and the transistors Q _1a, line by Q _1b A, B to I _A, is I _B supplied.

Note that R _{3 to} R _{10 in} FIG. 2 are resistors, and Q _3a and Q _3b in FIG. ₃ are transistors.

[Problems to be solved by the invention]

However, in such a conventional common-mode noise elimination circuit, in FIG. 3, a pair of transistors Q _3a and Q _2b provided between terminals cd and a pair of transistors provided between terminals ef are provided. For the transistors Q _2a and Q _3b , a pair of transistors having different polarities, that is, an NPN transistor and a P
Since it is configured by the NP transistor, the current between the currents i _e and i _f output from the common-mode voltage detection / control circuit 1 and
Some current difference between the i _c and i _d there is trouble occurring.

That is, i _c is However, beta _N: current amplification factor of the NPN transistor also, i _d is Where β _P is determined by the current amplification factor of the PNP transistor, and the current difference Δi between i _c and i _d is Is required.

Here, if β _N ≫1 and β _P ≫1, the above equation becomes Becomes

This means that the base current of the PNP transistor And base current of NPN transistor And the difference (Δi) corresponding to the difference is i _c
And between i and _d . In general, making NPN and PNP transistors with the same current gain is virtually impossible due to the use of different junctions and Δi
Is inevitable. _{Therefore, i c ≠ i d, i} e ≠ i f become result, the difference between the unintentionally I _A and I _B equilibrium 2-wire, i.e. will occur after reversed phase component to be mistaken as the original transmission information, rather There was a problem that it became a source of noise components by itself.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a common-mode noise removal circuit that suppresses the generation of its own noise component.

[Means for solving the problem]

In order to achieve the above object, the common-mode noise removal circuit according to the present invention detects a voltage difference between a reference voltage and a voltage generated by superimposing an in-phase component of two signals input through a pair of signal lines, A current having a magnitude corresponding to the voltage difference is supplied to the first
And a first output drive circuit which flows between a pair of terminals of the first set and a second set of terminals and receives one terminal of each of the first set and the second set as an input. A second output drive circuit that receives the other terminal of each of the pair and the second pair as an input and supplies a noise suppression current to each of the pair of signal lines; A first circuit connected between the terminals, and a second circuit connected between the pair of terminals of the second set, wherein the first circuit and the second circuit each have a plurality of terminals. Transistors are connected in series to form a main current path and a sub-current path. Each main and sub-current path has a pair of transistors having different polarities, and a main current path is connected to the base of the first polarity transistor in the sub-current path. Connected to the collector of the transistor of the first polarity of the Connecting the base of the transistor of the second polarity to the collector of the transistor of the second polarity in the main current path, connecting the main current path of the first circuit between the pair of terminals of the first set, The main current paths of the two circuits are connected between the pair of terminals of the second set, and the base currents of the transistors of the first polarity of the main current paths of the first circuit and the second circuit are shared. The pair of signal lines are connected to the bases of the transistors of the second polarity in the main current path of the first circuit, and are connected to the bases of the transistors of the second polarity in the main current path of the second circuit. It is characterized in that the base is supplied with the reference voltage.

[Action]

As shown in FIG. 1, when currents flowing into and out of a pair of terminals of a first set are Ic and Id, and currents flowing in and out of a pair of terminals of a second set are Ie and If, respectively, a conventional technique ( Japanese Patent Application Laid-Open No. 59-161171) cannot accurately set ic = id and ie = if.
According to the above configuration, ic = id and ie = if can be set.

That is, in the prior art, a terminal for capturing ic
Two transistors having different polarities (PNP transistor Q3a and NPN transistor Q
2b) are connected in series, and the reference voltage (V _REF ) is applied to the base of one transistor (Q3a) and the common mode noise voltage is applied to the base of the other transistor (Q2b). Transistor base current) − (base current of the other transistor) = id. Since the base currents of transistors having different polarities do not exactly match, a difference is generated between 1c and id by the amount of the mismatch, and exactly ic = Could not be id. This means that even between ie and if, ie + (base current of one transistor) − (base current of the other transistor)
The same is true because = if.

On the other hand, in the present invention, the base current of the transistor of the first polarity of the main current path (Wc for convenience) is set to Ic (or Ie).
_npn ) is added, and the base current of the transistor of the second polarity in the main current path from Ic (or Ie) (X _{pnp for} convenience)
Is subtracted from the prior art in that
(Or Ie) is subtracted from the base current (for convenience, Y _nan ) of the transistor of the first polarity in the sub-current path, and Ic (or
The difference is that the base current (for convenience, Z _pnp ) of the transistor of the second polarity in the sub-current path is added to Ie). That is, in the present _{invention, Id = Ic + W npn -X} pnp -Y npn + Z
_pnp (or If = Ie + W _npn −X _pnp −Y _npn + Z _pnp ),
Since base currents of the same polarity exactly match each other, W _npn
−Y _npn = 0, X _pnp −Z _pnp = 0, so that Ic, Id and
The relationship between Ie and If is exactly Ic = Id and Ie = If.

It should be noted that the relationship between Ic and Id and the relationship between Ie and If are accurately expressed as Ic = Id,
The reason why Ie = If must be satisfied is that, as described above, the operation of the pair of output driving circuits 3a and 3b is stopped when the balanced two-wire does not include in-phase noise (balanced two-wire). This is because the noise suppression currents IA and IB are not supplied to _A and _B ). EXAMPLES Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a common-mode noise elimination circuit according to the present invention, and is a diagram corresponding to the common-mode voltage detection / control circuit 1 of FIG.

In FIG. 1, a common-mode voltage detection / control circuit 10 has a first circuit 11 and a second circuit 12 which are configured symmetrically. Note that these circuits 11 and 12 have the same configuration, differences, whereas the first circuit 11 is connected to a connection node of the resistors R ₁₃ and R ₁₄ (reference numeral B of FIG. 1) Thus, the second circuit 12 is connected to the reference voltage _VREF . Hereinafter, the first circuit 11 will be described as a representative.

The first circuit 11, a main current path 13 includes a sub-current paths 14 and mirror circuit 15, a main current path 13 NPN transistor Q ₁₀ is connected in series between a pair of terminals c-d, PNP transistor Q ₁₁
And it has a resistance R _10. Q ₁₀ and Q ₁₁ constitute a pair of transistors. The sub-current path 14 includes NPN transistors Q ₁₂ and Q ₁₂ connected in series between two power supplies (GND / V _BB ).
_13, and a PNP transistor Q _14, Q ₁₅ and resistors R _11. Q ₁₂ and Q ₁₅ form a pair of transistors. Also,
The mirror circuit 15 is configured by connecting an NPN transistor Q _{16 having} a common base and collector, a PNP transistor Q ₁₇ having a collector connected to V _BB , and a resistor R ₁₂ in series.

The common base of Q ₁₁ , Q ₁₄ , and Q ₁₇ is connected to terminals a and b via a connection point (b) and resistors R ₁₃ and R ₁₄ , and Q ₁₀ , Q ₁₃ , Q _{The 16} common bases are
It is connected to the constant current source 16 supplies a constant current I _0.

In such a configuration, when no voltage is generated at the connection point b, that is, when the signal input through the balanced two wires does not include the in-phase noise component, or includes only the reverse-phase signal component when the current through the terminal c-d and e-f, for example, when focusing on the first circuit 11, and i _c
must be equal to i _d .

Now, the current through R ₁₀ of the main current paths 13 and i _10, the current flowing in the sub-current paths 14 and i _11, when the i ₁₀ = i _11, the collector current I _c10 of Q ₁₀ is The collector current I _c13 of Q ₁₃ is The collector current I _c12 of Q ₁₂ is Becomes Therefore, the current i _{c at} terminal c is The current i _{d at} terminal d is And the current difference Δi between i _c and i _d is Is required. Here, if β _N ≫1 and β _P ≫1, Becomes This means that the current difference Δ1 between i _c and i _d can be suppressed to one half of the current amplification factor (β _N , β _P ) of each of a pair of transistors, that is, NPN and PNP transistors, The error can be suppressed to an almost negligible level.

The following is a conceptual description of such a mechanism for suppressing Δi.

That is, i _c becomes i _d through Q ₁₀ , R ₁₀ , Q ₁₁ ,
In this process, the base current I _B10 of Q ₁₀ is applied to the i _c, also the base current I _B11 of Q ₁₁ is subtracted from i _c. I
_B10 and there is no problem if equal I _B11, but is impossible to match the base current of different polarity of the transistor, here there is a factor of the above problems (i _c ≠ i _d).

Accordingly, in this embodiment, in the process, Q from i _c
Pull the base current I _B12 of _12, also the base current I Q ₁₅ to i _c
B15 is added. Thus, the I _B10 canceled by I _B12, further, I _B11 is canceled by I _B15. It pairs transistors of the same polarity (Q
_This can be realized by making Q ₁₂ for _{10 and} Q ₁₅ for Q ₁₁ ).

As a result, it is possible to maintain the relationship of _{i c = i d, i e} = i f,
Alternatively, even if there is an error, the error can be made extremely small so as to be negligible, and a common-mode noise removing circuit that suppresses the generation of its own noise component can be realized.

〔The invention's effect〕

According to the present invention, since the base current of each of the pair of transistors in the main current path and the base current of each of the pair of transistors in the sub current path cancel each other, the input / output current of the main current path (implemented) In the example, i _c and i _d , i _e
i _f ) can be matched, and a common-mode noise removal circuit that suppresses the generation of its own noise component can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a common-mode voltage detection / control circuit showing an embodiment of a common-mode noise elimination circuit according to the present invention. FIGS. 2 and 3 are diagrams showing a conventional common-mode noise elimination circuit. FIG. 3 is a configuration diagram of the same, and FIG. 3 is a configuration diagram of the common-mode voltage detection / control circuit. A and B are a pair of signal lines, c and d are a pair of terminals of a first set, e and f are a pair of terminals of a second set, c is one terminal of the first set, and d is a first set of terminals. the other terminal of the set of, e is one terminal of the second set, f is the other terminal of the second set, 3a first output driving circuit, 3b and the second output drive circuit, I _a, I _B is the noise suppression current, 11 is the first circuit, 12 is the second circuit, 13 is the main current path, 14 is the sub current path, 16 is the constant current source, and Q ₁₀ is the first polarity of the main current path. transistors, Q ₁₁ and the second polarity of the transistors of the main current path, Q ₁₂ is the first polarity transistor of sub-current paths, Q ₁₅ and the second polarity of the transistors of the auxiliary current path, V _REF is the reference voltage.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04Q 3/42 H04M 19/00-19/08 H04B 15/00-15/06

Claims (1)

(57) [Claims] A detecting means for detecting a voltage difference between a voltage generated by superimposing an in-phase component of two signals inputted through a pair of signal lines and a reference voltage, and outputting a current having a magnitude corresponding to the voltage difference; A first output drive circuit that flows between a pair of terminals of one set and a pair of terminals of a second set and receives one terminal of each of the first set and the second set as an input; And a second output drive circuit having the other terminal of the second set as an input and a noise suppression current supplied to each of the pair of signal lines by a second output drive circuit. And a second circuit connected between the pair of terminals of the second set. The first circuit and the second circuit each have a plurality of terminals. Are connected in series to form a main current path and a sub current path. The path having a pair of transistors of different polarities, connecting the base of the first polarity transistor of the sub-current path to the collector of the first polarity transistor of the main current path; Is connected to the collector of the transistor of the second polarity of the main current path, the main current path of the first circuit is connected between the pair of terminals of the first set, and A main current path is connected between the pair of terminals of the second set, and a base current of a transistor of the first polarity of each main current path of the first circuit and the second circuit is supplied from a common constant current source. Supplying the pair of signal lines to the base of the transistor of the second polarity in the main current path of the first circuit, and connecting the reference voltage to the base of the transistor of the second polarity in the main current path of the second circuit. To supply and configure Characteristic common-mode noise removal circuit.