JP3044634B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a write pulse generation circuit in an STRAM (Self-Timed RAM). 2. Description of the Related Art In recent years, as the performance of information processing apparatuses such as computers has become higher, the cycle time of the system has been required to be further reduced, and a synchronous STRAM controlled by a clock has been provided. In such an STRAM, a write pulse generation circuit capable of performing a stable write operation is demanded.

[0002]

2. Description of the Related Art In recent years, as information processing apparatuses such as computers have become more sophisticated, STRAMs capable of shortening the cycle time of a system have been provided. FIG. 6 is a block diagram showing a basic configuration of the STRAM. In the figure, reference numeral 101 is a write pulse generation circuit, 102 is an input data holding circuit, 103 is a RAM circuit block, 104 is an output data holding circuit, and 105 is a clock circuit.

As shown in FIG. 6, an STRAM comprises a RAM circuit block 103, an input data holding circuit 102 provided at an input of the RAM circuit block 103 and temporarily holding an input signal.
An output data holding circuit 104 provided at the output of the AM circuit block 103 for temporarily holding an output signal, and an input data holding circuit
A clock circuit 105 for controlling the capture and holding of data in the output data holding circuit 102 and the output data holding circuit 104; and
A write pulse generation circuit 101 for generating a predetermined write pulse at a predetermined timing is provided. In FIG. 6, reference numerals ADD indicate an address input, DIN indicates a data input, #CS indicates a chip select signal, #WE indicates a write enable signal, CLK indicates a clock input, and Dout indicates a data output. Here, the input data holding circuit 102 and the output data holding circuit 1
04 is composed of a latch circuit or a register circuit. The clock circuit 105 supplies clocks of appropriate timing to the input data holding circuit 102, the output data holding circuit 104, and the write pulse generation circuit 101, and obtains a clock of a required timing, for example. And a delay circuit that can be used.

[0004] By the way, the STRAM can be regarded as having substantially no skew because it synchronizes at the clock edge even if the input signal has skew.
Since no problem occurs even if the external input signal is redundant because the write pulse is created within the
Time can be improved (reduced). That is,
In a normal RAM, it is necessary to apply a write pulse from outside the RAM to write data, and at the time of writing, set a timing with a certain margin between the write pulse and other input signals. There is a need. for that reason,
In ordinary RAM, it is difficult to reduce the cycle time.

On the other hand, in a STRAM, a register or a latch controlled by a clock is provided at an input terminal and an input / output terminal, so that skew of input data can be eliminated and the STRAM is built in the STRAM. Since the write pulse is generated by the write pulse generating circuit 101, the timing of each signal can be set only by providing a minimum margin. As a result, the STRAM can shorten the cycle time and increase the speed. This STR
The reduction in cycle time in AM will have a noticeable effect at higher device speeds.

FIG. 7 is a block circuit diagram showing an example of a conventional semiconductor memory device, and shows a conventional example of the write pulse generating circuit 101 in FIG. Write pulse generation circuit
(101) generates a pulse from the clock CLK, inputs the clock CLK to two delay circuits 11 and 12 having different delay times, and performs an OR operation or an AND operation on the outputs of the delay circuits 11 and 12 To generate a write pulse. That is, as shown in FIG.
Is supplied to a first delay circuit 11 having a delay time td1 and a second delay circuit 12 having a delay time td2, and outputs of the first and second delay circuits 11 and 12
The output is made via an ND circuit 13 and a NOT circuit (inverter) 14. As a result, a write pulse having a pulse width of (td2−td1) is generated.

FIG. 8 is a timing chart for explaining the operation of the semiconductor memory device of FIG. As shown in the figure, if a positive pulse (high-level pulse) of the clock CLK is input to the clock input 3, the first delay circuit 11
Output A has a delay time td1 A positive pulse is output with a delay. On the other hand, the output B of the second delay circuit 12 has a delay time
td2 A negative pulse (low-level pulse) is output with a delay. Here, it is assumed that the delay time is td1 <td2.

The time (td2-td) when the output A of the delay circuit 11 and the output B of the delay circuit 12 both become high level "H".
A negative pulse having a pulse width of 1) is output (C) after a delay time td3 of the NAND circuit 13 after the output A rises,
Further, the signal is inverted by the NOT circuit 14, and is output from the output OUT as a positive pulse after a delay time td4 of the NOT circuit 14.

[0009]

As described above, FIG.
The conventional write pulse generation circuit shown in FIG.
By the difference between the delay times of the two delay circuits 11 and 12, the time (td2−
A write pulse having a pulse width of td1) is generated. Therefore, a write pulse having a pulse width longer than the pulse width of the clock CLK cannot be generated.

Incidentally, the duty ratio of the clock CLK (the ratio of the width of the high level "H" to the width of the low level "L" of the CLK) within the cycle time of the STRAM is determined by the RAM circuit block (1).
The minimum pulse width and the like are limited so that a write pulse having a pulse width sufficient for the write operation in 03) can be generated. However, as the cycle time is shortened with the recent increase in speed, the clock CLK is also speeded up, and it becomes difficult to generate a clock CLK having a constant duty ratio. That is, as a result of the variation in the duty ratio of the clock CLK, for example, the pulse width of the write pulse generated by the write pulse generation circuit is shortened, and it may be difficult to perform a normal write operation. .

The present invention has been made in view of the above-mentioned problems of the conventional semiconductor memory device (write pulse generation circuit of STRAM), and has a duty ratio of a clock, that is, a write having a pulse width independent of the pulse width of a clock signal. An object of the present invention is to provide an STRAM capable of generating a pulse and performing a normal writing operation.

[0012]

FIG. 6 is a block diagram showing the configuration of an STRAM, and FIG. 1 is a block diagram showing the principle of a semiconductor memory device according to the present invention. According to the present invention, a RAM circuit block 103 and the RAM circuit block
An input data holding circuit 102 and an output data holding circuit 104 provided at the input and output of the input / output circuit 103 for temporarily holding input / output signals; and the input and output data holding circuits 102 and 104
And a write pulse generation circuit 101 for generating a predetermined write pulse at a predetermined timing, wherein the write pulse generation circuit 101 Comprises an edge trigger type register 1 and a delay circuit 2 having a predetermined delay time td02, and a clock control selection circuit (9) , and the output 6; Q or the inverted output 7 of the edge trigger type register 1; Supplied to the reset or set terminal 5, reset via the circuit 2,
1 generates a write pulse of a predetermined pulse width regardless of the clock 3, CLK edge that is supplied to the pulse width of the clock 3, CLK from the outside, and, said clock control select circuit
According to the clock control selection signal (CONT.) Supplied to (9)
The write pulse output from the write pulse generation circuit 101
Whether the pulse width of the clock depends on the pulse width of the clock
A semiconductor memory device characterized in that the control is performed.

[0013]

According to the semiconductor memory device of the present invention, the write pulse generation circuit 101 includes the edge trigger type register 1 having a reset function, the delay circuit 2 having a predetermined delay time td02 , and the clock control selection circuit 9 . Have. The output 6 (Q) or the inverted output 7 (XQ) of the edge trigger type register 1 is supplied to the reset or set terminal 5 (reset) via the delay circuit 2, and the write pulse generation circuit
Reference numeral 101 denotes a circuit for generating a write pulse having a predetermined pulse width from the edge of the clock CLK (3) supplied from the outside irrespective of the pulse width of the clock CLK (3). further,
The write pulse generation circuit 101 is connected to the clock control selection circuit 9.
According to the clock control selection signal CONT.
Write pulse output from pulse generation circuit 101
Controls whether the width depends on the pulse width of the clock.
Control. That is, according to the semiconductor memory device of the present invention, as shown in FIG. 1, the output 6 (Q) of the edge trigger type register 1 is supplied to the delay circuit 2 for a predetermined time td02.
The one-shot circuit configured to supply the signal to the reset terminal 5 (reset) with a delay of only
As a self-timed RAM.

FIG. 2 is a timing chart for explaining the operation of the semiconductor memory device of FIG. As shown in FIGS. 1 and 2, according to the semiconductor memory device of the present invention, the edge trigger type register 1 controls the data input of the data terminal 4 when the clock CLK supplied to the clock input 3 rises.
Capture and hold Din (fixed to high level "H") and output Q
And outputs data corresponding to the data input Din. That is, first, when the clock CLK is at the low level “L” and the data input Din
Is fixed at "H" and the output Q is at "L", the reset input reset supplied to the reset terminal 5 via the delay circuit 2 is at "H".

Next, when the clock CLK changes from "L" to "H", the edge trigger type register 1 sets the data input Di.
n level (fixed to "H"), and outputs "H" to the output Q after the delay time td01 of the edge trigger type register itself. This output goes through the delay circuit 2, and after a delay time td02 of the delay circuit 2, the reset input reset is set to "L". As a result, the edge trigger type register 1 is reset, and the output Q becomes “L” after the delay time td03 of the edge trigger type register 1. This output Q ("L") again passes through the delay circuit 2, and the reset input reset is set to "H". If the clock CLK is set to "L" at any time during this period, the state returns to the initial state.

As described above, according to the semiconductor memory device of the present invention, the output Q of the edge trigger type register 1
A pulse (write pulse) having a pulse width corresponding to the sum of the delay times of the delay circuit 2 and the edge trigger type register 1 at the time of reset is generated without depending on the pulse width of CLK.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor memory device according to the present invention will be described below with reference to the drawings. FIG. 3 is a block circuit diagram showing one embodiment of the semiconductor memory device of the present invention, and shows the configuration of the write pulse generating circuit 101 in the STRAM shown in FIG. First, as shown in FIG. 6, the STRAM includes a RAM circuit block 103, and a RAM circuit block 103.
An input data holding circuit 102 for temporarily holding an input signal supplied to the RAM, an output data holding circuit 104 for temporarily holding an output signal of a RAM circuit block 103, an input data holding circuit 102 and an output data holding circuit 104 Clock circuit 105 that controls the capture and retention of data in memory
And a write pulse generating circuit 101 for generating a predetermined write pulse at a predetermined timing. Here, the input data holding circuit 102 and the output data holding circuit 104 are configured by a latch circuit or a register circuit as described above.

As shown in FIG. 3, a write pulse generating circuit (101) as one embodiment of the semiconductor memory device of the present invention.
Is an edge trigger type register 1, a delay circuit 2, and
A clock control selection circuit 9 is provided. In FIG. 3, reference numeral 3 is a clock input terminal (CLK), 4 is a data input terminal (Din), 5 is a reset terminal (reset), 6 is an output terminal (Q), and 7 is an inverted output terminal (XQ ), And 8 indicate a clock control selection terminal (CONT.).

The clock CLK is supplied to the clock input terminal 3 of the edge trigger type register 1, the data input Din of the data terminal 6 is fixed at a high level “H”, and the output Q is supplied to the RAM circuit block 103. An output terminal 6 for outputting a write pulse is supplied to the reset terminal 5 via the delay circuit 2 as a reset input reset. The delay circuit 2 includes a plurality of inverters 21 to 24.
And an NAND circuit 10. The output Q of the edge trigger type register 1 is supplied to one input of the NAND circuit 10, and the output of the clock control selection circuit 9 is supplied to the other input of the NAND circuit 10. Supplied. Here, the clock control selection circuit 9 is formed of a NAND circuit, and a clock CLK is supplied to one input of the NAND circuit, and a clock CLK is supplied to the other input of the NAND circuit via the clock control selection terminal 8. The control selection signal CONT. Is supplied.

Next, the operation of the above embodiment will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 4 is a timing chart for explaining a normal operation of the semiconductor memory device of FIG. As shown in FIG. 4, when the clock control selection signal CONT. Is fixed at a low level "L", the output (node E) of the clock control selection circuit 9 is always fixed at a high level "H". Therefore, the other input of the NAND circuit 10 in the delay circuit 2 is fixed at “H”, and the output of the NAND circuit 10 is
The output Q of the edge trigger type register 1 supplied to one of the inputs is inverted. And first, the clock
When CLK is “L”, data input Din is fixed at “H”, output Q is “L” and inverted output XQ is “H”, NAND circuit
10 and a reset input reset supplied to a reset terminal 5 via a delay circuit 2 composed of inverters 21 to 24
Becomes "H".

Next, when the clock CLK changes from "L" to "H", the edge trigger type register 1 stores the data input Di.
n, and after the delay time td01 of the edge trigger type register itself, "H" is output as the output Q and "L" is output as the inverted output XQ. The output Q at the "H" level passes through the delay circuit 2 and sets the reset input reset to "L" after a delay time td02 of the delay circuit.
As a result, the edge trigger type register 1 is reset, and the output Q becomes “L” after the delay time td03 of the edge trigger type register 1. This output Q ("L") again passes through the delay circuit 2 to set the reset terminal reset to "H". If the clock CLK is set to "L" at any time during this period, the state returns to the initial state.

As described above, the delay time td02 of the delay circuit 2 and the delay time of the edge trigger type register 1 at the time of reset are applied to the output Q (output terminal 6) of the edge trigger type register 1 independently of the pulse width of the clock CLK. Sum of td03 (td02 +
A pulse (write pulse) having a pulse width of td03) can be generated. FIG. 5 is a timing chart for explaining the operation of the semiconductor memory device of FIG. 3 during a test. As shown in FIG. 5, the clock control selection signal CON
When T. is fixed to a high level "H", the output (node E) of the clock control selection circuit 9 is the clock CLK inverted with a delay of the delay time td04 of the clock control selection circuit 9. Therefore, the output of the NAND circuit 10 in the delay circuit 2 becomes “L” only when both inputs of the NAND circuit 10 are “H”. First, when the clock CLK is “L”, the node E is “H”, the data input Din is fixed at “H”, the output Q is “L” and the inverted output XQ is “H”, the NAND circuit 10 and The reset input reset supplied to the reset terminal 5 via the delay circuit 2 constituted by the inverters 21 to 24 becomes "H".

Next, when the clock CLK changes from "L" to "H", the edge trigger type register 1 sets the data input Di.
n, and after the delay time td01 of the edge trigger type register itself, "H" is output as the output Q and "L" is output as the inverted output XQ. At this time, the node E changes from “H” to “L” with a delay of the delay time td04 of the clock control selection circuit 9. Here, the output Q of the edge trigger type register 1 and the output (node E) of the clock control selection circuit 9 are supplied as inputs of the NAND circuit 10 in the delay circuit 2, and both the output Q and the node E are " When the signal goes high, the output of the delay circuit 2 goes low after the delay time td02 of the delay circuit, and the reset input
Set reset to “L”. As a result, the edge trigger type register 1 is reset, and the edge trigger type register 1 is reset.
After the delay time td03, the output Q becomes "L". This output Q ("L") again passes through the delay circuit 2
Set reset to “H”. Clock at any time during this time
When CLK is set to “L”, the state returns to the initial state. Here, the time during which the clock CLK is at the high level is td00, and td00
Assuming that 00 <td01, the output Q of the edge trigger type register 1 is
(Td02 + td03 + td04)
+ Td00-td01). That is, the width of the write pulse includes the pulse width of the clock CLK.

As described above, the width of the write pulse corresponds to the clock CL.
By including a time td00 during which K is at a high level, for example, when performing failure analysis of the STRAM itself, a clock CLK having a long pulse width is given to generate a write pulse having a long pulse width, By supplying the write pulse having the long pulse width to the RAM circuit block 103, it is possible to determine whether or not the cause of the defect exists in the write pulse generation circuit.

Although the output Q (6) of the edge trigger type register 1 is used in the above embodiment, a write pulse is generated using the inverted output XQ (7) of the edge trigger type register 1. You can also. Specifically, for example, the above-described embodiment is provided by supplying the inverted output XQ of the edge trigger type register 1 to one input of the NAND circuit 10 of the delay circuit 2 in FIG. 3 and adding (or removing) one inverter. A write pulse generating circuit performing the same operation as that described above can be configured. Further, in the above embodiment, the write pulse generation circuit is configured by using the reset terminal reset (5) of the edge trigger type register 1, but the set terminal of the edge trigger type register 1 (the reset terminal 5 in FIG. It is needless to say that a similar write pulse generation circuit can be configured even if the

As described above, by incorporating a one-shot circuit capable of generating a predetermined pulse width without depending on the pulse width of the clock CLK as a write pulse generation circuit, a stable write operation can be performed. STRAM can be realized. When performing a failure analysis or the like, the clock control selection signal is switched, and the circuit is changed so that the write pulse depends on the pulse width of the clock CLK. It will be possible to determine whether it exists.

[0027]

As described above in detail, according to the semiconductor memory device of the present invention, a write pulse having a pulse width independent of the pulse width of a clock signal is generated to perform a normal write operation. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of a semiconductor memory device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the semiconductor memory device of FIG. 1;

FIG. 3 is a block circuit diagram showing one embodiment of the semiconductor memory device of the present invention.

FIG. 4 is a timing chart for explaining a normal operation of the semiconductor memory device of FIG. 3;

FIG. 5 is a timing chart for explaining an operation at the time of test of the semiconductor memory device of FIG. 3;

FIG. 6 is a block diagram showing a basic configuration of an STRAM.

FIG. 7 is a block circuit diagram showing an example of a conventional semiconductor memory device.

FIG. 8 is a timing chart for explaining the operation of the semiconductor memory device of FIG. 7;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 edge trigger type register 2 delay circuit 3 clock input terminal 4 data input terminal 5 reset terminal (set terminal) 6 output terminal 7 inverted output terminal

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-1-119986 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/40-11/419

Claims (4)

(57) [Claims] 1. A RAM circuit blocks and the input data holding circuits and output data holding times for temporarily holding the input and output signals at the input and output of the RAM circuit block
In the semiconductor memory device including a road, a clock circuitry for controlling data capture and retention in the input and output data holding circuit, and a write pulse generating circuits for generating a predetermined write pulse at a predetermined timing there are, the write pulse generating circuits, the delay circuits having between edge-triggered register Contact <br/> spare time predetermined delay, and clock
The edge trigger type register.
Chikarama was is supplied to the reset or set pin anti inverted output is via the delay circuit,該書write pulse generating circuit,
Generating a write pulse of a predetermined pulse width regardless from the edge of the clock to be supplied to the pulse width of the external clock
And a clock supplied to the clock control selection circuit
Output from the write pulse generation circuit according to the control selection signal
The pulse width of the clock pulse to be written
A semiconductor memory device for controlling whether or not to depend on the semiconductor memory device. Wherein said write pulse generating circuits, the delay times
Claim 1 of the semiconductor memory, wherein the benzalkonium to generate a write pulse of a more defined by the pulse width between time put <br/> Ru delay to the edge-triggered register and contact between the time delays of the road apparatus. Wherein the delay circuitry is through / clamp is controlled by the clock, it has the features that shall write pulse outputted from the write pulse generating circuit and depends on the pulse width of the clock Claims characterized by
Item 1. The semiconductor memory device according to Item 1 . An edge-triggered les <br/> Soo data with 4. A reset function, a delay circuits having between at predetermined delay, anti-transfer-out force was Chikarama out of the edge-triggered register the is supplied to the reset or set pin through the delay circuits, the one-shot circuit for generating a pulse of a predetermined width regardless of clock edges that are externally supplied to the pulse width of the clock as a write pulse generating circuit Built- in
The write pulse generation circuit further includes a clock control selection circuit.
And a clock control circuit for supplying the clock control selection circuit.
Output from the write pulse generation circuit in response to a selection signal.
The pulse width of the write pulse
Timed RAM which is characterized by controlling whether or not to rely.