JP2907250B2 - External synchronous signal control type input / output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output circuit for transmitting data to a memory circuit, and more particularly, to an external synchronization signal input from an external terminal to determine whether or not address data should be transmitted to a static memory circuit. The present invention relates to an external synchronous signal control type input / output circuit to be controlled.

[0002]

2. Description of the Related Art In recent years, the application field of a static memory circuit as a cache memory of a processor has been expanded in order to take advantage of its high-speed access characteristic. In this type of system, in order to realize a faster cycle time, a static memory circuit having an external synchronization signal control type input / output circuit that controls an input / output circuit with an external synchronization signal input from an external terminal is required. Has been put to practical use.

Referring to a conventional example of an external synchronous signal control type input / output circuit shown in FIG. 5, ADD and ADD 'are external address signals and their internal signals, CLK and CLK' are external synchronous signals and their internal signals, and al to al. a12 is an inverter circuit, b1 is P
Channel MOS transistor, c1 is an N-channel MOS
It is a transistor.

[0004] Inverter circuits a4 to a6 constitute a storage element 10 of a static memory circuit. The P-channel MOS transistor b1 and the N-channel MOS transistor c1, which are complementary elements, and the inverter circuit a3 form a transfer gate element 11, whose conduction and non-conduction are controlled by an internal synchronization signal CLK '. The transfer gate element 10 and the storage element 11 are connected in series. The inverter circuits a1 and a2 constitute an input buffer circuit 12, and the inverter circuits a7 to a12 constitute an internal synchronization signal buffer circuit 13.

The operation of the external synchronizing signal control type input / output circuit shown in FIG. 5 will be described with reference to an internal operation waveform diagram shown in FIG. In FIG. 6, the external synchronization signal CLK is a signal having a constant cycle synchronized with the cycle time of the system. Accordingly, the internal synchronization signal CLK 'also operates at a constant cycle.

When the internal synchronization signal CLK 'changes from low level to high level, the transfer gate element 11
Becomes non-conductive. Therefore, the external address signal ADD
Is stored in the storage element 10 and transmitted to the internal address signal ADD '.

Next, when the internal synchronization signal CLK 'changes from the high level to the low level, the transfer gate element 11 becomes conductive. Therefore, the external address signal A
The information of an arbitrary address m input to the DD is stored in the storage element 10.
Through the internal address signal ADD '.

According to the conventional circuit configuration, the normal information (address n) to be given to the external address signal ADD is required only during the period when the external synchronization signal CLK changes from a low level to a high level. Is a high level period, the internal address signal ADD 'holds regular information even if arbitrary information is given in other periods. Therefore, the time limit of the regular information (address n) to be given to the external address signal ADD is relaxed, and the cycle time can be shortened.

In general, an external synchronous signal control type input / output circuit applied to a static memory circuit has a large number of semiconductor circuits mounted thereon. Noise also occurs in the power supply wiring from the operation of the tick memory circuit itself.

The operation of the conventional address input / output circuit when such noise occurs will be described with reference to FIG.

FIG. 7 shows a case where upward noise is generated in the GND wiring. In such a case, for example, even when the external synchronization signal CLK is at a sufficiently high level, the effective input voltage is determined by the difference voltage between the high level potential of the external synchronization signal CLK and the potential of the GND wiring.
Therefore, when upward noise is generated with respect to GND, the address input circuit senses the low level for a moment.
In this case, downward noise is added to the internal synchronization signal CLK '.

[0012]

However, the change of the internal synchronization signal CLK 'has a serious adverse effect on the external synchronization signal control type input / output circuit. That is, due to this change, the transfer gate element shifts from the non-conductive state to the conductive state for a moment. Therefore, at this time, the information of the arbitrary address given to the external address signal ADD is transmitted to the storage element, and the transfer gate element returns to the non-conductive state again, so that the information of the address m is held. . As a result, the information transmitted to the internal address signal ADD 'changes from the normal address n to the address m, causing a malfunction. Therefore, the high-level threshold voltage of external synchronization signal CLK is significantly deteriorated.

[0013]

According to the present invention, an information storage circuit is formed by connecting a storage element and a transfer gate element which controls transmission to the storage element, and an input signal of the transfer gate element is supplied to an external device. In an external synchronization signal control type input / output circuit for controlling transmission and reception of data by a control signal based on an external synchronization signal input from a terminal, noise is superimposed on the external synchronization signal, and the superposed noise is Receiving an internal pulse signal for generating an internal pulse signal for canceling the logical change during a period in which a logical change occurs in the information storage circuit; and an external synchronizing signal and the internal pulse signal in which the noise is superimposed. A noise logic change canceling circuit for outputting, as the control signal, an external synchronizing signal from which the noise multiplication has been cancelled. Part synchronous signal controlled output circuit is obtained.

[0014]

[Operation] When noise is generated, the internal pulse generation circuit
Generate an internal pulse signal. In the noise change canceling circuit, a logical change due to noise is canceled according to the internal pulse signal.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An external synchronization signal control type input / output circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a case where an external synchronizing signal control type input / output circuit according to an embodiment of the present invention is applied to an address input circuit as in the conventional example, and FIG. 2 shows an internal operation waveform thereof.

The external synchronizing signal control type input / output circuit of this embodiment includes storage elements 20 and 22 of a static memory circuit and a transfer gate element 21. The difference from the conventional example of FIG. 23 and a noise logic change canceling circuit 24. The noise logic change canceling circuit 24 includes various gate circuits (inverter circuit a1).
4, a15, a16, a17, a two-input NOR circuit d2,
It is composed of two-input NAND circuits e1 and e2) and includes a delay circuit formed by inverter circuits a14 and a15.

Referring to FIGS. 1 and 3, internal pulse generating circuit 23 includes an internal synchronizing signal buffer circuit 13 for generating internal synchronizing signal CLK 'which is the same as the conventional example. When noise occurs at the CLK terminal, the internal synchronization signal CLK 'from the internal synchronization signal huffer circuit 13 causes a low-level logic change shown by a downward V-shaped character. Internal pulse signal O only period t ₀ by the delay circuit so as to cancel a signal of the logic change the high level
Generate S. Thereby, the logical change of the noise can be canceled, and the node n1 is not affected by the noise at all.

That is, when upward noise is generated in the GND wiring, downward noise is added to the internal synchronization signal CLK 'as in the conventional example. However, at the same time, the node n1 keeps the high level state due to the high level internal pulse signal OS. Therefore, the transfer gate element 21 maintains the non-conductive state, and is non-conductive from the storage element 201 to the storage element 22 of the static memory circuit. As a result, the normal address information transmitted to the internal address signal ADD 'does not change.

Next, referring to FIG. 4, the input / output circuit of the external synchronization signal control type of the present invention is connected to a sense amplifier output S.
AOUT, the output of which is the output DO of the static memory circuit
Needless to say, even if the UT is changed to the UT, as in FIG.

It is needless to say that the present invention is not limited to the above-described embodiment, but is effective for all embodiments including the configuration of the present invention.

[0021]

As described above, according to the present invention,
Since the internal pulse generating circuit and the noise logic change canceling circuit are provided, there is an effect that malfunction due to noise can be prevented.

[Brief description of the drawings]

FIG. 1 is an external synchronization signal control type input / output circuit according to a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram of FIG.

FIG. 3 is an operation waveform diagram when noise occurs in the power supply wiring of FIG. 1;

FIG. 4 is an external synchronization signal control type input / output circuit according to a second embodiment of the present invention.

FIG. 5 is a conventional example of an external synchronization signal control type input / output circuit.

6 is an operation waveform diagram of FIG.

FIG. 7 is an operation waveform diagram of FIG. 5 when noise occurs in a power supply wiring.

[Explanation of symbols]

 Reference Signs List 13 delay circuit 20, 22 storage element 21 transfer gate element 23 internal pulse generation circuit 24 noise change canceling circuit ADD external address signal ADD 'internal address signal CLK external synchronization signal CLK' internal synchronization signal a1 to a17 inverter circuit b1 P-channel MOS transistor c1 M-channel MOS transistor n1 Node d1, d2 NOR circuit e1, e2 NAND circuit SAOUT Sense amplifier output DOUT output OS Internal pulse signal

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/413 H03K 19/003

Claims (2)

(57) [Claims] An information storage circuit is formed by connecting a storage element and a transfer gate element that controls transmission to the storage element, and an input signal of the transfer gate element is
In an external synchronization signal control type input / output circuit that controls transmission and reception of data by a control signal based on an external synchronization signal input from an external terminal, noise is superimposed on the external synchronization signal, and the superimposition is performed. An internal pulse generation circuit for generating an internal pulse signal for canceling the logical change during a period in which a logical change is caused in the information storage circuit by noise, and an external synchronizing signal and the internal pulse signal in which the noise is superimposed. A noise logic change canceling circuit for receiving, as the control signal, an external synchronizing signal from which the superposition of the noise has been canceled. 2. The external synchronous signal control type input / output circuit according to claim 1, wherein said internal pulse generation circuit is a two-input logical sum circuit, a two-input logical product negation circuit, a two-input logical product circuit, and a delay circuit. The two-input OR circuit;
An input NAND circuit and a delay circuit each receive an external synchronizing signal on which the noise is superimposed, and the delay circuit outputs a delayed signal to each of the two-input OR circuit and the two-input AND circuit. And outputs the logical sum output from the two-input logical sum circuit and the logical negation output from the two-input logical negation circuit as inputs to the two-input logical product circuit. An external synchronization signal control type input / output circuit, which outputs the internal pulse signal.