JP3043830B2 - PCM audio recording and playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio recording / reproducing apparatus, and more particularly to a super VHS (registered trademark) (S-VH).
The present invention relates to a PCM audio recording / reproducing apparatus which records an audio signal by a pulse code modulation (PCM) method by applying to an S) system video tape recorder (VTR) or the like.

[0002]

2. Description of the Related Art In a conventional VTR, the recording and reproduction of an audio signal, which is initially started with a fixed head system, is performed by a helical scan in order to cope with a reduction in tape speed in a long recording mode and audio multiplexing of television broadcasting. The recording and reproduction of the FM system, that is, the so-called HiFi (HiFi) audio system has been shifted. For example, in the VHS-HiFi method, a method of FM-modulating each carrier of 1.3 MHz and 1.7 MHz with a stereo audio signal and recording the audio FM signal in a deep layer by a rotary head of ± 30 degrees azimuth is adopted.

[0003]

The above-mentioned conventional VTR
In the HiFi audio system, the reproduced FM signal is not completely continuous because the reproduced signal of the two heads is spliced by the head switching signal. For this reason,
There is a problem that the reproduced audio signal is distorted every 30 Hz in accordance with the head switching signal.

Further, with the enhancement of digital audio sources such as B-mode (PCM) satellite broadcasting and the like, a VTR audio signal recording / reproducing apparatus capable of obtaining sound quality equivalent to that of a compact disk (CD) and digital audio tape recorder (DAT) system. Was eagerly awaited.

In order to solve the above-mentioned problems, the present invention multiplexes a PCM audio signal with a conventional FM audio signal, magnetically records the multiplexed signal, and places a higher order on the conventional device without adding a new recording / reproducing head. It is an object of the present invention to provide a PCM audio recording / reproducing device capable of ensuring compatibility.

[0006]

In order to solve the above-mentioned problems, according to the present invention, a predetermined number of subframe signals are generated from a digital audio signal for one TV frame, and the signals are used for error detection and correction. A signal having a subframe unit number one less than one TV frame is interleaved in a frame, and a signal in which a subframe unit signal is interleaved between frames is de-multiplexed.
Deinterleaving means for performing an interleaving process, the deinterleaving means storing first and second memories for storing a signal of one subframe unit less than one TV frame, and storing a signal of one subframe unit A third memory, and address conversion means for controlling a signal writing / reading process for the first to third memories, wherein the address conversion means converts a signal of a sub-frame unit to be de-interleaved in the frame to the first memory. Alternatively, a signal stored in the second memory and read from the other memory are read, and deinterleaving processing in the frame is performed by controlling the write / read position and timing of the signal.
A signal in units of subframes for performing deinterleaving between frames is written in the third memory, and deinterleaving processing between frames is performed by controlling the read timing of the signal written in the third memory. Things.

[0007] Further, the de-interleave circuit is characterized in that the delay time due to the de-interleave processing is set to one TV frame period or less.

[0008]

In the PCM audio recording and reproducing apparatus according to the present invention,
In FIG. 24 showing an example of the interleave circuit 31,
Reverse mirror-scared converted serial binary signal SBD
Is converted into an 8-bit code by a serial / parallel converter 161 and output to an octal D-latch 162. The octal D-latch 162 latches the input 8-bit signal as a PCM data symbol and a parity symbol of PCM data (hereinafter referred to as a data symbol) in synchronization with the data latch pulse supplied from the preceding sub-code decoding circuit 29. And RAM 181 and 18
2 and the auxiliary RAM 185.

The RAM 181 and the RAM 182 each have a memory capacity of 9 subframes out of 10 subframes of decoded data symbols per TV frame, and the auxiliary RAM 185 has a memory capacity of 1 subframe.
Ten sub-frames for one TV frame are written in the RAM 181 and the auxiliary RAM 185, and ten sub-frames for the next one TV frame are written in the RAM 182 and the auxiliary RAM 185.
Is written to. Therefore, the RAM 181 and the RAM 182 are alternately controlled to a write state and a read state every 1 TV frame period based on the 15 Hz WE pulse (FIG. 2).
5). The read address signal supplied from the read address counter 166 is converted into a write address by the write address conversion ROM 165,
RA via address selectors 171, 172, 175
M181, 182 and the write address of the auxiliary RAM 185 are controlled.

RAM 181 or RAM 182 and auxiliary R
The decoded data symbols input to the AM 185 are interleaved in blocks and between blocks in the recording system. Of these, interleaving between blocks,
That is, the inter-block de-interleaving (the process of returning the interleaving) to the interleaving in units of subframes is performed by storing the data symbols in the RAM 181 or 18.
2, when writing to the auxiliary RAM 185 is performed by the write address signal supplied from the write address conversion ROM 165. That is, inter-block deinterleaving is performed simultaneously with writing of each subframe.

In each reading period, each data symbol is sequentially read from the RAMs 181 and 182 and the auxiliary RAM 185, and the logical sum circuit 191 and the data distributor 192 are read.
Through the RAM 20 of the next stage (error detection / correction circuit 32)
1, 202 and written. RAM 181,
182, reading from the auxiliary RAM 185 is controlled by a read address signal supplied from a read address counter 166 via the address selectors 171, 172, 175. Writing to the RAMs 201 and 202 is controlled by a write address signal supplied from the write address conversion ROM 193 via the address selectors 195 and 196.

Here, the write address conversion ROM 19
3 converts the read address signal supplied from the read address counter 166 into a write address signal necessary for the de-interleaving process in the block. 182,1
The data is read out from the RAM 85 and transferred to the RAMs 201, 201 and executed at the same time.

As described above, the RAM (RAMs 181 and 182 and the auxiliary RAM 185) having a memory capacity less than half
Total memory capacity) and write address conversion ROM 16
6,193, inter-block de-interleaving is performed at the same time as writing to RAM, and de-interleaving within blocks is performed at the same time as reading from RAM. can do.

[0014]

Next, an embodiment of a PCM audio recording / reproducing apparatus according to the present invention will be described in detail with reference to the drawings.

In order to meet the above-mentioned demand, S-VHS V
Format related to PCM audio recording for TR
"Recording format" has been published ("JVC, prototype of VTR capable of recording digital audio signals", Nikkei Electronics, January 1990).
No. 22, issue No. 491, p. 93).

The recording format is a standard for ensuring compatibility when reproducing an audio signal.
The specification in the SC system is shown. In the figure, 48 kHz-2 channel mode (hereinafter, referred to as “48 k-mode”) is a B mode satellite broadcast (hereinafter, referred to as “BS”) or DAT.
The 32 kHz 4-channel mode corresponds to European MAC satellite broadcasting, Japanese satellite broadcasting A mode, and DAT option 3 mode. In addition, for each mode, specifications for systems other than the NTSC system are shown, but are omitted.

FIG. 2 is a diagram showing the track pattern in FIG. 1 in the case of the NTSC system. FIG. 2 (A)
1 shows a relationship between an analog audio signal and a digital audio signal obtained by sampling for one TV frame. FIG. 2B shows a track pattern of a digital audio signal deeply recorded on a video track.

FIG. 3 is a diagram showing a block format in each video track of the NTSC system.
One track is composed of a total of 156 blocks including a preamble (4 blocks), a data block (150 blocks = 5 subframes), and a postamble (2 blocks). Further, each data block includes data (31 symbols, where one symbol is 8 bits), a synchronization code SYNC.
(4EH), a subcode W1 (8 bits), W2 (8 bits), and a parity code P (8 bits) are shown as being composed of a total of 35 symbols (280 bits).

FIG. 4 is a block diagram showing an example in which the PCM audio recording / reproducing apparatus according to the present invention is applied to an S-VHS VTR. Hereinafter, based on this block diagram, [I]
The recording system (shown in the upper part of FIG. 4) and the [II] reproducing system (shown in the lower part of FIG. 4) are divided into two sections, and the 48k-mode will be described as an example. When the circuit configuration and the description of the processing content for each signal of channel 1 (L) and channel 2 (R) are similar, only the channel 1 (L) is shown and the overlapping circuit for channel 2 (R) is shown. The configuration and description are omitted.

[I] Recording System In FIG. 4, reference numeral 1 denotes an input terminal for L and R digital audio signals, which is connected to, for example, a digital output terminal of a BS tuner. The input digital audio signal is supplied to an error correction code (ECC) adding circuit 7 via an input selector 6.

Reference numeral 2 denotes an input terminal for L and R analog audio signals. The input analog audio signal is supplied to an analog-digital (A / D) converter 5 via a low-pass filter (LPF) 3 in order to prevent aliasing during reproduction. The LPF 3 is composed of, for example, a combination of a third-order LC filter and a digital filter, or a ninth-order active filter.

Reference numeral 4 denotes a timing generation circuit. The timing generation circuit 4 operates at 52.416 MHz (or 26.2 MHz).
08 MHz), a sampling clock, a bit clock BCK, etc. are generated from the
It is supplied to the D converter 5 and each circuit block (not shown).

Reference numeral 5 denotes an A / D converter. The A / D converter converts an input analog audio signal into a digital audio signal by 16-bit linear quantization based on the sampling frequency fs, channel clock, bit clock BCK, and the like supplied from the timing generation circuit 4. The A / D converter 5 is a 1-bit A
A / D converter or a 16-bit integrating A / D converter is employed.

Reference numeral 6 denotes an input selector. Input selector 6
A / D converts A / D between a digital signal input through the input terminal 1 and an analog signal input through the input terminal 2.
Either the digital signal output from the / D converter 4 is selected, and an error correction code (ECC) adding circuit 7 is selected.
To supply.

Reference numeral 7 denotes an ECC adding circuit. The digital signal input to the ECC adding circuit 7 has 648 symbols (= 27 symbols × 24 data blocks) as one block as shown in FIG.
3240 symbols), that is, one TV frame at a time in the random access memory (RAM). For the stored data, the ECC addition circuit 7 applies 282
Parity code of a symbol, that is, a duplex Reed-Solomon code C1 (31, 27, 5) for error correction / detection,
C2 (30, 24, 7) is generated and added. Therefore,
One block has 930 symbols (= 648 + 282 symbols).

The ECC addition circuit 7
This will be described later in detail.

Reference numeral 8 denotes an interleave circuit. The interleave circuit 8 has 9300 symbols (= 1TV frame) to which a parity code has been added by the ECC addition circuit 7.
930 symbols × 5 blocks × 2 channels) are interleaved. Interleaving is a well-known method for coping with intensive loss of data in a defective portion of a tape, that is, a burst error. That is, the order of the symbols and blocks is interchanged and recorded on the tape, and the interleave is returned (de-interleaved) at the time of reproduction, thereby converting the burst error into a substantially random error, thereby facilitating data correction and correction. Is to try.

In this embodiment, the parity code C
Simultaneously with the calculation of C1 and C2, the frames O00 and E00, O01 and E01,..., O04 and E04 shown in FIG. Are formed. In addition, each of the subframes E00 to E
04, O00 to O04, etc. are rearranged by the inter-block interleaving like the track pattern shown in FIG. Further, as shown in FIG. 3, the block includes a synchronization code Sync indicating the start of the block, an address subcode W1 indicating the subframe and the block address,
Four symbols of an ID subcode W2 indicating a mode and the like and a parity code Parity of the subcodes W1 and W2 are added.

The interleave circuit 8 will be described later in detail.

Reference numeral 9 denotes a mirror-scared (M ² ) conversion circuit. M ² conversion circuit 9, the data input from the interleave circuit 8, C1 parity, and M ² converts the C2 parity subcode W1 as an initial value, converted to M ² code.
The M ² conversion limits the run length of the recording code, converts the recording code into a DC-balanced recording code, and outputs it as serial data, in order to match the differential transfer characteristic of the magnetic recording system.

The M ² conversion circuit 9 will be described later in detail.

Reference numeral 10 denotes a pre- and postamble adding circuit. The pre- and post-amble adding circuits perform the respective track data output from the M ² conversion circuit 9 (see FIG. 3).
The serial data obtained by adding four blocks of the preamble pattern (90H) and two blocks of the postamble pattern (90H) before and after the QDPSK circuit 11
Output to

Reference numeral 11 denotes a QDPSK (four-phase differential phase modulation) circuit. The QDPSK circuit 11 performs four-phase modulation using a point before the modulation point as a reference phase.

FIG. 5 is a block diagram showing an example of the QDPSK circuit 11.

In FIG. 5, a serial / parallel converter 62 takes in two bits of serial data 61 supplied from the pre- and postamble adding circuit 10 and converts them into parallel two bits (dibits). The difference conversion circuit 63 generates two bit sequences from the current dibit with reference to the immediately preceding dibit, and supplies one to the balanced modulation circuit 65 and the other to the balanced modulation circuit 66. The balance modulation circuits 65 and 66 perform two-phase modulation on the 3 MHz carrier supplied from the carrier oscillator 64 and having a phase different by π / 2 based on the bit sequence input from the difference conversion circuit 63. Output. The combining circuit 67 takes the algebraic sum of both outputs of the balanced modulation circuits 65 and 66, and outputs it as a QDPSK output 68, that is, a PCM audio signal.

Reference numeral 12 denotes a band pass filter (BPF). The digital signal is subjected to analog phase modulation by the QDPSK modulation circuit 11, and the output PCM audio signal 68 is set to 3 MHz ± 665 KHz by the BPF 12, and VHS which is multiplexed in another signal band, particularly in the next stage.
-It is made not to affect the FM audio signal band of HiFi.

Reference numeral 13 denotes an FM audio circuit, which is a conventional VHS.
-Provided for compatibility with the HiFi method. The analog audio signal input to the input terminal 2 is supplied to the A / D converter 5 via the LPF 3 and
It is supplied to the M audio circuit 13. In the FM audio circuit 13, the input audio signal is 1.3M
Hz (L channel) and 1.7 MHz (R channel)
Are FM-modulated with a bandwidth of ± 150 KHz and output as FM-modulated signals. In addition, VHS-
Since the FM audio circuit 13 for HiFi is well known in the art, the circuit configuration and its detailed description are omitted.

Reference numeral 14 denotes a multiplexing circuit for audio signals. The multiplexing circuit 14 receives an 11-MHz AC bias signal output from an AC bias oscillator (not shown) from the QDPSK circuit 11 via the BPF 12 and outputs an S-VHS P-type signal.
CM audio signal and VHS input from FM audio circuit 13
The HiFi system FM audio signal is multiplexed and output as a multiplexed audio signal. As is well known, the AC bias signal is applied in accordance with the nonlinear characteristics of the electromagnetic conversion system in magnetic recording. The AC bias signal has a frequency three times or more the recording frequency, that is, 9 MHz (= 3 MHz ×
3) A higher frequency of 11 MHz.

Reference numeral 15 denotes a recording amplifier circuit, 16 denotes a two-head rotary head for recording audio, and 17 denotes a magnetic tape. The multiplexed audio signal output from the multiplexing circuit 14 is pre-emphasized for the high frequency component by the recording / amplifying circuit 15,
The current signal is supplied to the audio rotary head 16 and is recorded on the magnetic tape 17 in a deep layer. Next, a video signal is surface-recorded on the magnetic tape 17 by a video rotating head (not shown).

Next, the error correction code (ECC) adding circuit 7 in FIG. 4 will be described. As described above, the ECC adding circuit 7 corresponds to each subframe (FIG. 3). 648
Doubled Reed-Solomon codes C1 (31, 27, 5) and C2 (30, 24,
7) is calculated and added. Further, every time the addition of the C1 and C2 codes to each data block is completed, intra-block interleaving is performed.

In the recording format, generator polynomials Gp (x) and Gq for parity codes C1 and C2
(X) is defined as follows.

[0042]

(Equation 1)

FIG. 6 is a detailed block diagram of the ECC adding circuit 7.

The L and R channel digital audio signals supplied via the input selector 6 (FIG. 4)
Read / write memory (RAM) 71L, 71R or 7 via selectors S71L, S71R for each frame period
2L and 72R are written alternately.

The digital audio signal input during one TV frame period is 1620 samples (16 bits) for each channel, and each sample is composed of upper 8 bits (u) and lower 8 bits (u).
Written as two symbols of bit (l). That is, 6480 symbols for one TV frame are divided into blocks D0, D1,..., D9 in units of 648 symbols, and the RAMs 71L, 71R or 72L, 72
R stores five blocks of L and R channels, respectively.

Of the total of 10 blocks for both channels,
One block of L channel, ie, RAM 71L or 72
FIG. 7 shows the arrangement of 648 symbols for one block stored in L.

The ECC adding circuit 7 calculates the C2 parity (Q) of 162 symbols and the C1 parity (P) of 120 symbols for each of the five blocks of each of the L and R channels, and adds them as shown in FIG. Things. Since these calculations and additional processing are performed in common and in parallel for the L and R channels, the following description will be given of processing for one block of the L channel.

First, calculation and addition of the C2 parity are performed. In FIG. 6, for example, the selector S
24 symbols via 73L, for example, L000u, L0
001, L001u,..., L0111 (see FIG. 7)
Are sequentially read. Here, this reading is performed at six times the speed of writing. Each symbol (for example, L002
u) is converted by the data / α data conversion ROM 73L into an exponent of exponentiation and supplied to the adder 75L.

The C2 matrix coefficients of each of the six symbols for each symbol (L002u) are stored in the α coefficient ROM 74.
Are sequentially supplied to the adder 75L. Therefore, the α coefficient R
Reading of the C2 matrix coefficient from the OM 74 is performed at a speed six times as fast as reading each symbol (L002u), that is, 36 times as fast as writing.

The result of adding each of the six symbols to each symbol (L002u) is calculated by the adder 75L from the α coefficient /
The data is supplied to the data conversion ROM 76L and output to the exclusive OR (XOR) circuit 77L as a result of multiplication of 6 symbols. That is, the above-described data / α coefficient conversion ROM 73L,
α coefficient ROM 74L, α coefficient / data conversion ROM 76L
Is performed, for example, as follows. For example, for the data symbol “α ⁶⁴ ”, the data / α data conversion R
The OM 73L outputs “64”. α coefficient ROM74L
Outputs, for example, “3” for the C2 matrix coefficient “α ³ ”. The adder 75L adds "64" and "3" and outputs an addition result "67". α coefficient / data conversion ROM
76L converts the addition result “67” into a multiplication result “α ⁶⁷ ” and outputs the result to the XOR circuit 77L.

The XOR circuit 77L outputs a symbol corresponding to the result of the multiplication of the six symbols (in this example, the result of the multiplication of the symbol L002u by the six symbols) and the symbol corresponding to the result of the multiplication of the previous symbol (the symbol L001l in this example) by the six symbols. XOR with 6 symbols XO
The R result is output as C00 to C05.

The above operation is performed for 24 symbols L000.
, L0111 are sequentially repeated, and the finally obtained C00 to C05 are converted into C2 parities LQ000, LQ001,..., LQ0 of 6 symbols.
05 (see FIG. 7), and RA
Write to a predetermined area of M71L (see FIG. 7).

By repeating the above calculation and writing process for each of 27 sets (1 set = 24 symbols), the C of 162 (= 6 × 27) symbols for one block is obtained.
The addition of two parities is completed.

Next, calculation and addition of the C1 parity are performed.

For example, from the RAM 71L, the selector S7
27 symbols via 3L, for example, L000u, L01
, L312u (see FIG. 7) are sequentially read. .. Or L312u for each symbol L000u, L012u,.
L, α coefficient ROM 74, adder 75L, α coefficient / data conversion ROM 76L, and XOR circuit 77L calculate α
Except that the coefficient ROM 74 outputs C1 matrix coefficients of 6 symbols, the operation is exactly the same as that of the C2 parity. Such an operation is represented by 27 symbols L000u, L0.
12u,..., L312u are sequentially repeated, and the XOR results C00 to C05 of the six symbols finally obtained.
Of these, C00 to C03 are C1 parity LP000, LP1
As 00, LP200, and LP300 (see FIG. 7), data is written in a predetermined area of the RAM 71L via the selector S72L.

Here, the 4-symbol C1 parity C00-
To obtain C03, the XOR results C00 to C05 of six symbols are obtained as in the case of the C2 parity, and two symbols C0 are obtained.
4. The reason why C05 is discarded is that the circuit scale of the ECC adding circuit 7 can be significantly reduced by enabling calculation of C1 parity with a common circuit configuration and common timing (clock) with C2 parity.

The above calculation and write processing are performed for 30 sets (1 set = 27 symbols) including the C2 parity area.
By repeating each, 120 for one block
(= 4 × 30) The addition of the C1 parity of the symbol is completed.

The addition of the C1 and C2 parities is as follows.
Regarding the corresponding block stored in the RAM 71R,
As in the case of AM71L, the processing is performed simultaneously and in parallel.

The CCC and C1 for one block of 648 symbols for each channel by the ECC adding circuit 7 are described.
2 each time the addition of parity is completed,
Block, that is, 2 channels x 930 symbols (however,
930 = 648 + 162 + 120), the interleaving circuit 8 (see FIG. 4) performs inter-block interleaving processing. The intra-block interleave processing will be described later.

The above-described addition of C1 and C2 to each block of both channels and the interleave processing within the block are sequentially repeated for five blocks of each channel, thereby obtaining 3240 symbols for each TV frame stored in the RAMs 71L and 71R. Is completed, and in the next 1TV frame period, the RAM 7
Processing is performed on 3240 symbols of each channel for one TV frame stored in 2L and 72R.

FIG. 8A shows the above-described RAMs 71L and 71L.
The relationship between the read / write period of the digital audio signal of 1R or 72L and 72R and the addition of the C1 and C2 parity and the interleave period in the block for the five blocks in the read period is shown. FIG.
(B) shows the timing of adding the C1 and C2 parity and the interleaving in the block in the above-described block unit. FIG. 9 shows the above-described C1 and C2 parity calculation timing.

Next, the interleave circuit 8 in FIG. 4 will be described. FIG. 10 is a block diagram of the interleave circuit 8, and FIG. 11 is a timing chart over the ECC addition circuit 7 and the interleave circuit 8.

As described above, each time the addition of the C1 and C2 parities to one block of each of the L and R channels is completed by the ECC addition circuit 7, the RAM of the ECC addition circuit 7
The selectors S81E, S810, or S82E, S shown in FIG.
RAM 81E, 81O or 82E, 8 via 82O
Each block in 020 (930 symbols as shown in Fig. 7)
Is transferred and stored. That is, the symbols of each block of the L and R channels are selected by the selectors S81E and S810.
Alternatively, the symbols are classified into even-numbered symbols and odd-numbered symbols by S82E and S82O,
E, 82O show even / odd subframes E as shown in the figure.
00 to E04 and O00 to O04.

Therefore, at each time t0 to t3 shown in FIG. 11, each of the subframes E00 to E34 of 930 symbols stored in the RAM 81E or 81O or 82E or 82O,
The arrangement of O00 to O34 is as shown in FIG.

Next, the interleaving between blocks will be described. The inter-block interleaving means that the sub-frames E00, O00, E01,..., O34,.
Are interleaved in subframe units corresponding to the track pattern shown in FIG. That is, by transferring each sub-frame stored in the arrangement of FIG. 13 to the RAM 81 or 82 via the inter-block address conversion circuit 83, the auxiliary RAM 84 and the RA
A sub-frame arrangement corresponding to the track pattern is obtained on M85 or M86.

The track patterns shown in FIG. 2B, for example, output patterns E01, O00, E02, O01, E03, O02, E04, O03, E of ten subframes for one TV frame.
As is clear from 10, O04, the odd-numbered subframe O00-
Since O04 is output with a delay with respect to the even subframes E01 to E10, the even subframe E10 belonging to the next TV frame is mixed. Conventionally, such two TVs
In the interleaving of the subframes over the frames, that is, the interleaving between the blocks, the RAMs 85 and 86 are used to store the subframes of two TV frames.
A memory capacity for a total of 40 frames was required for each of 20 subframes.

Therefore, in the present invention, by providing the inter-block address conversion circuit 83 and the auxiliary RAM 84 for one subframe as shown in FIG. 10, the memory capacity for a total of 19 subframes, Has enabled interleaving between blocks with a memory capacity of less than half (19/40).

FIG. 15 shows an inter-block address conversion circuit 8.
3, the sub-frame E stored in the RAM 81, 82
00-E04, O00-O04, etc. are auxiliary RAM84, RAM8
FIG. 5 is a timing chart for explaining to which area 5, 86 the data is transferred, how it is read, and output in the order according to the track pattern shown in FIG.

First, the write cycle period t of the RAM 85
From 0 to t1, the 10 sub-frames E00, O00, E01, O01,..., E04, O04 stored in the RAM 81 are read out in this order. Inter-block address conversion circuit 8
3 controls the storage destination of each output sub-block as follows.

As shown in FIG. 15, the sub-frame E00 read from the RAM 81 is written to the auxiliary RAM 84 as the area 9 between the times t0 and t01. Time t01
During the period from to t02, the subframe O00 is written to the area 2 of the RAM 85. Thereafter, subframes O01, E02,..., O04 are written in the RAM 85 as shown in FIG.
At 1, the RAM 85 enters a read cycle.

Read cycle period t1 to t2 of RAM 85
At 1, the 1 stored in the RAM 85 and the auxiliary RAM 84
The 0 subframes are sequentially read out in the order of the area numbers, and output to the synchronization / subcode adding circuit 87 via the selector S83. The order of the output subframes follows the track pattern as shown.

On the other hand, read cycle period t of RAM 85
From 1 to t2, the RAM 86 and the auxiliary RAM 80 which are in a write cycle have 10 sub-frames E10 for one TV frame stored in the RAM 82,
O10, E11,..., O14 are written as shown, and at time t2, the RAM 86 enters a read cycle.

Read cycle period t2 to t3 of RAM 86
, The 10 subframes E11, O10, E12,..., E20, O14 are output to the synchronization / subcode adding circuit 87 via the selector S83 in the order conforming to the track pattern.

Here, the writing of the sub-frame to the auxiliary RAM 84, for example, the writing of the sub-frame E10 is performed in the period t1 to t01, and the reading is performed in the period t18 to t19. As shown in the figure, the next writing, that is, writing of the sub-frame E20 is performed in the period t2 to t21, so that no inconvenience occurs.

Next, the mirror-scared (M ² ) conversion circuit 9 in FIG. 4 will be described. FIG. 16 is a block diagram showing the M ² conversion circuit 9, and FIG. 17 is a block diagram showing its operation. Hereinafter, FIG. 16 will be described with reference to FIG.

In FIG. 16, the latch pulse SubF
D, BLAD, 3-bit subframe address Sub
F2, SubF1, SubF0, and a 5-bit block address Block Add4, Block Ad
d3, Block Add2, Block Add1,
Block Add0 is a signal generated by dividing the bit clock BCK by a counter (not shown).

In the register 91, 3-bit subframe addresses (0 to 4) SubF2, SubF1, SubF
0 is input, captured by the latch pulse SubFD, and output to the logical sum (OR) circuit 93. The register 92 has a 5-bit block address (0 to 29).
Block Add4 to Block Add0 are input, captured by the latch pulse BLAD, and output to the OR circuit 93. Therefore, the 8-bit output of the OR circuit 93 corresponds to the address subcode W1 of each block (each block composed of 35 symbols (280 bits) shown in FIG. 3) input from the interleave circuit 8.

The 8-bit outputs W10 to W17 and the two bits of the logic level "1" are supplied to the input A of the data selector 94 as initial values. An M-sequence generation circuit 9 including D flip-flops (DFF) D91 to D100
XOR of the output of DFF D97 and the output of DFF D100, and DFF D91 to D99
Output, that is, 10-bit data is supplied to the data selector 94.
Is supplied to the input B.

Therefore, if the data selector 94 is controlled so as to select the input A, an M ² data output corresponding to the initial value W 1 is output from the M sequence generation circuit 95. Also,
By controlling the data selector 94 to select the input B, M-sequence signal from the M-sequence generation circuit 95, i.e. the pseudo random number sequence is supplied to the XOR circuit 96 as M ² data output.

The control of the data selector 94 is as follows.
This is performed by the control signals SELA and SELB, and FIG.
As shown in, for the first data symbol D0 M ² conversion by the initial value W1 is, M ² conversion is performed by the M-sequence signal for the other 30 data symbols D1～D30. Here, M ² conversion output is the output of the interleave circuit 8 XOR circuit 96 which receives the signal and M ² data output to the input (FIG. 4).

The control signal SELA is generated by dividing the bit clock BCK by a counter C91, and the control signal SELB is generated by dividing the bit clock BCK by a counter C92. A signal I obtained by dividing the bit clock BCK by the counter C94 is
The output of the AND gate A92 using SHI1 as the gate signal is M during the period during which the data symbols D0 to D30 are input.
The bit clock BCK is supplied to the sequence generation circuit 95.
That is, of the 35 symbols in each block, the synchronization code S,
Subcode W1, W2, parity codes P are not converted M ^2, only the remaining 31 symbols D0~D30 is converted M ^2, are output from the XOR circuit 96. A signal IS obtained by dividing the bit clock BCK by the counter C93
HI4 is connected to DFFs D91 to D91 via AND gate A91.
D100 is provided to each reset terminal, and DFF is input during the input period of the synchronization symbol S which is the first symbol of each block.
D91 to D100 are initialized. This is to correctly set the initial values W10 to W17 in the M-sequence generation circuit 95 for each block.

The recording system of the PCM audio recording / reproducing apparatus according to the present invention has been described above. Next, a reproduction system of the apparatus will be described with reference to FIG.

[II] Reproduction System In FIG. 4, reference numeral 21 denotes a video tape on which PCM and FM audio signals are multiplexed or recorded, or a video tape on which FM audio signals are recorded. Numeral 22 denotes a reproducing rotary head for audio of ± 30 degrees azimuth,
May also be used. The reproduction head 22 is a video tape 2
1 converts the audio magnetic recording recorded in the deep layer into an electromagnetic wave and outputs it as a reproduction signal.

The reproducing head 22 outputs a PCM audio signal (3M
Hz carrier) and the conventional FMHiFi signal (1.3 MHz)
z and 1.7 MHz carrier), the head gap and the like are appropriately changed for PCM recording and reproduction.

Reference numeral 23 denotes a head amplifier, which has frequency characteristics corresponding to the band of the reproduced signal.

Reference numeral 24 denotes an equalizer (equalizer). The equalizer 24 is provided for suppressing intersymbol interference of a reproduction signal input from the head amplifier 23. The reproduction signal input from the head amplifier 23 is supplied to a PCM equalizer and an FMHiFi equalizer connected in parallel via a buffer amplifier (not shown). The PCM equalizer converts the PCM reproduction signal into an FM equalizer Is F
The equalizer 24 is configured to output an M reproduction signal. Alternatively, an FM equalizer having peaking constants of 1.3 MHz and 1.7 MHz and a PCM equalizer having a peaking constant of 3 MHz may be connected in series.

Reference numeral 25 denotes a band pass filter (BPF). The BPF 25 has an AC bias signal (11 MHz),
FMHiFi carrier (1.3MHz and 1.7MHz)
And the like, and outputs only the PCM reproduction signal among the reproduction signals input from the equalizer 24. The BPF 25 includes a Chebyshev filter having a band of 3 MHz ± 665 kHz, a passive filter, a Butterworth filter, or the like.

Reference numeral 26 denotes a QDPSK (4-phase differential phase keying) demodulation circuit, which is a QDPSK in the above-described recording system.
Contrary to the circuit 11, the phase demodulation of the PCM reproduction signal (analog signal) input from the BPF 25 is performed, and the serial 2
Output as a value signal (digital signal).

That is, the QDPSK demodulation circuit 26 operates at 3 MHz.
The PCM analog reproduced signal of z is sequentially demodulated into 2-bit (dibit) digital data by a balance circuit (not shown) and output as a serial binary sequence (hereinafter, referred to as serial data) at a transmission rate of 2.62 Mbps. The QDPSK demodulation circuit 26 is well-known in a BS (satellite broadcast) tuner or the like, and a description thereof will be omitted.

Reference numeral 27 denotes a PLL (phase locked loop) circuit. The PLL circuit 27 is a circuit that receives serial data from the QDPSK demodulation circuit 26 as input, and outputs a bit clock BCK (2.62 MHz) in phase with the serial data. Since the PLL circuit 27 is a well-known circuit configured to combine a phase comparator and a voltage-controlled oscillator and to obtain an output that is phase-synchronized with an input by using a negative feedback loop of an integral control type regarding frequency, The description is omitted.

Reference numeral 28 denotes a synchronization detection circuit. As is apparent from the above description, in the recording system of this embodiment, the 16-bit sample of the audio signal is made up of two data symbols (8 bits each), and these data symbols and parity symbols are converted into mirror-scared (M ² ) conversions. is M ² conversion by the circuit, is outputted as respective 8-bit serial-bit data. That is, the signal is output by the so-called 8-8 modulation method.

[0092] On the other hand, without being M ² conversion, sync code output from M ² conversion circuit 9 (4EH) Sync (hereinafter,
Similarly, the sub-codes W1 and W2 and the parity code Parity (hereinafter abbreviated as "P") are each 8-bit serial bit data.

Further, the pre / postamble adding circuit 10
Similarly, the preamble (4 blocks) and postamble (2 blocks) added in 8 bits are also 8 bits (90H).
Is a serial bit pattern.

Therefore, for synchronous reproduction in the reproduction system, the bit pattern (4E
There is a problem that even if H) is detected, the sync code S is not necessarily detected.

That is, of the bit patterns (4EH), those corresponding to the M ² -converted data symbols and parity symbols (hereinafter referred to as pseudo sync patterns) are excluded, and bit patterns (4EH) correctly corresponding to the sync code S are removed. ) Must be detected.

Therefore, the synchronization detection circuit 28 of this embodiment performs synchronization detection in two stages as follows. First, QDPS
Among the serial binary signals input at 2.62 Mbps from the K demodulation circuit 26, a postamble pattern and a preamble pattern (hereinafter, referred to as an amble pattern) added over six blocks before and after the inter-track boundary are
The detection is performed based on the head switching pulse SWP and the bit clock BCK, and an amble synchronization signal is generated.

Second, a sync pattern (4EH) of the serial binary signal is detected based on the amble synchronization signal and the bit clock BCK thus detected.
Generate a synchronization signal.

Thus, even under the above conditions,
The starting point of each block shown in FIG. 3, that is, the sync code S can be detected stably and reliably without erroneously recognizing the pseudo sync pattern indicating the same bit pattern (4EH) as the sync code S. .

Note that the synchronization detection circuit 28
This will be described later in detail.

Reference numeral 29 denotes a subcode (W1) decoding circuit. As shown in the “recording format” of FIG.
The block includes a sync code S and an address subcode (A
DR) W1, ID subcode (ID) W2, subcode parity P (4 or more symbols), 31 data symbols and parity symbols D0 to D30
Consists of

The sub-code (W1) decoding circuit 29 converts the serial binary signal input from the QDPSK demodulation circuit 26 into 8-bit serial / parallel signals based on the bit clock BCK and the synchronization signal supplied from the synchronization detection circuit 28. To obtain an address subcode W1, an ID subcode W2, and a subcode parity P.

Next, the presence or absence of an error in the address subcode W1 is checked using the ID subcode W2 and the subcode parity P. If no error is detected, the address subcode W1 is output as it is, or if an error is detected, after being corrected based on an appropriate judgment criterion, and output as an initial value for inverse Miller Scared (M ² ) conversion Is done.

The subcode (W1) decoding circuit 2
9 will be described later in detail.

Numeral 30 denotes an inverse mirror squared (inverted M ² ) conversion circuit. QDPSK serial binary signal SBD to be input from the demodulation circuit 26, inverse M ² conversion circuit 30 by block per 31 data symbols D0~D30 area (24
8 bits) and then output after inverse M ² conversion. Here, the sub-code W1 supplied from the sub-code decoder 29 is used as the initial value of the inverse transform, the data area signal is used to indicate a data area (248 bits) to be converted inverse M ^2. This inverse conversion is substantially the same as the above-described description of the M ² conversion circuit 9 in the recording system, and thus the description thereof is omitted.

Reference numeral 31 denotes a de-interleave circuit. In the de-interleave circuit 31, the inverse M ² conversion circuit 3
The serial binary signal SBD input from 0 is sequentially decoded into 8-bit symbols, stored in the RAM in units of 9300 symbols (= 10 subframes × 30 blocks × 31 symbols) for one TV frame, and at the same time, in subframe units. Is performed, and then intra-block de-interleaving is performed. The inter-block and intra-block de-interleaving described above is an inverse process performed to restore the inter-block and intra-block interleaving in the interleaving circuit 8 described above in the recording system. The deinterleaved symbols are output in units of subframes (930 symbols) E00, O00, E01,.
An error correction / correction process in the next stage is performed.

The de-interleave circuit 31 will be described later in detail.

Reference numeral 32 denotes an error correction / correction (ECC) circuit. Each of the sub-frames E00, O00, E01, O01,... Sequentially input from the de-interleave circuit 31 is composed of a total of 930 symbols of 648 data symbols and 282 parity symbols (see FIG. 7). E
CC circuit 32 stores the sub-frame as one block in RAM (not shown), 648 data symbols for alpha ⁿ coefficient ROM, a detection of an error by using a ROM for error position (both not shown) Do.

When a data symbol in which an error has been detected is correctable, correction is performed. When correction is not possible, a so-called erasure correction is performed, for example, by setting a flag on the symbol to indicate an error. That is, the syndrome of the C1 sequence is calculated and the presence or absence of an error is determined. If the error is "present", the error is corrected if it is within the range of the error correction capability, and if it is outside the range of the error correction capability, the erasure flag is set.

Next, the syndrome of the C2 series is calculated,
Correct the data symbol with the erasure flag set. Here, when the error correction capability of C2 is exceeded, correction processing by, for example, average value interpolation or previous value interpolation is performed in order to suppress the occurrence of abnormal noise in the reproduced sound.

Each data symbol thus subjected to error correction / correction is supplied as a digital audio signal to a digital input terminal of a digital audio tape recorder (DAT) via a digital output terminal 39, for example.

33 is a digital / analog (D / A) converter, 34 is a low-pass filter (LPF), and 38 is an output selector. The data symbols sequentially input from the ECC circuit 32 include upper (u) and lower (l) symbols.
One symbol is set as one set to form 16-bit digital data, and the D / A converter 33 uses the bit clock BCK or the like from the timing generation circuit 4 to perform S-VH
It is converted to an analog audio signal of the SPCM system. This PCM analog audio signal is supplied to the output selector 38 via the LPF 34 that suppresses unnecessary components such as the sampling frequency fs.

Reference numeral 35 denotes a low-pass filter (LPF) for extracting FM carriers (1.3 and 1.7 MHz) in the conventional S-VSHSFMFi system from the multiplexed reproduction signal output from the equalizer 24. The following Butterworth filter is used. Also, 3
Reference numeral 6 denotes an FM audio demodulation circuit that demodulates an FM signal input via the LPF 35 and outputs an analog audio signal of the S-VHS FM method to the output selector 38. The above, LP
Since the F35 and the FM audio demodulation circuit 36 are both well-known conventional technologies, detailed description will be omitted.

Reference numeral 37 denotes an FM / PCM detection circuit which controls the output selector 38 in accordance with whether the deep recording of the audio signal on the video tape 21 is a multiplexing system of PCM and FM or a conventional FM system.

FIG. 18 is a block diagram showing an example of the FM / PCM detection circuit 37. Equalizer 24 shown in FIG.
Is input to the BPF 102 having a center frequency of 3 MHz via the buffer amplifier 101. PCM playback signal component of the playback signal (carrier 3MHz)
Is extracted by the BPF 102 and the frequency / voltage (f
/ V) f / V converted by the conversion circuit 104 and output as a voltage signal. This output voltage is supplied to the voltage comparator 105
Is compared with the reference voltage to determine the presence or absence of a PCM reproduction signal. This comparison output is output as a selector control signal to the output selector 38 (FIG. 4) via the integration circuit 106.

The output selector 38 has a PC
Both analog audio signals of M and FM are input, and one of them is selected and output to the analog output terminal 40. This selection is arbitrarily made in the manual mode, and is made by a selector control signal from the FM / PCM detection circuit 37 in the automatic mode.

Next, the synchronization detecting circuit 28 will be described. FIG. 19 is a block diagram showing an example of the synchronization detection circuit 28, and FIG. 20 is a waveform diagram showing its operation timing.

The serial / parallel (S / P) converter 111 converts a serial binary signal (hereinafter referred to as serial data) SBD input from the QDPSK demodulation circuit 26 into
Serial / parallel conversion is performed in synchronization with the bit clock BCK supplied from the PLL circuit 5, and 8-bit parallel data is output to the comparators 112 and 122.

The comparator 112 sets 8 as the reference value.
Since the bit amble pattern “90H” is given, the bit pattern “90H” is added to the serial data SBD.
Each time “H” appears, the comparator 112 outputs the amble pattern match signal AC to the NAND (NAND) gate 11.
Output to 3. This bit pattern “90H” appears as an amble pattern in an area of a preamble of four blocks and a postamble of two blocks added before and after each track data, and also has a mirror-scared (M ² ).
As described above, the converted PCM data and parity area can also exist as a pseudo amble pattern.

On the other hand, since the sync code pattern “4EH” of 8 bits is given to the comparator 122 as a reference value, every time the bit pattern “4EH” appears in the serial data SBD, the comparator 122 outputs the sync pattern coincidence signal. SC is output to the NAND gate 123. This bit pattern “4EH” may be present as a pseudo sync pattern in the PCM data and parity areas in addition to appearing as a sync pattern added to the head of each block. That is, the sync pattern coincidence signal SC cannot be used as it is as the sync signal SS which determines the success or failure of the PCM decoding process. FIG. 20 shows the above state.

Therefore, in the present invention, first, NAN
By giving the amble area signal AA as a gate signal to the D gate 113 and removing the amble pattern match signal AC based on the pseudo amble pattern, the NA
The ND gate 113 outputs a stable amble synchronization signal AS.

Next, the sync mask signal SM generated based on the amble synchronization signal AS is supplied to the NAND gate 123 as a gate signal to remove the sync pattern coincidence signal SC based on the above-mentioned pseudo sync pattern. 123 supplies a stable synchronizing signal SS to the sub-code decoding circuit 29 of the next stage.

The above amble area signal AA is generated as follows.

Delay circuit 11 composed of D flip-flop
4 indicates that the input 30 Hz head switching signal SWP is d
The output is output to the exclusive-OR (NXOR) gate 115 of the negative logic output with a delay of (≧ 2) bit clock periods. NX
Since the head switching signal SWP is directly supplied to the OR gate 115, the NXOR gate 115 outputs the reset signal R synchronized with the bit clock BCK and the head switching signal.
Is output to the frequency dividing circuit 116 and the D flip-flop 117. Here, the pulse width of the reset signal R is the d-bit clock BCK (see FIG. 20).

The frequency dividing circuit 116 reset by the reset signal R divides the bit clock BCK by n (where 7 ≦
n ≦ 1120−d), and outputs the result to the D flip-flop 117 as the amble mask signal AM. Reset signal R
The D flip-flop 117 resets the logic level “1”, uses the amble mask signal AM as a clock, and changes the amble area signal AA and bar AA to NA.
The signal is output to the ND gate 113 and the subcode decoding circuit 29 in the next stage.

The NAND gate 113 removes the match signal AC corresponding to the pseudo amble pattern from the amble pattern match signal AC using the amble area signal AA as a gate signal, and converts the amble synchronization signal AS into a frequency dividing circuit 126.
(See FIG. 20). Here, the comparator 11
The 2-D flip-flop 117 forms the amble pattern detection circuit 110.

The frequency dividing circuit 126 reset by the amble synchronization signal AS includes AND gates 124a, b, c, D flip-flops 125a, b, c, d, and a frequency divider 127.
a, 280 frequency divider 127b, inverter 128a,
b, and an OR gate 129. After the detection of the amble pattern, the bit clock is frequency-divided by 8 until the first sync pattern of the track is detected.
It is made to divide by 80. Here, the 280 frequency division is based on the fact that each data block (35 symbols) is composed of 280 bits. The operation of the frequency dividing circuit 126 is as follows.
FIG. 20 shows a waveform, which is well known in the prior art.
Detailed description is omitted. In this way, the frequency divider 126 outputs the sync mask signal SM to the NAND gate 123.

The NAND gate 123 uses the sync mask signal SM as a gate signal and a sync pattern coincidence signal SC.
Of the coincidence signal SC corresponding to the pseudo sync pattern, the synchronization signal SS is output to the sub-code decoding circuit 29 of the next stage.
Output to Here, the comparator 122 to the frequency dividing circuit 1
26 constitutes the sync pattern detection circuit 120.

FIG. 20 shows a waveform at a delay time d = 2BCK, where the division ratio n = 7 is indicated by a dotted line, and n = 1.
The case of 118 (= 1120-d) is shown by a solid line.

As described above, first, the amble pattern detection circuit generates the amble synchronization signal AS from which the pseudo amble pattern has been removed, and then the sync pattern detection circuit removes the pseudo sync pattern based on the amble synchronization signal AS. Thus, the synchronization signal SS that affects the success or failure of decoding can be made stable and reliable.

Next, the subcode (W1) decoding circuit 29 will be described. As is clear from the data structure of the track shown in FIG. 3, a serial binary signal SBD obtained by demodulating a reproduction signal for one track (１ ／ TV frame) is obtained.
Is composed of a preamble area of 4 blocks (= 1120 bits), a data area of 5 subframes (= 150 blocks), and a postamble area of 2 blocks (= 560 bits). Here, each block in the data area is a QDPSK demodulation circuit 2 as a 280-bit serial binary signal SBD corresponding to 35 8-bit symbols.
6, respectively.

Since the position of the leading symbol of each block, that is, the position of the sync symbol S in the serial binary signal SBD is known by the synchronization signal SS, the synchronization detection circuit 28 described above uses the address subcode W1, ID subcode W2, parity code P, D0 symbol, D1 symbol,..., D30 symbol are serial 2 bits for each 8-bit clock BCK after the synchronization signal SS.
Decoding is performed by serial / parallel conversion of the value signal SBD and latching.

Of the decoded sub-codes W1, W2, P, the address sub-code W1 is the upper 3 bits (binary (000) _2- (10
0) ₂ ) and the lower 5 bits (0
0000) ₂ to (11101) ₂ , and is used as an initial value of the inverse M ² conversion in the inverse mirror squared (M ² ) conversion circuit 30.

That is, the success or failure of the inverse M ² conversion depends on the reliability of the initial value. Therefore, in the subcode (W1) decoding circuit 29 according to the present invention, the decoded address subcode W1 Decrypted ID subcode W
The presence / absence of an error is checked using 2 and the parity code P. If an error is detected, the following correction is performed, and the correction is supplied to the inverse M ² conversion circuit 30 in the next stage as an initial value. .

FIG. 21 is a flowchart showing a procedure for decoding, error detection and correction of the address subcode W1.

First, based on the bit clock BCK from the PLL circuit 27 and the synchronizing signal SS from the synchronizing signal detecting circuit 28, the sub code W is converted from the serial binary signal SBD.
1, W2, and P are decoded and latched (steps ST1 to ST1).
ST3).

Next, a parity check of the subcode is performed. That is, it checks whether the inverted output of the exclusive OR of the 8-bit subcodes W1 and W2 and the exclusive OR of the subcode P are equal to zero (step ST4). If the result is equal to zero (YES), it is determined that there is no error in the subcode W1, and the result is output as it is to the inverse M ² conversion circuit 30 as an initial value (step ST9).

If there is any error in subcodes W1, W2, P, that is, if the check result of step ST4 is "N
In the case of "O", after detecting the amble pattern, it is determined whether or not the first subcode is W1 based on the negative logic amble area signal AA from the synchronization detection circuit 28. "YE
S ", that is, the subcode W1 in the first block in the data area of the track, the subcode W1
Of the subcode W1 must be corrected to zero (step ST1).
1) Output (step ST9).

After detecting the amble pattern, if it is not the first subcode W1 (NO), it is checked whether the least significant bit (LSB) of the subcode W1 is "1" (step ST6). If “NO” (LSB = 0), the sub-code W1 (−1) of the previous block is incremented to be the current sub-code W1 (step ST10) and output (step ST9).

"YES" (LSB of subcode W1 =
In the case of 1), it is checked whether or not the subcode W2 is zero (step ST7). The subcode W2 is an optional subcode, and is set to zero in this embodiment. Therefore, if "NO" (W2 （0), it is determined that there is an error in the subcode W2, and the subcode W1 is left as it is. Output (step ST9).

If "YES" (W2 = 0), it is determined that there is an error in subcode W1, and subcode W2 and bar P
Is taken as the sub-code W1 (step ST8) and output (step ST9).

[0141] Thus, the sub-code decoder 29 is adapted to latch and decode the subcode W1, W2, P, and outputs the detect and correct errors in subcode W1 to the next stage of the inverse M ² conversion circuit 30 It is configured as follows.

FIG. 22 is a block diagram showing an example of the subcode decoding circuit 29.

[0143] 131 is the serial binary signal SBD to 8
This is a serial / parallel converter for converting into bit subcodes W1, W2, P.

132 is a latch pulse generation circuit.
The synchronization signal SS from the synchronization detection circuit 28 and the amble area signal AA are input, and latch pulses for latching the subcodes W1, W2 and P output from the serial / parallel converter 131 and data D0 to D30 are latched. To output a data latch signal and a first W1 area signal. FIG. 23 shows a waveform diagram of input / output signals of the latch pulse generation circuit 132.

The address subcode W1 output from the serial / parallel converter 131 is converted into an 8-bit D by the W1 latch pulse from the latch pulse generation circuit 132.
-Latch (hereinafter referred to as octal D-latch) 133, and the previous address subcode W1 (-1) output from octal D-latch 133 is also supplied to octal D-latch 136 by the W1 latch pulse. Latched by the adder 137, the sub-code W1 (−
"1" is added to the lower 5 bits of 1), and the subcode W
It is output as 1 (-1) +1. The ID subcode W2 is an octal D-latch 1 by a W2 latch pulse.
At 34, the parity subcode P is latched by the octal D-latch 135 by a parity (P) latch pulse.

The above processing corresponds to steps ST1 to ST3 in the flowchart shown in FIG. The timing of each latch pulse is as shown in FIG.

The address sub-code W1 output from the octal D-latch 133 and the ID sub-code W2 output from the octal D-latch 134 are XORed by an exclusive OR (XOR) circuit 138, and passed through an inverter 139. Input to the XOR circuit 140. Since the subcode P output from the octal D-latch 135 is given as an input to the XOR circuit 140, the XOR circuit 140
An XOR result of the two input data, that is, a parity check result is output to the magnitude comparator 145. The magnitude comparator 145 compares the parity check result given as the input A with the input B (= 0).

The above processing corresponds to step ST4 in FIG.
Is equivalent to

If the parity check result is equal to zero,
That is, when there is no error in the subcodes W1, W2, and P,
Since the magnitude comparator 145 outputs the coincidence signal A = B as a gate signal to the AND (AND) circuit 152, the subcode W1 output from the octal D-latch 133 includes the AND circuit 152 and the OR (OR) circuit 156.
Is output as is. This is because the parity check in step ST4 is "YES" in FIG.
Corresponds to the case of

The AND circuit 144 using the first W1 area signal as a gate signal resets the lower 5 bits of the subcode W1 to zero in the first block and resets the subcode FW.
The sub code W1 is output to the magnitude comparator 146 as the sub code FW1 as it is in the second block and thereafter.

The magnitude comparator 146 inputs the lower 5 bits of the subcode FW1 (input A) to the input B (=
0), the match signal A = B is output to the AND circuit 153 as a gate signal when the lower 5 bits are equal to zero. The AND circuit 153 includes a non-coincidence signal A ≠ B of the magnitude comparator 145 as other gate signals,
The first W1 area signal is supplied. Therefore, the parity check result is not zero (that is, the subcode W1,
When an error is detected in W2 and P, the magnitude comparator 145 outputs the mismatch signal A ≠ B) and the subcode of the first block (ie, the lower 5 bits of the subcode FW1 are equal to zero, and the magnitude comparator 14
6 is the coincidence signal A = B), the AND circuit 153 outputs the lower 5
The sub-code FW1 whose bit has been reset to zero is output as a corrected sub-code W1 via the OR circuit 156. Here, the subcode FW1 is output from the AND circuit 144 to the coincidence output A =
Through an AND circuit 151 using B as a gate signal,
It is supplied to the D circuit 153. This corresponds to steps ST5, ST11 and ST9 in the flowchart of FIG.
Corresponds to the processing of

The magnitude comparator 147 has a sub-code W1 input from the octal D-latch 133.
The least significant bit (LSB) of (input A) is compared, and when the least significant bit is equal to zero, match signal A = B is output to AND circuit 154 as a gate signal. When the least significant bit is equal to “1”, the non-coincidence signal A ≠ B is output to the AND circuit 155.

The magnitude comparator 148 has a sub code W2 input from the octal D-latch 134.
(Input A) are compared, and when the subcode W2 is equal to zero, the coincidence signal A = B is output to the AND circuits 154 and 155 as gate signals.

The AND circuit 154 is supplied with three gate signals other than the above two. That is, first, the first W1 area signal is supplied to the second
In addition, the coincidence signal A =
Thirdly, B receives the mismatch signal AB of the magnitude comparator 146 as a gate signal via the inverter 149.

Therefore, when all five gate signals are logic "1", that is, "parity check result $ 0"
In "subcode W1 @ first W1", "lower 5 bits of subcode FW1 @ 0" and "subcode W2 =
0 ”and“ LSB of the subcode W1 = 0 ”, the AND circuit 154 outputs the output W1 of the adder 137.
(-1) +1 (sub code W1 in the immediately preceding block
OR the value obtained by adding "1" to the lower 5 bits of (-1)
The corrected sub-code W1 is output via the circuit 156. This corresponds to the processing of steps ST6, ST10, ST9 in the flowchart of FIG.

The AND circuit 155 receives four gate signals. That is, first, the coincidence signal A = B of the magnitude comparator 145 passes through the inverter 149, and secondly, the first W1 area signal passes through the inverter 1
Third, the magnitude comparator 1
Fourth, the non-coincidence signal A ≠ B of 47 and the coincidence signal A = B of the magnitude comparator 148 are provided as gate signals.

Therefore, when all four gate signals are logic "1", that is, "parity check result $ 0"
Then, “subcode W1 ≠ first W1”, “LSB of subcode W1 ≠ 0”, and “subcode W2 = 0”
In this case, the AND circuit 155 outputs the output of the XOR circuit 143 via the OR circuit 156 as the corrected sub-code W1. Here, since the subcode W2 is input from the octal D-latch 134 to the XOR circuit 143 and the subcode P is input from the octal D-latch 135 via the inverter 142, the XOR circuit 1
The output of 43 indicates a subcode W1 calculated from the subcode W2 and the parity code P when there is no error in the subcodes W2 and P. This corresponds to the processing of steps ST7 to ST9 in the flowchart of FIG.

As described above, in the subcode (W1) decoding circuit 29 of the present invention, the synchronization detecting circuit 28
From sub-codes W1, W2 and P based on serial binary signal SBD based on stable and
Is decoded, and error detection and correction of the subcode W1 is performed in real time by a predetermined algorithm, and is output as an initial value to the next-stage inverse-mirror-scared (M ² ) conversion circuit 31, so that highly reliable decoding is performed. Becomes possible.

Next, the de-interleave circuit 31 will be described.

As described above, in the recording system, PCM
The symbols and their parity symbols (hereinafter referred to as data symbols) are magnetically recorded after being subjected to interleaving within and between blocks in accordance with the “recording format”. Therefore, in a reproducing system, these are decoded from the reproduced signal. A process of returning interleaving between blocks of symbols and within a block (de-interleaving) is required. The de-interleave circuit 31 has the inverse M
Data symbols are decoded from the serial binary signal SBD after the ² conversion, and data
Perform interleaving.

FIG. 24 is a block diagram showing an example of a de-interleave circuit 31 in the PCM audio recording / reproducing apparatus according to the present invention, and FIG. 25 is a timing chart showing the relationship between an input signal and each control signal in the circuit 31. .

A serial / parallel (S / P) converter 161 converts the serial binary signal SBD after inverse M ² conversion input from the inverse M ² conversion circuit 30 into 8-bit parallel data in synchronization with the bit clock BCK. , Octal D-
Output to latch 162. In the upper part of FIG. 25, the input serial binary signal SBD is converted into sub-frames E01, O00, E0.
Shown in units of 2, O01, ... The relationship between the bit configuration of the serial binary signal SBD for one subframe and the data latch pulse supplied from the subcode (W1) decoding circuit 29 is shown in an enlarged manner.

The octal D-latch 162 receives the input 8
The bit data is latched by a data latch pulse and sequentially output as data symbols D0 to D30, which are stored in the RAMs 181 and 182 as the first and second memories or the auxiliary RAM 185 as the third memory.

RAMs 181 and 182 and auxiliary RAM 1
The read / write (R / W) control of R / W 85 is controlled by 15H supplied from the timing generation circuit 4 constituting the address conversion means.
This is performed by a write control (WE) pulse of z, a read control (R) pulse for the auxiliary RAM, and a WE pulse. These control pulses are shown in the lower part of FIG. Fifteen
The Hz WE pulse is supplied to the RAM 18 via the inverter 167.
2, the RAM 181 and the RAM 182 store 1
The writing state and the reading state are alternately controlled for each TV frame. As shown in FIG. 25, the auxiliary RAM 185 stores time periods t01 to t02, t11 to t12, t21 to t22,.
In the writing state in the period t09 to t1, t19
To t2 and t29 to t3, and the RAM is read out.
181 and the RAM 182 operate as a common auxiliary RAM. The address conversion means is a W address conversion ROM 1
65, R address counter, address selector 171,
172 and 175.

Read (R) address counter 166
Outputs a read address based on a read clock supplied from the timing generation circuit 4, and the write (W) address conversion ROM 165 converts the read address to a write address and outputs the converted address. The write address and the read address are stored in the address selector 17.
1, 172, 175 to the RAMs 181 and 182 and the auxiliary RAM 185 to define a memory address where the decoded data symbols D0 to D30 are to be stored, that is, a memory address for de-interleaving between blocks. RAMs 181 and 182 and an auxiliary RAM 185 for deinterleaving in a block.
Stipulates a memory address in reading each data symbol stored in. Here, the address selector 17
In 1,172,175, the write / read address is switched by a 15 Hz WE pulse or an inverted WE pulse via an inverter 167.

FIG. 26 is a timing chart showing the above-described write and read control. The serial binary signal SBD corresponding to the subframe E01 input during the period t0 to t01 is decoded into 930 (= 30 blocks × 31 data symbols) data symbols,
It is stored at address 1 of AM 181. Period t01-t02
Sub-frame O00 is the auxiliary RAM 1 at address 10.
85 is written. During the period t02 to t1, the subframes E02, O01, E03, O02, E04, O03, E10, and O04 are sequentially written to the addresses shown in the RAM 181.

At time t1, RAM 181 is set to the read state, and RAM 182 is set to the write state.

In the period t1 to t2, the subframe E11 is stored at the address 1 of the RAM 182 in the auxiliary RAM 185.
The subframe O10 is stored at the address 10 of the RAM 182.
Addresses 2 to 9 have subframes O11, E12, O12,
E13, O13, E14, O14, and E20 are stored, respectively.

In this period t1 to t2 during which writing to RAM 182 is performed, RAM 181 and auxiliary RAM 1
85, the subframes E01, O01, E02, O02,..., E04, O04, E1 in the order of address numbers 1 to 10.
0 and O10 are sequentially read out, and a logical sum (OR) circuit 191
Are sequentially output for intra-block de-interleaving.

By the writing / reading control and address control of the auxiliary RAM 185 common to the RAMs 181 and 182 as described above, the 20 subframes decoded during the 2TV frame period from the period t0 to t2, that is, the interleaving between blocks is performed. 20 subframes E01, O
.., E14, O13, E20, and O14, 1 TV frame subjected to inter-block deinterleaving in the period t1 to t2, and 10 subframes E0
1, O01, E02, O02,..., E10, O10 are sequentially output.

Similarly, sub-frames E11, O11,..., E20, O20 deinterleaved between blocks in the periods t2 to t3 are sequentially output from the input signals in the periods t1 to t3.

Conventionally, as described above, de-interleaving in units of sub-frames (inter-block de-interleaving) spanning between two TV frames has a RAM of 2 TV frames × 2 banks, that is, a RAM having a capacity of 40 sub-frames. And the deinterleaving process between the blocks is performed with a delay of 2 TV frame periods.

On the other hand, in the de-interleave circuit 30 according to the present invention, the RAM 18 for nine sub-frames is used.
1 and 182 and an auxiliary RAM 185 for one subframe shared by the RAMs 181 and 182, a RAM having a capacity of a total of 19 subframes, by simply writing and reading data symbols in subframe units, deinterleaving between blocks. Processing completes quickly.

That is, according to the present invention, the data
The memory capacity required for interleaving can be reduced to 19/40, and accordingly, the processing time can be increased from a delay of 2 TV frame periods to a delay within 1 TV frame period.

The read address supplied from the read (R) address counter 166 determines the RAM 181
Each data symbol sequentially read and output from the 182 and the auxiliary RAM 185 is output to the data distributor 192 via the OR circuit 191. The data distributor 192 supplies, for example, the data symbols output from the RAM 181 and the auxiliary RAM 185 to the RAM 201 during the period t1 to t2, and the data symbols output from the RAM 182 and the auxiliary RAM 185 to the RAM 202 during the period t2 to t3.

The intra-block deinterleaving process, that is, the process of returning from a pair of odd / even subframes to the left (L) channel and right (R) channel subframes is performed in the RAM 2.
01 and 202 are performed.

The read address output from the read (R) address counter is the write address conversion ROM 1
93, the address is converted into a write address for de-interleaving in the block,
A write address of the RAM 201 or 202 is controlled via 196. FIG. 27 shows the state of the L / R channel subframe stored in RAM 201 as a result of the intra-block deinterleaving controlled in this way.

FIG. 27 shows that R is set during the period t1 to t2 shown in FIG.
, E10, and O10 sequentially output from the AM 181 and the auxiliary RAM 185 are input to the RAM 201 via the data distributor 192, and are written in the block by the write address given through the address selector 195.・ Interleaved RAM2
FIG. 11 is an explanatory diagram showing a state stored in the storage unit 01. For example, the subframes E01 and O01 of 930 symbols read from the RAM 181 in the periods t1 to t12, respectively.
During the same period t1 to t12, the intra-block deinterleave processing is performed, and 930 symbols of L channel blocks L01 and R
It is stored as a channel block R01. The arrangement of each symbol in the block is as shown in FIG.

In FIG. 24, the read addresses input to the address selectors 195 and 196 are supplied from the read (R) address counter 205 and stored in the RAM 201 or 202 for error detection / correction processing in the next stage. This is an address control signal for reading the data symbols of the L / R channels in block units. However, RAM 201, 202 and read (R)
The address counter 205 forms a part of the error detection / correction circuit 32 at the next stage.

As described above, the embodiment of the PCM audio recording / reproducing apparatus according to the present invention has been described for the 48k-mode of the S-VHS system. However, the present invention is not limited to this and other than the S-VHS system. For example, a PCM audio recording / reproducing apparatus for a video tape recorder of an 8 mm video system, other than the 48k-mode, for example, a 32k-mode, for example, a PAL system other than the NTSC system, or a single PCM signal recording / reproducing apparatus. Clearly applicable.

[0181]

As described above, according to the deinterleave circuit of the PCM audio recording / reproducing apparatus according to the present invention, since the auxiliary RAM shared by each TV frame is provided, the RAM capacity for deinterleave is provided. Can be reduced to less than half as compared with the related art.

The write address conversion ROM performs de-interleaving between blocks simultaneously with writing of data symbols to the RAM, and further performs de-interleaving within blocks simultaneously with reading and transferring of data symbols from the RAM. Therefore, the TV frame delay for de-interleaving can be one TV frame period which is less than half of the conventional one.

[Brief description of the drawings]

FIG. 1 is a diagram showing the specifications of a PCM audio recording format of S-VHS.

FIG. 2 is a diagram showing a track pattern in an S-VHS PCM audio recording format.

FIG. 3 is a diagram showing a data configuration in the same format.

FIG. 4 is a block diagram showing one embodiment of the present invention.

FIG. 5 shows four-phase differential phase modulation (QDPSK) in FIG.
It is a block diagram showing a circuit.

FIG. 6 is a block diagram showing an error correction code (ECC) adding circuit in FIG. 4;

FIG. 7 is a diagram showing a symbol arrangement of each block in the same format.

FIG. 8 is a timing chart of ECC addition and intra-block interleaving.

FIG. 9 is a timing chart of an ECC calculation.

FIG. 10 is a block diagram showing an interleave circuit in FIG. 4;

FIG. 11 is a timing chart of ECC addition and interleaving.

FIG. 12 is a diagram illustrating a subframe configuration in an ECC addition and interleave format.

FIG. 13 is a subframe arrangement diagram for each television frame.

FIG. 14 is a timing chart of interleaving between blocks.

FIG. 15 is a detailed timing chart of interleaving between blocks.

FIG. 16 is a block diagram showing a mirror-scared (M ² ) conversion circuit in FIG. 4;

FIG. 17 is a timing chart of the Miller Scared (M ² ) conversion circuit in FIG. 4;

18 is a block diagram illustrating an example of an FM / PCM detection circuit 37 in FIG.

19 is a block diagram illustrating an example of a synchronization detection circuit 28 in FIG.

20 is a timing chart of the synchronization detection circuit 28 in FIG.

FIG. 21 is a flowchart of error detection and correction of an address subcode in the subcode decoding circuit 29 shown in FIG.

FIG. 22 is a block diagram illustrating an example of a subcode decoding circuit 29 in FIG.

23 is a timing chart of a latch pulse generation circuit 132 in the subcode decoding circuit 29 in FIG.

24 is a block diagram illustrating an example of a de-interleave circuit 31 in FIG.

FIG. 25 is a timing chart of the de-interleave circuit 31 in FIG. 4;

FIG. 26 is a timing chart of deinterleaving between blocks of the deinterleaving circuit 31 in FIG. 4;

FIG. 27 is an explanatory diagram showing de-interleaving in a block of the de-interleaving circuit 31 in FIG. 4;

[Explanation of symbols]

7 Error Correction Code (ECC) Addition Circuit 8 Interleave Circuit 9 Miller Scared (M ² ) Conversion Circuit 10 Pre / Postamble Addition Circuit 11 4-Phase Differential Phase Modulation (QDPSK) Circuit 13 FM Audio Circuit 14 Multiplexing Circuit 62 Serial / Parallel Conversion Circuit 63 Difference conversion circuit 64 Carrier oscillator 65, 66 Balanced modulation circuit 67 Synthesis circuit S71L, S71R, S72L, S72R, S73L,
S73R Selector 71L, 71R, 72L, 72R RAM 73L, 73R Data / α data conversion ROM 74 α coefficient ROM 75L, 75R Adder 76L, 76R α coefficient / data conversion ROM 77L, 77R Exclusive OR (XOR) circuit S81O, S81E, S82O, S82E, S83 Selectors 81, 81O, 81E, 82, 82O, 82E, 85,
86 RAM 83 Inter-block address conversion circuit 84 Auxiliary RAM 87 Synchronization / subcode addition circuit A91, A92 AND gate C91-C94 Counter D91-D100 D flip-flop 91, 92 Register 93 OR circuit 94 Data selector 95 M-sequence generation circuit 96 Exclusive Logical OR (XOR) gate 110 amble pattern detection circuit 111 serial / parallel converter 112, 122 comparator 113, 123 NAND (NAND) gate 114 delay circuit 115 exclusive OR (NXOR) gate of negative logic output 116, 126, 127a , 127b frequency divider 117, 125a-125d D flip-flop 120 sync pattern detection circuit 124a, 124b AND gate 128a, 128b inverter 1 29 OR gate 131 Serial / parallel converter 132 Latch pulse generation circuit 133-136 Octal D-latch 137 Adder 138,140,143 Exclusive OR (XOR) circuit 139,142 Inverter circuit 144,152-155 AND (AND) circuit 145 to 148 Magnitude comparator 149, 150 Inverter 151 AND (AND) gate 156 OR (OR) circuit 161 Serial / parallel converter 162 Octal D-latch 165, 193 Write address conversion ROM 166, 205 Read address counter 171, 172, 175, 195, 196 Address selector 181, 182, 201, 202 RAM 185 Auxiliary RAM 191 OR (OR) circuit 192 Data distribution

Claims (2)

(57) [Claims] 1. A PCM audio recording / reproducing apparatus for magnetically recording and reproducing an audio signal by a PCM method, wherein a predetermined number of subframe-unit signals are generated from a digital audio signal of one TV frame, and error detection and correction are performed. Therefore, a deinterleaving means for deinterleaving a signal in which one subframe unit less than one TV frame is interleaved in a frame and deinterleaving a signal in which one subframe unit is interleaved between frames is provided. Wherein the de-interleaving means comprises: first and second memories for storing a signal of a subframe unit less than one TV frame, and a third memory for storing a signal of one subframe unit. And address conversion means for controlling the signal writing / reading processing for the first to third memories. In the address conversion means, a signal in a subframe unit to be deinterleaved in the frame is stored in the first or the second one, and the stored signal is read out from the other memory to write and read the signal. By controlling the position and timing, a de-interleave process within a frame is performed, and a signal for each sub-frame for performing de-interleave between the frames is written to the third memory, and is also stored in the third memory. A PCM audio recording / reproducing apparatus, which performs deinterleaving processing between frames by controlling read timing of a written signal. 2. The address processing means controls signal write / read processing for the first to third memories,
2. The PC according to claim 1, wherein a delay time due to the de-interleave processing is set to one TV frame period or less.
M audio recording and playback device.