JP3043752B2 - VISS signal detection method and storage medium storing computer program for detecting VISS signal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer which does not have a hardware-based VISS detection function or cannot be used.
The present invention relates to a VISS signal detection method capable of detecting an S signal and a storage medium storing a computer program for detecting a VISS signal.

[0002]

2. Description of the Related Art A VISS signal is a VIS signal at the start of recording.
This signal is created by writing a fixed amount (the number within the standard) of the S pulse, and is used for finding the recording start position. Generally, in a cueing operation called by a name such as an index search, a video tape running at high speed is scanned, and normal reproduction is performed from a detection position of a VISS signal. The VISS system detects a VISS pulse created by changing the falling edge timing of the phase position detection signal recorded at the time of VTR recording.
When 25 or more ISS pulses are continuously detected, V
This is a system that determines that an ISS signal has been found. (The standard allows leakage of about 1 pulse during continuous detection, and a VISS signal is detected if 25 pulses are detected in 90% or more of the write pulses.) Judge that you did).

[0003] The occurrence of a delay in the start of interrupt processing will be described with reference to a time chart of FIG. At the timing 901 in FIG. 9, the processing A starts to be executed, and during the execution of the processing, an execution request for the processing B having a higher priority than the processing A and the processing C having a lower priority than the processing A occurs at the timing 902. In this case, the currently executing process A is interrupted, the process B is started, and the process C is in a start waiting state.

When the processing B is completed, the processing A having a higher priority than the processing C is restarted, and the execution of the processing C waits for the completion of the processing A. In this state, when an execution request of the interrupt processing D having a lower priority than the processing A and higher than the processing C occurs at the timing 903, the execution of the interrupt processing D is started immediately after the end of the processing A, and the execution of the processing C is performed. The start is waited until the end of the interrupt processing D. In this case, the time 910 from the generation of the request for the processing C to the actual start thereof is referred to as an interrupt delay time.

[0005] In the VTR system, disturbance of the drive control of the motor leads to disturbance of the image. Therefore, it is ideal to set the interrupt processing for motor drive control to the highest priority possible. Further, in order to minimize the interrupt delay time in the motor drive control processing, it is necessary to shorten the processing time of the interrupt processing having a higher priority than the motor drive control processing as much as possible.

FIG. 10 is a time chart showing a conventional operation of detecting a VISS signal, FIG. 11 is a block diagram showing an example of a register configuration inside a microcomputer used for conventional VISS pulse detection, and FIG. 12 is a standard of the VISS pulse. FIG.

The operation of VISS detection using conventional hardware will be described with reference to FIGS. FIG.
At 1, the timer 1103 measures the time of one cycle of the phase position detection signal, and is cleared by interruption of the phase position detection signal. The count value of the timer 1103 is stored in the comparison register 1102.

First, based on the phase position detection signal cycle time 1001 before the phase position detection signal cycle time measurement timing 1005 shown in FIG.
The VISS signal determination timing in the phase position detection signal cycle after 5 is determined. Here, the VISS signal determination timing is a time point at which half (50%) of the preceding phase position detection signal cycle time 1001 has elapsed from the measurement timing 1005. That is, it is determined whether or not the signal is a VISS signal based on the level of the phase position detection signal at this time. That is, the phase position detection signal waveform level is determined at the timing when the count value obtained in the immediately preceding phase position detection signal cycle and stored in the comparison register 1102 and the count value of the timer 1103 coincide with each other. It is determined as a VISS pulse, and if it is at a low level, it is determined as a normal pulse. At this time, the level of the phase position detection signal is detected by the level detection unit 1107, and VI
The data is stored in the SS detection buffer 1108. While the VISS detection buffer 1108 shifts and stores data in the VISS signal determination buffer 1109, the value of the newly acquired result is the value of the VISS signal determination buffer 1109, that is, the value already set as the pattern at the time of VISS detection. (In this example, the Hi level is 2
When five or more consecutive detections have been made), it is determined that a VISS signal has been found, and a vector interrupt is generated.

The above series of operations is automatically performed by hardware (the software only sets the VISS signal pattern), and the processing after the VISS is discovered is performed by a vector interrupt that occurs only when the VISS mark is discovered. The operation is performed by hardware.

The hardware setting for detecting the VISS signal in the above operation is performed by the detection edge selector 11 shown in FIG.
01, the VISS signal is detected using the rising edge of the phase position detection signal. This allows
When the rising edge of the phase position detection signal is detected, the count value of the timer 1103 for one cycle of the phase position detection signal is stored in the register 1102.
03 is cleared, and 50% of this time is stored in the register 1104. In the example of FIG. 10, at the timing 1005, the time of the period 1001 is the value of the timer 1103 stored in the comparison register 1102.

After the timer 1103 is cleared, the count of the timer 1103 again proceeds, and the value of the register 1104 (ie, 50% of the period 1101)
(Minute time), the phase position detection signal is detected, and the level of the phase position detection signal at that time is buffered in the VISS detection buffer 1108 by the level detection unit 1107, and the VISS signal determination buffer 1109 is set in advance. Is compared to the value.

When the above processing is repeated and the result of the level buffered in the VISS detection buffer 1108 matches the value of the VISS signal determination buffer 1109, an interrupt request 1110 for notifying that a VISS signal has been detected. Is output. The interrupt request 1110 is detected by software.

In the above-mentioned prior art, the detection processing of the VISS signal and the processing up to the detection of the VISS signal are automatically performed in hardware, so that the detection position is not delayed due to another interrupt. Therefore, it is effective when the phase position detection signal can be detected and the detected phase position detection signal can be used for detecting the VISS signal. However, it may not be usable due to the following problems.

First, there is another timer unit that uses the phase position detection signal as a detection edge (for example, the register 1105 in FIG. 11). May need to be set to detect both rising and falling edges in the phase position detection signal.
The interrupt process of the register 1105 is controlled by the phase control signal. However, since the processing load is heavy, the process is divided by detecting both edges of the phase position detection signal. However, register 11
05, the clearing of the timer 1103, and the capturing operation edge of the register 1102,
Since the timing is generated by the same signal, it is impossible to separately set the edge to be used.

Second, there is a case where the interval between the phase position detection signals is not constant in the state where the VISS detection is performed. At the time of fast-forward (FF) and rewind (REW), the detection processing of the VISS signal by the operation of the built-in hardware is performed based on the time of one cycle of the immediately preceding phase position detection signal.
The capture position for detecting the S signal is calculated. For this reason, if the speed of fast-forward or rewind is continuously increased rather than stepwise at regular intervals, the capture position is set to be delayed when the speed change amount is 50% or more. There is a possibility of misjudgment.

Next, a conventional method of detecting a VISS signal by setting to detect both rising and falling edges in the phase position detection signal by software will be described with reference to FIGS.

In this example, since the timer is cleared by both edges of the phase position detection signal shown in FIG. 13, a register for storing the count value of the timer (FIG. 11)
At the timing 1302, the value of the section 1301 is stored at the timing 1302.
Stores the value of the section 1303 and the timing 1307
In, the value of the section 1305 is stored. Also, since the value of the register is held until the next edge occurs, the VISS pulse determination process started by the edge (FIG. 14)
Can refer to the value of the register.

The VISS pulse determination processing of FIG. 14 will be described. The VISS pulse determination process is started according to each edge of the phase position detection signal in FIG. First, when the operation is started by the phase position detection signal edge at the timing 1302 in FIG. 13, the value of the edge counter is “0” as an initial state, so the value of the register is stored in the α buffer (steps 1401 and 1402). Then, the edge counter is updated to "1" in order to update the processing content (step 1403).

The edge counter is a counter for distributing the count value of a timer for measuring the time between edges of the phase position detection signal to a plurality of buffers, and counts up at rising and falling edges of the phase position detection signal. , And counts a continuous first value, second value... Like “0”, “1”, “2”.
When counting to a predetermined value, counting is restarted from the initial value. Based on the count value of the edge counter, a buffer for storing the value of the register is determined.

Next, when the operation is started by the phase position detection signal edge at the timing 1304 in FIG. 13, the value of the register is changed to β because the value of the edge counter is “1”.
Stored in the buffer (steps 1401 and 1404), and α
It is determined whether the phase position detection signal is a VISS pulse by comparing the value stored in the buffer with the value stored in the β buffer (step 140).
5). If the phase position detection signal is a VISS pulse,
The value of the VISS pulse counter for counting the number of VISS pulses is updated (step 1406), and if not, the count value of the VISS pulse counter is reset (step 1407). Then, the edge counter is updated to “0” to make the next storage destination the α buffer (step 1408).

Next, it is determined whether or not the value of the VISS pulse counter has reached a preset reference value. If the value has reached the reference value, information indicating that 10 VISS signals have been detected is created. (Steps 1409 and 141
0). Note that VISS is applied to each edge of the phase position detection signal.
Instead of determining whether a signal has been detected, the VISS signal is monitored when it is confirmed that the value of the VISS pulse counter has reached a predetermined reference value by a VISS pulse count monitoring process performed at regular intervals. It is also conceivable to determine that it has been detected.

However, during the detection of the VISS pulse, the feed amount of the tape must be controlled.
In some cases, the start of the VISS interrupt may be delayed due to interrupt control (for example, tape speed, phase control, rotary head speed, phase control) having a higher priority than the S signal detection processing. In the VISS signal detection processing in the case where the tape runs at a normal speed such as during reproduction, even if the start of the VISS signal detection processing occurs due to a high-priority interrupt processing, it is shown in FIG. Since there is enough time between the edges (9.15
mS), edge data is not missed.
However, in the VISS signal detection processing when the tape runs at a high speed such as during fast-forward or rewind, the time between edges is only a short time as shown in FIG. 12B (about 0.8 mS). When the waiting for the start of the VISS signal detection processing occurs due to the interrupt processing with high priority, the next edge of the phase position detection signal may occur while the processing is in the standby state. In the case of FIG. 13 as an example, an interrupt of the VISS signal detection processing occurs at the timing 1304, but the interrupt processing 1305 having a high priority is performed.
Is executed, the start of the VISS signal detection process is delayed until timing 1306. As a result, the value of the register at the timing 1304 is not stored in the β buffer. Since the edge generated at the timing 1307 during the interrupt processing 1305 cannot be detected, the value of the register is overwritten at 1306 at the start of the VISS signal detection processing.
4, the value of the register is erased.

That is, the setting of the process started at the timing 1306 is a process that should start at the timing 1304, so the value of the register is written into the β buffer.
At this time, the value of the register has already been overwritten as described above, and the value of the register in the section 1305 (the value of the register at the timing 1307) is stored in the β buffer, so that a normal determination cannot be made.

Further, the conventional VISS signal detection method described with reference to FIGS. 13 and 14 cannot detect a VISS signal at the time of fast forward or rewind at a speed exceeding 5 times speed.

[0025]

As described above, as a conventional technique for detecting a VISS signal recorded on a video tape, a technique of detecting using a hardware can be implemented by a microcomputer having no hardware configuration. Also, even if the microcomputer has the hardware configuration, the VI
There is a disadvantage that it may not be used for detecting the SS signal.

In the conventional method of detecting the VISS signal by software, the detection of the edge of the phase position detection signal at the time of high-speed running of the videotape occurs, and an accurate VISS signal is generated.
There is a disadvantage that the SS signal cannot be detected.

The present invention solves the above-mentioned disadvantages of the prior art, and does not omit detection of a phase position detection signal edge even during high-speed running of a video tape and can accurately detect a VISS signal. It is an object to provide a storage medium storing a computer program for detecting a VISS signal and a method.

[0028]

According to a VISS signal detection method of the present invention, which achieves the above objects, a process of executing a process of capturing an inter-edge time for each level edge of a VISS signal and a process of detecting a VISS pulse are performed. And V
Performing a VISS signal detection process based on the detection result of the ISS pulse detection means, wherein the process of the inter-edge time capturing process is set as an interrupt process having the highest priority, and in the VISS pulse detection process, , VI used in the inter-edge time capturing step
By referring to the count value of the edge counter for distributing the count value of the timer for measuring the time between edges of the phase position detection signal to which the SS signal is added to a plurality of buffers, The presence / absence of a delay in the processing of the step is determined based on the number of times the edge-to-edge time capturing step has occurred, and if a delay has occurred, a VISS pulse detection process corresponding to the delay and the edge-to-edge time in the next cycle are performed. It is characterized in that post-processing for accurately performing the fetch processing is performed.

As a result, the VISS pulse can be detected even in the frame immediately after the occurrence of the delay, and the VISS signal can be detected even during high-speed tape running during fast-forward or rewind.

According to a second aspect of the present invention, in the method of detecting a VISS signal according to the present invention, the step of capturing the time between edges includes the step of checking the value of an edge counter, and the step of acquiring the value of the edge counter being a predetermined first value. Storing the value of the register storing the count value of the timer in the first buffer; and storing the value of the register in the second buffer when the value of the edge counter is a predetermined second value. Storing the value of the register in a third buffer if the value of the edge counter is a predetermined third value; and storing the value of the edge counter in the third buffer. 2
, The value of the register is stored in any one of the first buffer, the second buffer, and the third buffer, and then the value of the edge counter is updated. Next, the buffer for writing a value is changed. The VISS pulse detecting step includes a step of checking a value of an edge counter, and performing any processing when the value of the edge counter is a second value. And when the value of the edge counter is the third value, the value of the register stored in the first buffer is compared with the value of the register stored in the second buffer. Then, it is determined whether the phase position detection signal is a VISS pulse or not.
Updating the count value of the S-pulse counter and initializing the count value of the VISS pulse counter when it is determined that the pulse is not a VISS pulse; and when the edge counter value is a predetermined fourth value, The value of the register stored in the first buffer is compared with the value of the register stored in the second buffer to determine whether or not the phase position detection signal is a VISS pulse. The count value of the VISS pulse counter is updated, and when it is determined that the count value is not a VISS pulse, the count value of the VISS pulse counter is initialized, the buffer information is corrected, and the contents of the third buffer are moved to the first buffer. And when the value of the edge counter is not one of the second value, the third value, and the fourth value, Initializing the value of the SS pulse counter; and updating or initializing the count value of the VISS pulse counter in a process when the value of the edge counter is a third value; Initializing the edge counter after processing for initializing the count value of the VISS counter when the value is not any of the second value, the third value, and the fourth value. .

According to a third aspect of the present invention, in the method for detecting a VISS signal according to the third aspect of the present invention, when the value of the edge counter becomes a predetermined fifth value by updating, the step of capturing the time between edges includes The method further includes a step of notifying occurrence.

According to a fourth aspect of the present invention, in the method of detecting a VISS signal according to the present invention, the step of capturing the time between edges includes the step of examining a value of an edge counter, and the case where the value of the edge counter is a predetermined first value. The value of the register storing the count value of the timer is stored in the first buffer, and if the VISS determination reference time is set, the VI
The SS determination reference time is compared with the value of the first buffer to determine whether or not the phase position detection signal is a VISS pulse. If it is determined that the phase position detection signal is a VISS pulse, the count value of the VISS pulse counter is updated. Initializing the count value of the VISS pulse counter when it is determined that the value of the edge counter is a predetermined second value, and storing the value of the register in a second buffer when the value of the edge counter is a predetermined second value; Storing the value of the register in a third buffer when the value of the edge counter is a predetermined third value;
If the count value of the VISS pulse counter is not the value of the second value or the third value, the count value of the VISS pulse counter is updated or initialized in a process in a case where the value of the edge counter is the first value, and Storing the value of the register in one of the second buffer and the third buffer, and then updating the value of the edge counter to change the buffer to which the next value is written. ,
Checking the value of the edge counter; and, if the value of the edge counter is the second value, ending the operation without performing any processing, and if the value of the edge counter is the third value. Measuring the period of the phase position detection signal and setting the VISS pulse determination reference time; and when the value of the edge counter is a fourth value,
The period of the phase position detection signal is measured, the VISS pulse determination reference time is set, the buffer information is corrected, the contents of the third buffer are moved to the first buffer, and the set VISS pulse determination reference time is further set. And the value of the first buffer, and determines whether or not the phase position detection signal is a VISS pulse. If it is determined that the phase position detection signal is a VISS pulse, the count value of the VISS pulse counter is updated,
Initializing the count value of the VISS pulse counter if it is determined that the pulse is not the S pulse; and determining the VISS pulse value if the value of the edge counter is not any of the second value, the third value, and the fourth value. Initializing the value of a pulse counter, and after setting the VISS pulse determination reference time in the process when the value of the edge counter is a third value, and when the value of the edge counter is a second value,
The VIS when neither the third value nor the fourth value
Initializing the edge counter after the process of initializing the count value of the S counter.

Further, in the VISS signal detecting method according to the present invention, in the VISS pulse detecting step, a half of the period of the measured phase position detection signal is set to the VISS pulse detecting step.
It is characterized in that it is set to the SS pulse determination reference time.

According to a sixth aspect of the present invention, in the method for detecting a VISS signal according to the first aspect of the present invention, when the inter-edge time capturing step is performed, the value of the edge counter becomes a fifth value by updating.
The method further comprises the step of notifying the occurrence of a buffering error.

The VISS signal detection method of the present invention
For example, it is executed in a CPU or other data processing device. In this case, a computer program for realizing the VISS signal detection method of the present invention is provided by being stored in a storage medium and loaded into the data processing device.

[0036]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 illustrates a VIS according to one embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a system that implements an S signal detection method. Referring to FIG. 1, a system for realizing the present embodiment includes an inter-edge time acquisition processing step 101 for executing an inter-edge time acquisition processing for each level edge of a VISS signal, and an inter-edge time acquisition processing step 101. A VISS pulse detection processing step 102 for detecting a VISS pulse activated when the used edge counter 101a is updated or the inter-edge time acquisition processing step 101 is completed, and a VISS signal is detected at 10 ms intervals. And a VISS signal detection processing step 103 for performing the processing. These computer programs are provided, for example, stored in a program-controlled CPU and other data processing devices and an internal memory.

The inter-edge time fetch processing step 101 is set so that the priority is set higher than other interrupt processing as much as possible, and the interrupt processing by edge detection can be executed even during execution of other interrupt processing. . This makes it possible to capture the time between edges of the phase position detection signal in the register without causing a delay. Since the priority of the VISS pulse detection processing step 102 is not particularly set higher than that of other interrupt processing, a delay due to other interrupt processing may occur. However, even if the processing in the VISS pulse detection processing step 102 is delayed by the execution of another interrupt processing, the count value of the edge counter 101a used in the edge-to-edge time capturing processing step 101 that executes the processing without delay. , It is possible to detect that a delay has occurred in the processing in the VISS pulse detection processing step 102 and perform normal pulse judgment (comparison between the α buffer and the β buffer).

The edge counter 101a is a counter for distributing a count value of a timer for measuring a time between edges of the phase position detection signal to a plurality of buffers, and counts at rising and falling edges of the phase position detection signal. Up (updated), "0", "1",
A first value, a second value, such as "2" ...
・ When counting to a predetermined value, counting is restarted from the initial value. Based on the count value of the edge counter 101a, the value is determined from a plurality of buffers that store the value of the register (see register 1102 in FIG. 11) that stores the count value of the timer. Note that the value counted by the edge counter 101a may be a continuous value, and the values shown in the present embodiment (“1”, “2”,...)
・) It is not necessary to be.

FIG. 2 is a flowchart showing the operation of the inter-edge time acquisition processing step 101 of this embodiment. Referring to FIG. 2, the inter-edge time acquisition processing step 101 first checks the value of the edge counter 101a (step 201,
203, 205), if the value is “0”, the register storing the count value of the timer (register 110 in FIG. 11)
2) is stored in the α buffer which is the first buffer (steps 201 and 202). If the value of the edge counter 101a is “1”, the value of the register is stored in the β buffer, which is the second buffer (steps 203 and 204). If the value of the edge counter 101a is “2”, the value of the register is stored in the γ buffer as the third buffer (steps 205 and 20).
6). When the value of the edge counter 101a is “0”, “1”,
If it is not any of “2” and after storing the register value in any of the α buffer, β buffer, and γ buffer, update the value of the edge counter 101a by one and change the buffer to which the next value is written ( Step 207). Then, the value of the edge counter 101a is updated to “4”.
, The occurrence of a buffering error is notified (step 208).

FIG. 3 is a flowchart showing the operation of the VISS pulse detection processing step 102 of this embodiment. FIG.
Referring to, the VISS pulse detection processing step 102 includes:
First, the value of the edge counter 101a is checked (step 30).
1, 302, 306), if the value is “1”, the operation ends without performing any processing (step 301). If the value of the edge counter 101a is "2", the value of the register stored in the .alpha. Buffer is compared with the value of the register stored in the .beta.
It is determined whether the pulse is an SS pulse (steps 302 and 30).
3). If it is determined that the pulse is a VISS pulse,
The count value of the S pulse counter is updated (step 30).
4) If it is determined that the pulse is not a VISS pulse,
Initialize the count value of the pulse counter (step 3
05). After these processes, the edge counter 101a is initialized (step 312). Edge counter 101
If the value of “a” is “3”, the value of the register stored in the α buffer is compared with the value of the register stored in the β buffer to determine whether or not the phase position detection signal is a VISS pulse (step 306, 307). And VI
If it is determined that the pulse is the SS pulse, the count value of the VISS pulse counter is updated (step 308). If it is determined that the pulse is not the VISS pulse, the count value of the VISS pulse counter is initialized (step 309). After these processes, if the value of the edge counter 101a is "3", since the phase position detection signal edge has occurred during the interrupt delay, the buffer information is corrected and the content of the γ buffer is moved to the α buffer. (Step 310). If the value of the edge counter 101a is not one of "1", "2", and "3", it is determined that a plurality of edges have been detected during the interrupt delay, so that accurate pulse determination becomes impossible. , It is necessary to initialize the VISS detection processing. Therefore, the value of the VISS pulse counter is initialized (step 311), and subsequently the edge counter 101a
Is initialized (step 312).

FIG. 4 is a flowchart showing the operation of the VISS pulse detection processing step 103 of this embodiment. FIG.
Referring to FIG. 5, the VISS pulse detection processing step 103
First, the value of the VISS pulse counter counted in the VISS pulse detection processing step 102 is checked (step 401). If the value of the VISS pulse counter is equal to or greater than the specified pulse, information indicating that a VISS signal has been detected is created (step 402).

Next, the operation according to the present embodiment will be described by taking as an example a case where an interrupt request is generated at the timing shown in the timing chart of FIG. In the present embodiment, even if some processing is being executed by detecting the phase position detection signal edge, the processing is interrupted, and the processing in the inter-edge time acquisition processing step 101 having the highest priority is executed. Thereafter, if no other interrupt processing is performed, the processing in the VISS pulse detection processing step 102 is subsequently executed. VISS pulse detection processing step 10
In the case where a process having a higher priority than the process by No. 2 is being executed or is in a standby state, after all such processes are completed, V
The processing in the ISS pulse detection processing step 102 is executed.

More specifically, when the VISS signal detection processing is started at timing 501 in FIG. 5, the inter-edge time acquisition processing step 101 and the VISS pulse detection processing are performed by the phase position detection signal edge generated at timing 505. Step 102 is activated. In the inter-edge time fetch processing step 101, the edge counter 101a is initialized at a timing 504 in FIG. Therefore, the inter-edge time fetch processing step 101 determines that the value of the edge counter 101a is “0” (see step 201), and writes the value of the register (the time of the section 506 in FIG. 5) to the α buffer (step 202) ), And updates the value of the edge counter 101a to “1” (step 207).
reference). Further, since the updated value of the edge counter 101a has not reached "4", the process ends without determining that an error has occurred (see step 208).

After completion of the processing in the inter-edge time fetch processing step 101, the VISS pulse detection processing step 102 is started. In the VISS pulse detection processing step 102, since the value of the edge counter 101a is "1" in the edge counter determination processing, it is determined that the data to be compared is not complete, and the processing ends (step 301).

Next, in response to the phase position detection signal edge at the timing 501 in FIG. 5, the inter-edge time fetch processing step 101 is started again. Edge time capture processing step 101
Writes the value of the register into the β buffer because the value of the edge counter 101a has been updated to “1” (see steps 203 and 204). And the edge counter 1
01a is updated to “2” (see step 207),
Since the value of the updated edge counter 101a is "2", the process ends without determining that an error has occurred (step 20).
8).

After completion of the processing in the inter-edge time acquisition processing step 101, there is no interruption delay (at timing 5 in FIG. 5).
When the VISS pulse detection processing step 102 is started (before 02), the value of the α buffer is compared with the value of the β buffer because the value of the edge counter 101a is “2” (steps 302 and 303). reference). That is,
It is determined whether the phase position detection signal is a VISS pulse or not based on the ratio between the time of the section 506 and the time of the section 507 in FIG. When the phase position detection signal is VI
When it is determined that the pulse is the SS pulse, the value of the VISS counter is updated (see step 304). When it is determined that the pulse is not the VISS pulse, the VISS counter is initialized (see step 305). Then, the edge counter 101a is initialized for the next pulse measurement (step 3).
12).

On the other hand, the VISS pulse detection processing step 102
, A VISS pulse detection processing step 102 is performed after the timing 502 in FIG.
Is started, the timing 502 in FIG.
It means that the processing of the inter-edge time capturing processing step 101 has been completed. The operation of the inter-edge time acquisition processing step 101 at this time is to check the edge counter 101a, write the value of the register (the time of the section 508 in FIG. 5) to the β buffer, and update the value of the edge counter 101a to “3”. Then, the process ends without determining that an error has occurred (step 20).
3, 204, 207, 208).

In this case, VISS pulse detection processing step 1
In the case of 02, since the value of the edge counter 101a is “3”, the value of the α buffer is compared with the value of the β buffer (see steps 306 and 307). It is determined whether the phase position detection signal is a VISS pulse or not. If the phase position detection signal is determined to be a VISS pulse, the value of the VISS counter is updated (see step 308).
The SS counter is initialized (see step 309). Then, since the data in the γ buffer becomes the data of the next α buffer, the contents of the γ buffer are moved to the α buffer, and the value of the register is changed to the value of the β buffer As stored in
The edge counter 101a is changed to "1" and the process is terminated (see step 310).

Thereafter, at the timing 509 in FIG. 5, the value of the edge counter 101a is "1".
As described above, in the processing of the inter-edge time acquisition processing step 101, the value of the register is stored in the β buffer. Then, when the VISS pulse detection processing step 102 is processed without any interruption delay, the operation of detecting the VISS pulse is immediately performed. Even if an interrupt delay occurs, the value of the register is stored in the γ buffer in the inter-edge time fetching step 101, and after the VISS pulse detecting operation is performed in the VISS pulse detecting step 102, The contents are moved to the α buffer.

The VISS pulse detection processing step 102
If the value of the edge counter 101a is other than a valid value (“1”, “2”, “3”) in the processing according to the above, it is determined that there is no credibility of the time between edges and the accumulated buffer data is invalidated. I do. Then, in order to restart the VISS signal detection from the beginning, the number of VISS pulses detected up to that point is cleared, and the edge counter 101
a is initialized to clear the edge time data storage position.

Next, the VIS according to another embodiment of the present invention
The S signal detection method will be described. VIS of the present embodiment
The system for implementing the S signal detection method is the same as the system shown in FIG. FIGS. 6 to 8 show an inter-edge time capture processing step 101, a VISS pulse detection processing step 102, and a VISS pulse detection processing step 1 in the present embodiment.
03 shows the operation.

In this embodiment, as shown in FIG. 7, the VISS pulse detection processing step 102 compares the value of the α buffer with the value of the β buffer to determine whether the phase position detection signal is VI.
Without performing the process of determining whether it is an SS pulse,
The time from the falling edge of the phase position detection signal edge to the next falling edge (the total time of the section 506 and the section 507 in FIG. 5) is obtained, and the VISS determination reference time is calculated.

The inter-edge time acquisition processing step 101 is shown in FIG.
When the reference time is set in the VISS pulse detection processing step 102, as shown in FIG.
The value of the register (time counted by the timer) is fetched into the buffer, the fetched time is compared with a reference time, and the phase position detection signal is VISS based on the comparison result.
Determine if it is a pulse.

Next, the operation according to this embodiment will be described with reference to the timing chart of FIG. 5 and the flowcharts of FIGS. When the VISS signal detection processing is started at the timing 501 in FIG. 5, the edge position acquisition processing step 101 and the VISS pulse detection processing step 102 are started by the phase position detection signal edge generated at the timing 505. In the inter-edge time fetch processing step 101, the edge counter 101a is initialized at a timing 504 in FIG. Therefore, the inter-edge time acquisition processing step 101 determines that the value of the edge counter 101a is “0” (step 601),
The value of the register (the time in the section 506 in FIG. 5) is written into the α buffer (step 602). In this processing cycle, since the VISS determination reference time (set value of half the time of one cycle of the phase position detection signal) is not set, the process proceeds to the edge counter update process (step 603), and the value of the edge counter 101a is changed to “ 1 ”(Step 6
11), the value of the updated edge counter 101a is “1”
Therefore, the process ends without determining that an error has occurred (step 612).

After the end of the processing in the inter-edge time acquisition processing step 101, the VISS pulse detection processing step 102 is started. In the VISS pulse detection processing step 102, in the edge counter determination processing, since the value of the edge counter 101a is "1", it is determined that the data for obtaining the VISS determination reference time is not complete, and the processing ends (step 701). ).

Next, the inter-edge time acquisition processing step 101 is started again by the phase position detection signal edge at the timing 501 in FIG. Edge time capture processing step 101
Writes the value of the register into the β buffer since the value of the edge counter 101a has been updated to “1” (steps 607 and 608). Then, the edge counter 101
The value of “a” is updated to “2” (step 611), and since the updated value of the edge counter 101a is “2”, the process ends without determining that an error has occurred (step 612).

After completion of the processing in the inter-edge time acquisition processing step 101, there is no interruption delay (at timing 5 in FIG. 5).
When the VISS pulse detection processing step 102 is started (before 02), the value stored in the α buffer and the value stored in the β buffer are added because the value of the edge counter 101a is “2”. Then, the phase position detection signal cycle time is calculated (steps 702 and 703). Then, １ ／ of the calculated phase position detection signal cycle time is set as a reference time for VISS pulse determination, and information indicating that the reference time has been set is created (step 704). Thereafter, the edge counter 101a is initialized (Step 713).

Thereafter, in the phase position detection signal detection at the timing 502 in FIG. 5, the inter-edge time fetch processing step 101 stores the register value in the α buffer because the edge counter 101a has been returned to “0”. Write (steps 601 and 602). Since the VISS determination reference time has been set in step 704, the VISS determination reference time is compared with the value of the α buffer to determine whether the phase position detection signal is a VISS pulse (step 604). That is, if the value of the α buffer is longer than the reference time value, it is determined that the pulse is a VISS pulse. If it is determined that the phase position detection signal is a VISS pulse, the value of the VISS pulse counter is updated (step 605). If it is determined that the pulse is not a VISS pulse,
The count value of the ISS pulse counter is initialized (Step 606). After these processes, the edge counter 10
1a is updated to "1" (step 611), and the process ends without determining that an error has occurred (step 612). And
In the next interrupt by the phase position detection signal edge (timing 509 in FIG. 5), the edge counter 101
Interruption processing when the value of a is “1” is performed.

On the other hand, the VISS pulse detection processing step 102
, A VISS pulse detection processing step 102 is performed after the timing 502 in FIG.
Is started, the timing 502 in FIG.
It means that the processing of the inter-edge time capturing processing step 101 has been completed. The operation of the inter-edge time acquisition processing step 101 at this time is to check the edge counter 101a, write the value of the register (the time of the section 508 in FIG. 5) to the γ buffer, and update the value of the edge counter 101a to “3”. Then, the process ends without determining that an error has occurred (step 60).
9, 610, 611, 612).

In this case, VISS pulse detection processing step 1
In No. 02, since the value of the edge counter 101a is “3”, the value stored in the α buffer and the value stored in the β buffer are added to calculate the phase position detection signal cycle time (step 706). ). Then, １ ／ of the calculated phase position detection signal cycle time is set as a reference time for VISS pulse determination, and information that the reference time has been set is created (step 707). After that, the data in the γ buffer becomes the data in the next α buffer, so the contents of the γ buffer are moved to the α buffer, and the value of the register is set to β in the next edge time acquisition processing step 101. The edge counter 101a is changed to "1" so as to be stored in the buffer (step 708).

Next, the VIS created in step 707 is
The S determination reference time is compared with the value of the α buffer to determine whether the phase position detection signal is a VISS pulse (step 709). That is, if the value of the α buffer is longer than the reference time value, it is determined that the pulse is a VISS pulse. If the phase position detection signal is determined to be a VISS pulse,
The value of the ISS pulse counter is updated, and the process ends (Step 710). If it is determined that the pulse is not a VISS pulse, the count value of the VISS pulse counter is initialized and the process ends (step 711). Then, the next phase position detection signal edge (timing 5 in FIG. 5)
In the interruption by 09), an interruption process is performed when the value of the edge counter 101a is "1".

The VISS pulse detection processing step 102
If the value of the edge counter 101a is other than a valid value (“1”, “2”, “3”) in the processing according to the above, it is determined that there is no credibility of the time between edges and the accumulated buffer data is invalidated. I do. Then, in order to restart the VISS signal detection from the beginning, the number of VISS pulses detected up to that point is cleared, and the edge counter 101
a is initialized to clear the edge time data storage position.

As described above, each of the above-described embodiments corresponds to the VIS
If the execution of the detection processing of the S pulse is delayed, the data is stored in the γ buffer and processed in the processing for capturing the time between edges of the phase position detection signal, and the VISS pulse detection processing is performed. By moving to the α buffer, the VISS pulse can be detected even in the frame immediately after the occurrence of the delay. For this reason, in the conventional VISS signal detection method, when the error of the VISS detection processing caused by the delay occurs, it is not necessary to reset the processing. Also makes it possible to detect the VISS signal.

Further, in the above-described other embodiment for calculating the VISS judgment reference time in the processing of the VISS pulse detection processing step, a buffer for storing the set value of the VISS judgment reference time is required, and the phase position detection signal cycle calculation is performed. Processing time will be added by the amount of time required to perform VI.
There is no effect on the SS signal detection performance.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0067]

As described above, the VISS of the present invention is
According to the signal detection method and the storage medium storing the computer program for detecting the VISS signal, a case where the cycle of the phase position detection signal is shortened due to high speed running at the time of fast-forward or rewind of the tape and interrupt delay is likely to occur Even in this case, even when the video tape is running at high speed, there is an effect that the detection of the edge of the phase position detection signal is not missed and the VISS signal can be detected accurately.

Specifically, for example, in the conventional method, VI
If a phase position detection signal edge occurs even once during the SS detection interrupt delay, it is necessary to discard the VISS pulse measurement result up to that point and perform a new measurement.
In some cases, measurement omission of the VISS pulse that has been written and written may occur. However, according to the present invention, when the phase position detection signal edge is generated up to once while the VISS pulse determination interrupt processing is delayed. But the delayed VISS
VISS pulses can be detected continuously after the execution of the pulse determination process.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a system that implements a VISS signal detection method according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of an edge-to-edge time capturing process according to the first embodiment;

FIG. 3 is a flowchart showing an operation of a VISS pulse detection processing step of the first embodiment.

FIG. 4 is a flowchart showing an operation of a VISS pulse detection processing step of the first embodiment.

FIG. 5 is a timing chart showing measurement targets and operation timings in the VISS signal detection method of the present invention.

FIG. 6 is a flowchart showing an operation of an inter-edge time fetching process in a VISS signal detection method according to a second embodiment of the present invention.

FIG. 7 is a flowchart showing the operation of a VISS pulse detection processing step of the second embodiment.

FIG. 8 is a flowchart showing an operation of a VISS pulse detection processing step of the second embodiment.

FIG. 9 is a timing chart illustrating interrupt processing.

FIG. 10 is a timing chart showing a VISS waveform detection operation.

FIG. 11 is a block diagram illustrating an example of a hardware configuration when a VISS signal is detected using hardware.

FIG. 12 is a diagram showing a standard of a VISS pulse.

FIG. 13 is a timing chart showing measurement targets and operation timings in a conventional VISS signal detection method.

FIG. 14 is a flowchart showing a conventional software-based VISS signal detection method.

[Explanation of symbols]

 101 Time acquisition processing between edges 101a Edge counter 102 VISS pulse detection processing step 103 VISS pulse detection processing step

Claims (12)

(57) [Claims] A step of acquiring a time between edges for each level edge of a VISS signal; a step of detecting a VISS pulse; and a VI based on a detection result of the VISS pulse detection means.
Performing a process of detecting an SS signal, wherein the process of the inter-edge time capturing step is set as an interrupt process having the highest priority, and is used in the inter-edge time capturing step in the VISS pulse detecting step. VISS
By referring to the count value of the edge counter for distributing the count value of the timer for measuring the time between edges of the phase position detection signal to which the signal is added to a plurality of buffers, the edge generated up to the processing of the process The presence / absence of a delay in the processing of the process is determined based on the number of occurrences of the interval time capturing process, and if a delay occurs, the VISS corresponding to the delay is determined.
A VISS signal detection method, comprising: performing post-processing for accurately performing pulse detection processing and the edge-to-edge time capturing processing in the next cycle. 2. The inter-edge time capturing step includes: checking an edge counter value; and, when the edge counter value is a first predetermined value, changing a value of a register storing a count value of a timer. Storing the value of the edge counter in a second buffer when the value of the edge counter is a predetermined second value; and storing the value of the edge counter in a second buffer when the value of the edge counter is a predetermined second value. Storing the value of the register in a third buffer when the value is the third value; and when the value of the edge counter is not any of the first value, the second value, and the third value. And, after storing the value of the register in one of the first buffer, the second buffer, and the third buffer, updating the value of the edge counter and changing the buffer to which the next value is written. Including The VISS pulse detecting step includes a step of examining a value of an edge counter; and, if the value of the edge counter is a second value, ending the operation without performing any processing; If the value is 3, the value of the register stored in the first buffer is compared with the value of the register stored in the second buffer to determine whether the phase position detection signal is a VISS pulse. Then V
Updating the count value of the VISS pulse counter when it is determined that the pulse is an ISS pulse, and initializing the count value of the VISS pulse counter when determining that the pulse is not a VISS pulse; , The value of the register stored in the first buffer is compared with the value of the register stored in the second buffer to determine whether the phase position detection signal is a VISS pulse. If it is determined that the pulse is a pulse, the count value of the VISS pulse counter is updated. If it is determined that the pulse is not a VISS pulse, the count value of the VISS pulse counter is initialized. To the first buffer; and when the value of the edge counter is a second value, a third value, If not, the step of initializing the value of the VISS pulse counter; and updating or initializing the count value of the VISS pulse counter in the processing when the value of the edge counter is a third value. After initialization, and after the processing of initializing the count value of the VISS counter when the value of the edge counter is not any of the second value, the third value, and the fourth value, the edge counter is initialized. 2. The VISS signal detection method according to claim 1, further comprising the step of: 3. The inter-edge time capturing step further includes a step of notifying the occurrence of a buffering error when the value of the edge counter reaches a predetermined fifth value by updating. V according to claim 2
ISS signal detection method. 4. The inter-edge time capturing step includes: checking a value of an edge counter; and, when the value of the edge counter is a predetermined first value, changing a value of a register storing a count value of a timer. When the phase position detection signal is stored in the first buffer and the VISS determination reference time is set, the VISS determination reference time is compared with the value of the first buffer to determine whether the phase position detection signal is a VISS pulse. Updating the count value of the VISS pulse counter when it is determined that the pulse is a VISS pulse, and initializing the count value of the VISS pulse counter when determining that the pulse is not a VISS pulse; Storing the value of the register in a second buffer when the value of the edge counter is a predetermined third value. Storing the value of the register in a third buffer when the value of the edge counter is not one of the first value, the second value, and the third value. After updating or initializing the count value of the VISS pulse counter in the process when the value is the first value, and
After the value of the register is stored in one of the buffer and the third buffer, updating the value of the edge counter to change the buffer to which the next value is written, and the VISS pulse detecting step includes: Checking the value of the edge counter; and, if the value of the edge counter is the second value, ending the operation without performing any processing; and, if the value of the edge counter is the third value, Measuring the period of the phase position detection signal and setting the VISS pulse determination reference time; and, when the value of the edge counter is a fourth value, measuring the period of the phase position detection signal. A pulse judgment reference time is set, the buffer information is corrected, the contents of the third buffer are moved to the first buffer, and the set VISS pulse judgment reference time and The comparator compares the value of the first buffer, the phase position detection signal to determine whether VISS pulse, if it is determined that the VISS pulse VI
Updating the count value of the SS pulse counter and initializing the count value of the VISS pulse counter when it is determined that the count value is not a VISS pulse; and setting the edge counter value to a second value, a third value, or a fourth value. If the value is not any of the values, after initializing the value of the VISS pulse counter, and after setting the VISS pulse determination reference time in the processing when the value of the edge counter is a third value,
And the value of the edge counter is a second value, a third value,
2. A step of initializing the edge counter after processing for initializing the count value of the VISS counter when the value is not any of the fourth values.
4. The VISS signal detection method according to 1. 5. In the VISS pulse detecting step,
5. The VISS signal detection method according to claim 4, wherein a half of the period of the measured phase position detection signal is set as the VISS pulse determination reference time. 6. The inter-edge time capturing step, further comprising the step of notifying the occurrence of a buffering error when the value of the edge counter becomes a fifth value by updating. 6. The VISS signal detection method according to claim 4 or claim 5. 7. A storage medium storing a computer program for controlling a data processing device, the computer program executing a process of capturing a time between edges for each level edge of a VISS signal, and detecting a VISS pulse. Performing VI processing based on the detection result of the VISS pulse detecting means.
Performing a process of detecting an SS signal, wherein the process of the inter-edge time capturing step is set as an interrupt process having the highest priority, and is used in the inter-edge time capturing step in the VISS pulse detecting step. VISS
By referring to the count value of the edge counter for distributing the count value of the timer for measuring the time between edges of the phase position detection signal to which the signal is added to a plurality of buffers, the edge generated up to the processing of the process The presence / absence of a delay in the processing of the process is determined based on the number of occurrences of the interval time capturing process, and if a delay occurs, the VISS corresponding to the delay is determined.
A storage medium storing a computer program for detecting a VISS signal, wherein the computer program performs post-processing for accurately performing a pulse detection process and the edge-to-edge time capturing process in a next cycle. 8. The inter-edge time capturing step includes: checking a value of an edge counter; and when the value of the edge counter is a first value, storing a count value of a timer in a first value. Storing the value of the register in a second buffer when the value of the edge counter is a second value; and storing the value of the edge counter in a third buffer. Storing the value of the register in a third buffer; and when the value of the edge counter is not any of the first value, the second value, and the third value, and Storing the value of the register in one of a second buffer and a third buffer, and then updating the value of the edge counter to change the buffer to which the next value is written. The output step is a step of checking the value of an edge counter. If the value of the edge counter is a second value, the operation ends without any processing, and the value of the edge counter is a third value. , The value of the register stored in the first buffer is compared with the value of the register stored in the second buffer to determine whether the phase position detection signal is a VISS pulse.
Updating the count value of the VISS pulse counter when it is determined that the pulse is an ISS pulse, and initializing the count value of the VISS pulse counter when determining that the pulse is not a VISS pulse; and the value of the edge counter is a fourth value. In this case, the value of the register stored in the first buffer is compared with the value of the register stored in the second buffer to determine whether the phase position detection signal is a VISS pulse.
If it is determined that the pulse is an ISS pulse, the count value of the VISS pulse counter is updated. If it is determined that the pulse is not a VISS pulse, the count value of the VISS pulse counter is initialized. To the first buffer; and, if the value of the edge counter is not any of the second value, the third value, and the fourth value, initializing the value of the VISS pulse counter. After updating or initializing the count value of the VISS pulse counter in the processing when the value of the edge counter is the third value, and when the value of the edge counter is the second value, the third value, After the process of initializing the count value of the VISS counter when the value is not any of the values of 4, the step of initializing the edge counter. Storage medium storing a computer program for detecting a VISS signal according to claim 7, characterized in Mukoto. 9. The method according to claim 1, wherein the step of capturing the time between edges further includes a step of notifying the occurrence of a buffering error when the value of the edge counter becomes a fifth value by updating. VISS described in 8 above
A storage medium storing a computer program for detecting a signal. 10. The inter-edge time capturing step includes: checking a value of the edge counter; and, if the value of the edge counter is a first value, changing a value of a register storing a count value of a timer to a second value. 1 and the VISS determination reference time is set, the VISS determination reference time is compared with the value of the first buffer to determine whether or not the phase position detection signal is a VISS pulse. If VISS pulse is determined, V
Update the count value of the ISS pulse counter, and
Initializing the count value of a VISS pulse counter when it is determined that the pulse is not a pulse; storing the value of the register in a second buffer when the value of the edge counter is a second value; If the value of the edge counter is a third value, storing the value of the register in a third buffer; and if the value of the edge counter is a first value, a second value, and a third value. In the case where the value of the edge counter is the first value, the count value of the VISS pulse counter is updated or initialized in the processing when the value of the edge counter is the first value;
After the value of the register is stored in one of the buffer and the third buffer, updating the value of the edge counter to change the buffer to which the next value is written, and the VISS pulse detecting step includes: Checking the value of the edge counter; and, if the value of the edge counter is the second value, ending the operation without performing any processing; and, if the value of the edge counter is the third value, Measuring the period of the phase position detection signal and setting the VISS pulse determination reference time; and, when the value of the edge counter is a fourth value, measuring the period of the phase position detection signal. A pulse judgment reference time is set, the buffer information is corrected, the contents of the third buffer are moved to the first buffer, and the set VISS pulse judgment reference time and The comparator compares the value of the first buffer, the phase position detection signal to determine whether VISS pulse, if it is determined that the VISS pulse VI
Updating the count value of the SS pulse counter and initializing the count value of the VISS pulse counter when it is determined that the count value is not a VISS pulse; and setting the edge counter value to a second value, a third value, or a fourth value. If the value is not any of the values, after initializing the value of the VISS pulse counter, and after setting the VISS pulse determination reference time in the processing when the value of the edge counter is a third value,
And the value of the edge counter is a second value, a third value,
8. A step of initializing the edge counter after processing for initializing the count value of the VISS counter when the value is not any of the fourth values.
14. A storage medium storing a computer program for detecting a VISS signal described in 1. 11. The VISS pulse detection step according to claim 10, wherein the VISS pulse detection step sets a half of the period of the measured phase position detection signal as the VISS pulse determination reference time. A storage medium storing a computer program to be detected. 12. The inter-edge time capturing step, further comprising the step of notifying the occurrence of a buffering error when the value of the edge counter becomes a fifth value by updating. 10 or claim 1
A storage medium storing the computer program for detecting the VISS signal according to claim 1.