JP3039218B2 - Charge-coupled device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge-coupled device,
In particular, the present invention relates to a charge-coupled device in which transfer charges of two CCD registers are combined and charge detection is performed at one output unit. Such a charge-coupled device is used, for example, in a linear image sensor in which CCD registers are arranged on both sides of one pixel column.

[0002]

2. Description of the Related Art In general, in a linear image sensor, CCD registers A2 and B3 are arranged on both sides of a linearly arranged pixel row 1 as shown in FIG. The pixel group of bits (P1,
P3, P5, P7, P9,...) Signal charges (electrons; hereinafter, the signal charges are all electrons in the present specification) and even-bit pixel groups (P2, P4, P6, P8, P1).
0, ... each biphasic pulse phi ₁ signal charges) are transferred by dividing the CCD register A2 and the CCD register B3 by phi _2. It is CC that adopts such a transfer method
When two-phase transfer pulses φ ₁ and φ ₂ applied to the D register A2 and the CCD register B3 transfer signal charges of pixels (P1, P2, P3, P4,...) Of all bits by one CCD register. This is because the frequency can be reduced to a half of that in the case of FIG.

Reference numeral 18 denotes a CCD register A2 and a CCD register A2.
An output gate provided adjacent to the register B3. Signal charges transferred by the CCD register A2 and the CCD register B3 pass under the output gate 18 and are input to the adjacent signal charge detection unit 7. , P1, P2, P3, P4,..., And are converted into signal voltages and output. The signal charge detection section 7 is usually a floating diffusion layer amplifier type charge detection device. Numeral 8 is provided adjacent to the signal charge detection unit 7, discharges the signal charge of each bit which becomes unnecessary after the signal charge detection to the outside, and resets the potential of the floating diffusion layer of the signal charge detection unit 7 to a constant level. This is a reset unit for performing.

FIG. 9 is a plan view showing a state in the vicinity of a signal charge detection unit in the overall configuration diagram in FIG. In FIG. 9, components common to those in FIG. 8 are denoted by the same reference numerals. Each of the CCD register A2 and the CCD register B3 has a two-layer electrode group 2A, 2B, 3A, 3B of polycrystalline silicon as a transfer electrode.
Implantation barrier type 2 using the diffusion layer 13 as a charge transfer region
In these CCD registers, the electrode groups 2A, 2B, 3A and 3B are
The signal charges are transferred to the output gate by applying two-phase transfer pulses φ ₁ and φ ₂ from the l wiring 10.

The output gate 18 is also formed by two layers of polycrystalline silicon electrodes, and is _{supplied with} constant voltages V _OG1 and V _OG2 . Here, the transfer pulse phi ₁ to the electrode adjacent to the CCD register A2 in the output gate 18 is transferred odd bit signal charge of the pixel columns, and the output in the CCD register B3 to the signal charges of the even bits are transferred A transfer pulse φ ₂ having a phase opposite to that of the transfer pulse φ ₁ is applied to an electrode adjacent to the gate 18 for use, and the floating diffusion layer 7 a of the signal charge detection unit (floating diffusion layer amplifier type charge detection device) is alternately output from each CCD register. , And is synthesized into signal charges according to the pixel columns (P1, P2, P3, P4,...). The input signal charge is converted to a voltage signal in the floating diffusion layer 7a, and the active-side MOS transistor Q1
And (the gate bias constant voltage V _G is applied) load type MOS transistor Q2 is outputted through the source follower amplifier composed of. That is, in this case, the signal charge detection unit also functions as the signal charge synthesis unit.

Reference numeral 8a denotes a reset gate of the reset section 8 for discharging unnecessary signal charges after the signal charge detection operation from the floating diffusion layer 7a to reset the potential of the floating diffusion layer 7a to a constant level;
Is a reset drain of the reset unit 8. A reset pulse φ _R is applied to the gate 8a,
As a result, a reset operation is performed.

FIGS. 10A and 10B are cross-sectional views taken along lines AA 'and BB' in FIG. 9, respectively. FIG.
In (a) and (b), components common to the components in FIG. 9 are denoted by the same reference numerals. CC
D register A2, CCD registers n-type diffusion layer 13 and n ⁺ -type diffusion layer in which the floating diffusion layer 7a (the junction capacitance and C _FJ) constituting a charge transfer region of the B3 are both n-type silicon substrate 11 on Is formed in a p-type well 12 provided in the semiconductor device. CCD register A2, CC
Electrode group 2A, 2 which constitutes the transfer electrode of D register B3
B, 3A, 3B is formed on the n-type diffusion layer 13 through the silicon oxide film (not shown), the capacitance C _A ^1, C _A ² between each electrode and the p-type well 12, _{^{C A 3, ..., C B}} 1, C
_B ² , C _B ³ ,... Are formed. Here, p-type well 1
2 is a common G of the CCD register A2, the CCD register B3 and the floating diffusion layer 7a of the signal charge detection unit.
ND, and is connected to the external GND from the Al wiring 10 through the contact 9 and the p ⁺ -type diffusion layer 14 (the resistance between the respective parts is R ₁ , R 2 as shown in FIG. 10).
_2, R _3, and R _4).

Reference numeral 15 denotes an oxide film formed by the LOCOS method, 16 denotes a channel stop formed by doping p-type impurities at a high concentration, and 17 denotes an electrode group 2A in the surface region of the n-type diffusion layer 13. N, which are formed by implanting a p-type impurity with masks 3A and 3A as a barrier region for CCD register A2 and CCD register B3.
^- a type diffusion layer.

[0009]

In the above-described conventional linear image sensor, the odd-numbered pixels (P1, P3, P
, P7, P9,...) And even-numbered pixels (P2,
P4, P6, P8, P10,...) Have a problem that noises having different waveforms are superimposed on each other to cause output unevenness. Hereinafter, this will be described. FIG. 11 is a timing chart of transfer pulses φ ₁ and φ ₂ and a reset pulse φ _R and noises (V _G2 , V _G1 and V _G2) .
_G ) and an output signal (V _out ) waveform diagram. Odd bit pixels (P1, P3, P5, P5) from the CCD register A
7, P9, ... the signal charges of), phi ₁ is because the channel potential under the electrode 2A that phi ₁ is applied when the falls from H level to L level becomes lower than the channel potential under the output gate 18 _Is input to the floating diffusion layer 7a through the lower part of the output gate 18 and is output as a signal voltage (t _sig1 period). Similarly, pixels of even-numbered bits (P2, P4, P6, P8, P10,
Signal charge ...) is, phi ₂ passes through the lower output gate 18 when falls from H level to L level is input to the floating diffusion layer 7a, is output as the signal voltage (t _sig2 period. Normal Is t _sig1 = t _sig2 ). This is alternately repeated to obtain an output signal according to the pixel column 1. t
_R and t _F are a reset period and a reset feedthrough period of each bit, respectively.

In these series of transfer operations, FIG.
As shown in (a) and (b), the reference level (GND) point (referred to as point G) of the floating diffusion layer and the reference level (GND) point of the CCD registers A and B are connected through a resistor. , Reference point G of floating diffusion layer
It is, phi _1, the capacitance C _A ¹ in synchronization with the rise and fall of ^{_{φ 2, C A 2, C}} A 3 ..., C B 1, C B 2, C B 3 ... and R _2, R
₃ , R ₄ ... Thus, in general, φ
_1, the capacity of the CCD registers A and B phi ₂ is applied ^{_{C A 1, C A 2,}} C A 3 ... and ^{_{C B 1, C B 2,}} C B 3 ... is or manufacturing variations of the device, each electrode Are not the same due to differences in the patterns. Also, it is impossible for the pulses φ ₁ and φ _{2 to} be completely out of phase with each other. Thus, phi variation of G points by variation and phi ₂ pulse at the point G by _one pulse is not the same, as shown in FIG. 11, the potential of the point G, phi ₁ only by at a potential variation (V _G1 of G points 1) as shown by the sum of the potential change at point G (indicated by V _G2 ) due to φ ₂ only)
A waveform riding of alternately different noise for each bit (indicated by V _G). For this reason, the output waveform _Vout is obtained by superimposing this noise on the output (shown by the dotted line) of the original signal.

[0011] In the waveform indicated by the V _G, noise crest values ± G and noise width t _G is the resistance value and the p-type well, CCD register A, the capacity of the electrodes of the B or GN
Although the contact point between the D line varies depending on the distance or the like to point G, the actual measurements by trial of FAX for CCD linear image sensor of 5000-class high-speed operation of about 5~10MHz is required, C _A ^1, C _A ² , C _A ³ ,
, C _B ¹ , C _B ² , C _B ³ ,.
_1, rising an average of φ ₂ pulse, 30n the fall time
s, when the resistance value of R _{2 to} R ₄ is 200Ω and the distance from the contact point with the GND wiring to the point G is about 30 μm, the noise peak value ± G is about ± 50 mV and the noise width t _G
Was about 70 ns.

Therefore, when this device is operated at a data rate of 10 MHz, for example, a 1-bit period (= t
_R + _{t F} + t sig1,2) the signal period t _Sig1,2 about 50~60ns becomes excluding the reset period t _R and the reset feedthrough period t _F because it is 100 ns, the noise period t _G is about 70ns and from this Because of the long length, the output value is different between the odd-numbered bits and the even-numbered bits. When the output is taken on the basis of optical black (optical black reference), the noise level differs between odd-numbered pixels and even-numbered pixels, resulting in uneven output. Output unevenness due to such φ ₁ and φ ₂ pulses increases the data rate (= the signal period becomes shorter)
This becomes more prominent as a result, and this has been a problem in increasing the speed of the linear image sensor.

Therefore, it is an object of the present invention to end the noise period t _G before the end of the signal period t _sig1,2 , whereby the sampling of the signal voltage (usually the signal period (Set immediately before the end of the period t _sig1,2 ) so that noise is not superimposed on the signal voltage, and as a result, output unevenness between the odd bit and the even bit can be eliminated. It is to be.

[0014]

According to the present invention, in order to achieve the above object, two CCDs whose charge transfer regions are integrated into one charge transfer region after the leading end in the charge transfer direction. A register (2, 3); and a composite input gate (4) provided on the charge transfer area adjacent to the front end of each of the two CCD registers in the charge transfer direction and applied with a constant voltage. A signal charge combining and transferring section (5) comprising a one-stage CCD register provided adjacent to the combining input gate; and an output gate (6) provided adjacent to the signal combining and transferring section. A signal charge detector (7) provided adjacent to the output gate signal for converting a signal charge into a voltage signal, wherein a transfer pulse frequency of the signal charge combining and transferring unit is two. C
Double the transfer pulse frequency of the CD register, and
The transfer timing of the signal charge combining transfer unit
Delay from the transition point of the transfer pulse applied to the CCD register
Charge-coupled device, characterized in that Selle, is provided.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an overall configuration diagram of a first embodiment of the present invention. In FIG. 1, components denoted by the same reference numerals as those of the conventional example in FIG. 8 are the same components, and the operation is the same. In FIG. 1, 4 indicates CCD registers A2 and C
The signal charge transferred from the CD register B3 is transferred to the one-stage CC
A combining input gate for inputting to the signal charge combining / transferring section 5 composed of a D register, 6 is an output gate, and the signal charge passes from the signal charge combining / transferring section 5 to the signal charge detecting section 7 through the output gate 6. Input, converted to voltage and output. Here, the transfer electrodes (5A, 5A,
A pulse φ _L is applied to B).

FIG. 2 is a plan view showing a state near the signal charge detecting section 7 in FIG. In FIG. 2, components denoted by the same reference numerals as those in FIG. 9 indicate the same components, and the operation is the same. Has been transferred as in the conventional example by CCD registers A2 and CCD register B3, the signal charges corresponding to the odd bits and even bits of the pixel column, phi ₁ and phi ₂ are each polycrystalline falls period from H to L Consisting of two layers of silicon electrodes, constant voltages V _IG1 and V _{IG2 of} about 0 to 2 V are alternately input to the signal charge synthesizing and transferring section 5 through the gate 4 to which the synthesizing input is applied. Here, the signal charge transfer section 5 is made of polycrystalline silicon 2.
This is a single-stage CCD register having transfer electrodes 5A and 5B in layers, and has the same ion implantation barrier type as the CCD registers A2 and B3. The two-layer electrodes of the signal charge transfer section 5 are connected to the Al wiring 10 via the contacts 9, and a pulse φ _L is applied.

[0017] After the signal charges of the odd-numbered bits from the CCD register A2 is inputted to the signal charge synthesizing transfer unit 5, the pulse φ output gate 6 in the falling period of the _L (constant voltage V
_OG is applied) to the floating diffusion layer 7a of the signal charge detection unit. Similarly, after being transferred to the even bits of the signal charges even if the signal charge combining transfer unit 5 from the CCD register B3, pulse phi _L of the floating diffusion layer 7a of the signal charge detection unit through the output gate 6 in the falling period Is forwarded to

Here, in order to prevent the odd-numbered bit signal charges and the even-numbered signal charges from being mixed in the signal charge synthesizing and transferring section 5 comprising a single stage CCD register, a pulse Φ _L is applied to the CCD registers A2 and B3. Transfer pal
Scan .phi.1, twice the frequency of .phi.2, CCD register A2
After the odd-numbered bit signal charges from the CCD register B3 are transferred to the signal charge synthesizing and transferring section 5 by Φ1, before the even-numbered signal charges from the CCD register B3 are transferred to the signal charge synthesizing and transferring section 5, they are floated by the pulse Φ _L The transfer to the diffusion layer 7a may be completed. The same applies to the signal charges of the even-numbered bits from the CCD register B3, which are alternately repeated. That .phi.1, it suffices to [Phi _L falls before the start of the falling period of .phi.2.

FIGS. 3 (a) and 3 (b) show A-
It is sectional drawing of the A 'line and the BB' line. FIG. 3 (a),
In FIG. 10B, components denoted by the same reference numerals as those of the conventional example shown in FIGS. 10A and 10B indicate equivalent components. Also, reference numerals 4, 5, and 6 in FIG. 3 denote the same components with the same reference numerals in FIG. Here, one stage of C constituting the signal charge combining and transferring section 5
The CD resistor is of an ion implantation barrier type. That is, the n ⁻ -type diffusion layer 17 serving as a barrier layer is formed below the upstream transfer electrode 5B. In this embodiment, the capacitance C _L and the resistance R ₂ ′ of the signal charge synthesizing and transferring section 5 are added as compared with the conventional example, and G is a reference point of the floating diffusion layer 7a.
Although factors themselves for varying the point is increasing, the output at the time of the fall of the odd bits and even bits of the signal output are both phi _L is initiated, the effects of phi _L is exactly be the same for both , Output unevenness between odd and even bits.

Φ _L is φ ₁ because the signal charge synthesizing transfer section receives signal charges from CCD registers A and B.
And phi becomes H level before the start of the _second falling period, even more phi _1, phi desirably (phi ₁ to maintain between H level including falling period of _2, the start of the falling period of phi ₂ In the case of the timing when φ _L is changed from L to H, the signal charge temporarily remains under the combined input gate, and the signal charge amount is larger than the channel potential difference under the combined input gate determined by V _IG1 and V _IG2. If the next CC
Since part of the signal charges in the D register would flow, limiting signal charge amount becomes stricter), together with restrictions falling time of the above-mentioned phi _L, the timing of phi _L is phi _1, phi
₂ rising and falling periods include a period of H of each phi _L, it is sufficient to for the rest becomes L.

When the timing of φ _L is set in this manner, the potential fluctuation at the point G occurring during the rising and falling periods of φ ₁ and φ ₂ starts during the H period of φ _L , that is, the non-signal period of each bit. Will do. Also, reset pulse
φ _R outputs the H period from the signal charge combining and transferring section 5
Of the signal charge detection unit through the gate 6
電荷 _L from H to L at which signal charges are transferred to the diffusion layer 7a
This can be set before the falling period of this reset.
The pulse φ _R is the signal voltage separated by the signal
Timing with respect to the applied pulses phi ₁ and phi ₂ of the load transfer portion
The reset pulse φ _R is not
Rising position of phi ₁ and phi ₂ of the period, falling
Any time, that is, the start time of the potential fluctuation at the point G
It can be set. As a result, at point G
Reset pulse is applied during the period of noise occurrence due to potential fluctuation.
To as much as possible slow down the rising period of the scan φ _R
It becomes possible. For this reason, the signal period can be maintained even after the end of the noise period , and the influence of the noise on the signal can be reduced to zero in the operation of the image sensor having a data rate of about 10 MHz, for example. It can be significantly reduced as compared with the above. The above situation is shown in the timing chart of FIG.

In FIG. 4, V _G is a CCD register A,
This is a potential variation at the point G due to the B signal charge transfer pulses φ ₁ and φ ₂ , which is the same as that of the conventional example shown in FIG. V _G ′ is a potential variation at the point G due to the influence of the pulse φ _L applied to the signal charge combining and transferring section provided according to the present invention. Therefore, point G is subjected to a potential fluctuation obtained by combining these two. Here, noise and 'peak value ± G of noise in the' V _G width t _G 'capacity by at most two electrode C _L (about 0.5 pF) and resistor R ₂ of the p-type well'
Because due (200 [Omega about), smaller than the peak value ± G and noise width t _G in V _G, the V _G 1 /
It is about five.

The effect of this noise on the output _Vout is exactly the same for odd and even bits, and therefore does not cause uneven output of odd and even bits.
Meanwhile, the period in which the V _G in signal period affects the output V _out is non-signal period (reset period or the reset feedthrough period) of the duration of generation start phi _L is H noise, that is, the output V _out The noise width t _G
Thus, only the period (t _G −t _d ) obtained by subtracting the period t _d from the change point of φ ₁ and φ _{2 to} the start of the fall of φ _L is obtained. Therefore, in the case of the above-described conventional example (in the case of operation at a data rate of 10 MHz), t _G was about 70 ns, so if t _d was set to 30 ns (t _G −t
_d ) is 40 ns, and the signal period is 50 ns as in the conventional example.
If ～60Ns, as shown in V _out in FIG. 4, the effect of V _G is at the end of the signal period has disappeared, as a result, V _G is an odd number, the cause of the output unevenness of the even bits (In the figure, the dotted line of V _out indicates an ideal waveform when G and G ′ = 0).

Next, a second embodiment of the present invention will be described with reference to FIGS. This embodiment is different from the first embodiment in that the transfer electrode of the signal charge synthesizing transfer section is connected to the gate of the reset section. That is, the second embodiment differs from the first embodiment in that the pulse φ _L applied to the signal charge combining transfer unit and the pulse φ _R applied to the reset unit are shared. FIG. 5 shows a timing chart of the operation.
The transfer state of signal charge at each time of ₁ ~t _7, FIG. 2
6 and 7 are channel potential diagrams under each electrode in a cross section taken along line AA 'and line BB'. FIG.
7, the same reference numerals as those in FIGS. 2A and 2B denote the same components.

[0025] ^{_{Q A i (i = 1,2,}} ...) the signal charge from the CCD register ^{_{A, Q B j (j =}} 1,2, ...) is a signal charge from the CCD register B. Normally, the floating diffusion layer is not depleted, and is set to the potential V _{DD of the} reset drain during the reset operation (when φ _R is H) as shown in FIGS. At t ₁ , Q _A ⁱ and Q
_A ^{i + 1} is the lower electrode 2a is applied the phi _1, also Q _B ⁱ is phi ₂
Is accumulated under the electrode 3a to which the voltage is applied. At t ₂ , when φ _L (= φ _R ) becomes H, no charge is transferred, but a potential well is formed below the transfer electrode of the signal charge synthesis transfer section 5 and the floating diffusion layer is reset.

[0026] In t _3, when phi ₁ is L, phi ₂ is H, Q _A ⁱ is transferred to the potential well of the signal charge synthesis transfer unit,
Q _A ^{i + 1} is below the applied electrode 2a of φ ₂ and Q _B ⁱ ,
Q _B ^{i + 1} are transferred under the electrodes 3a applied in phi _2. t
In _4, when φ _L (= φ _R) is L, CCD registers A, transfer the B but not performed, the charge Q _A ⁱ accumulated in the signal charge synthesizing transfer unit 5, transferred to the floating diffusion layer Is done. In _{t 5, φ L (= φ} R) becomes H, but is not carried out the transfer of similar charge to that of t2, the potential wells are formed under the transfer electrodes of the signal charge combining transfer unit 5, a floating diffusion The layer is reset. In t _6, phi ₁ is H, when phi ₂ becomes L, Q _B ⁱ is transferred to the potential well of the signal charge synthesis transfer ^{_{unit, Q A i + 1, Q}} A i + 2 is phi ₁
The lower electrode 2a is applied, also, Q _B ^{i + 1} are transferred under the electrodes 3a applied for phi _1. In t _7, returns to the state of t _1, the same operation is repeated later.

In this embodiment, attention must be paid to the following in order to make φ _L and φ _R common. That is, since the transfer of the signal charge from the signal charge synthesis transfer unit to the floating diffusion layer and the timing at which the reset transistor is turned off are the same, in order to prevent a part of the signal charge from flowing to the reset drain, FIG. Output gate 6 shown in FIG.
The difference in potential vQ _A ⁱ and vQ _B ^j when the signal charges are input to the channel potential v _OG and the signal charge combining transfer unit 5 below, namely (vQ _A ⁱ -v _OG) and (vQ _B ^j -v _OG ) Is the difference between the potential V _{DD of the} reset drain and the channel potential v _RH under the reset gate 8a when φ _L (= φ _R ) becomes H (v
_RH -V _DD) always respect _{(v RH -V DD) <(} vQ A i -v OG) and _{(v RH -V DD) <(} vQ B j -v OG) ( all i, for j, That is, it must be designed so as to be (for the minimum value of vQ _A ⁱ and vQ _B ^j ). When φ _L (= φ _R ) becomes L, the speed at which the potential under the gate 8a of the reset unit decreases and the speed at which the potential under the transfer electrode of the signal charge synthesizing transfer unit 5 decreases are expected to be substantially the same. by setting so that, when Q _a ⁱ to (Q _B ^j) passes under the output gate 6, because it is possible to separate the reset drain from the floating diffusion layer.

Although the present embodiment has the above-described design limitations, it is possible to reduce the number of input clocks to the device by one as compared with the first embodiment, and also to provide a reset feed which is a non-signal period. the through period t _F can be 0, since it is possible to take longer correspondingly signal period, it is possible to reduce the influence of the more V _G. Alternatively, the period of one bit can be shortened, and the data rate can be easily increased accordingly.

While the preferred embodiment has been described above,
The present invention is not limited to these embodiments, and various changes can be made within the gist of the present invention described in the claims. For example, in the embodiment, 2
The phase drive type buried channel type charge coupled device has been described, but this can be changed to a drive type other than two-phase type or a surface channel type. Further, the present invention can be applied not only to a linear image sensor but also to other devices.

[0030]

As described above, the charge-coupled device of the present invention combines the signal charges of the two CCD registers to obtain one.
In the case where electric charges are detected by two electric charge detection units, both C
A combining input gate and a signal charge combining / transferring unit including a one-stage CCD register are provided at the leading end of the CD register in the charge transfer direction. The combined signal charge is temporarily stored in the signal charge combining / transferring unit, and then the output gate is provided. Is transferred to the floating diffusion layer of the charge detection unit through
According to the present invention, the transfer timing of the signal charge from the signal charge synthesis transfer section to the signal charge detection section is delayed from the transition points (H → L and L → H) of the transfer pulses applied to the two CCD registers. In addition, the timing of the reset pulse can be delayed with respect to the timing of the transfer pulse of both CCD registers as compared with the related art. As a result, the entire signal period can be delayed as compared with the related art. Therefore, the signal period can be terminated after the level of the noise based on the transfer pulse generated at the transition point of the transfer pulse becomes sufficiently low, so that the charge-coupled device driven by the high-speed transfer pulse is also caused by the transfer pulse. As a result, the noise level superimposed on the output signal can be significantly reduced. Therefore, as a result, the output unevenness between the odd-numbered bits and the even-numbered bits in the output signal due to the transfer clock noise can be greatly reduced. For example, when a 5000-bit class linear image sensor is driven at a high data rate of about 10 MHz. Thus, it is possible to prevent almost even output unevenness.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing the entire configuration of a first embodiment of the present invention.

FIG. 2 is a plan view showing a state near a signal charge detection unit according to the first embodiment of the present invention.

FIG. 3 is a sectional view taken along line AA ′ and line BB ′ in FIG. 2;

FIG. 4 is a timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 5 is a timing chart for explaining a second embodiment of the present invention.

FIG. 6 is a potential distribution diagram for explaining a second embodiment of the present invention.

FIG. 7 is a potential distribution diagram for explaining a second embodiment of the present invention.

FIG. 8 is a schematic plan view showing the entire configuration of a conventional example.

FIG. 9 is a plan view showing a state in the vicinity of a signal charge detection unit in a conventional example.

FIG. 10 is a sectional view taken along lines AA ′ and BB ′ in FIG. 9;

FIG. 11 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Pixel row 2 CCD register A 2A, 2B electrode 3 CCD register B 3A, 3B electrode 4 Synthesis input gate 5 Signal charge synthesis transfer part 5A, 5B transfer electrode 6 Output gate 7 Signal charge detection part 7a Floating diffusion layer 8 Reset Part 8a reset gate 8b reset drain 9 contact 10 Al wiring 11 n-type silicon substrate 12 p-type well 13 n-type diffusion layer 14 p ⁺ -type diffusion layer 15 oxide film by LOCOS method 16 channel stop 17 n ^- type diffusion layer 18 for output Gate Q1 Active MOS transistor of signal charge detector Q2 Load MOS transistor of signal charge detector

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/762 H01L 21/339 H01L 27/148

Claims (5)

(57) [Claims] 1. Two CCD registers, each of which is integrated into one charge transfer region after a leading end in the charge transfer direction, and a leading end of each of the two CCD registers in the charge transfer direction. And a signal charge combining / transferring unit comprising a combined input gate provided on the charge transfer region adjacent to the unit and to which a constant voltage is applied, and a one-stage CCD register provided adjacent to the combined input gate. When,
A charge coupled device comprising: an output gate provided adjacent to the signal charge combining / transferring unit; and a signal charge detecting unit provided adjacent to the output gate and converting a signal charge into a voltage signal. Wherein the transfer pulse frequency of the signal charge synthesis transfer section is twice the transfer pulse frequency of the two CCD registers, and the transfer timing of the signal charge synthesis transfer section is set to be equal to the two CCD registers. A charge-coupled device, wherein the charge-coupled device is delayed from a change point of a transfer pulse applied to the charge-coupled device. 2. The method according to claim 1, wherein the two CCD registers are formed with one pixel row interposed therebetween, and each CCD register transfers a signal charge generated in the pixel row. Item 2. The charge-coupled device according to Item 1. 3. The transfer pulse of the signal charge synthesizing transfer section ,
Rising after the timing of the rise of the reset pulse, a charge coupled device according to claim 1, characterized in that falls after the fall timing. 4. The charge-coupled device according to claim 1, wherein said signal charge synthesizing transfer section is in a charge holding state when transfer pulses of said two CCD registers are in a transition state. 5. The transfer pulse of the signal charge synthesis transfer section,
2. The charge-coupled device according to claim 1, wherein a reset pulse for resetting a potential of the signal charge detection unit has the same phase and the same timing.