JP2509666B2 - Charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a charge transfer device having a plurality of CCD registers.

(Prior Art) A charge transfer device having a CCD register is widely used for a delay line and an image sensor.

If there are multiple CCD registers, the multiple CCDs
In some cases, it is necessary to have a structure in which the signal charges transferred from the registers are integrated and read by one output unit. A conventional charge transfer device will be described with reference to FIG. 5 showing its structure. The photodiode 1 is irradiated with light to generate a signal current, and the CCD registers 2 and 3 accumulate the signal charges generated in the photodiode 1 and transfer them to the output gate 12. The output gate 12 sequentially outputs the signal charges transferred from the CCD registers 2 and 3 to the floating diffusion layer 11. The floating diffusion layer 11 corresponds to the storage part, and the output gate 12
The signal charges are sequentially received from and accumulated. The accumulated signal charges are sequentially read by the source follower circuit 7. The reset gate 6 discharges excess charges accumulated in the floating diffusion layer 11 before sequentially receiving the signal charges, and sets the floating diffusion layer 11 to a constant voltage.

A partial enlarged view of the output section I of this device is shown in FIG.
Shown in the figure and described. CCD registers 2 and 3 are transfer stage 2 respectively
a, 2b, 2c, 2d, ... And transfer stages 3a, 3b, 3c, 3d ,. The clock pulse ₁ is applied to the transfer stages 2b, 2d, ... And the transfer stages 3a, 3c ,.
b, 3d, ... clock pulses phi ₂ of the clock pulses phi ₁ opposite phase is applied to. Based on the applied clock pulse, each transfer stage accumulates the signal charges transferred from one adjacent transfer stage and transfers the signal charges to the other adjacent transfer stage. For example, the transfer stage 2c transfers and accumulates the signal charge from the transfer stage 2d, and then transfers the signal charge to the transfer stage 2b.
The signal charges transferred from 2c are transferred to the transfer stage 2a. Each transfer stage has a potential barrier that prevents the backflow of signal charges. The signal charges transferred from the respective transfer stages are alternately transferred to the output gate 12 from the transfer stages 2a and 3a corresponding to the final stage, and further output to the floating diffusion layer 11.
As a result, the signal charges transferred from the CCD registers 2 and 3 are alternately flown into the floating diffusion layer 11. The floating diffusion layer 11 is given a reset pulse RS from the reset gate 6 before each signal charge is flowed in, and discharges the excess charge accumulated in the floating diffusion layer 11,
It is set to a constant voltage. The signal charges flowing into the floating diffusion layer 11 and accumulated therein are sequentially read by the source follower circuit 7. Source follower circuit 7 is FET7a, FET7b
And performs impedance conversion.

The pulse timings of the output signal output from the floating diffusion layer 11, the clock pulse φ ₁ , the clock pulse φ ₂ , and the reset pulse RS will be described with reference to the time chart of FIG. 7. Before the signal charges are transferred, the reset pulse RS is applied to the floating diffusion layer 11 from the reset gate 6, and the potential becomes the set potential E ₀ . When the reset pulse RS becomes high level or low level, the floating diffusion layer 11 is coupled to the reset gate 6, and thus induced noise is generated and becomes the potential E ₀ ′. Thereafter, of the transfer stages 2a and 3a, which are the final transfer stages of the CCD registers 2 and 3, the signal charge is transferred from one of the transfer stages in which the applied clock pulse is at the low level, and the output gate 12 is transferred. It passes and is accumulated in the floating diffusion layer 11. In example FIG. 7, from the transfer stage 3a of clock pulses phi ₁ is applied, the potential of the floating diffusion layer when the clock pulses phi ₁ becomes the low level signal charge is transferred is E _11. After this, reset pulse R
S is given and the potential of the floating diffusion layer 11 becomes E ₀ , and further becomes E ₀ ′ due to the noise of the reset pulse RS. Then from the transfer stage 2a clock pulse phi ₂ is applied, when the clock pulse phi ₂ becomes low level signal charge is transferred, the potential of the floating diffusion layer 11 is E _12. Similarly, the signal charge is transferred from the transfer stage 3a and the potential of the floating diffusion layer 11 is changed.
It becomes E ₁₃ , then the signal charges are transferred from the transfer stage 2a and the potential of the floating diffusion layer 11 becomes E ₁₄ .

(Problems to be Solved by the Invention) With respect to such a charge transfer device, there is an increasing need to improve the sensitivity and reduce the signal charge amount when used as an image sensor. For this purpose, it is necessary to reduce the charge storage capacity of the floating diffusion layer 11 and increase the charge-voltage conversion gain.

However, the portion of the floating diffusion layer 11 connected to the output gate 12 needs to correspond to the area of the output gate 12 separately connected to the transfer stages 2a and 3a. Therefore, the area cannot be reduced, and as a result, the floating diffusion layer 11
There is a problem that there is a limit to reduce the storage capacity of the.

In view of the above circumstances, it is an object of the present invention to provide a charge transfer device capable of reducing the charge storage capacity of the floating diffusion layer 11 and improving the charge-voltage conversion gain.

[Structure of Invention]

(Means for Solving Problems) The above object is to integrate a CCD register unit having a plurality of CCD registers for transferring signal charges in a transfer path surrounded by an element isolation region and each transfer path of the CCD register. In the integrated part, the convex element isolation regions are formed so as to bite into the areas where the transfer paths meet.
After being given the signal charges transferred from the registers, respectively, having an integrating section for outputting and a plurality of transfer electrodes, after being given and transferring the signal charges outputted from the integrating section,
This is achieved by a charge transfer device including an output transfer stage and an accumulation unit that receives and accumulates the signal charge output from the transfer stage.

(Function) The signal charges respectively transferred from the plurality of CCD registers are output to the transfer stage through the transfer path integrated by the integration unit. A plurality of transfer electrodes are provided in the transfer stage, and after the given signal charges are transferred, they are output to and accumulated in the accumulating unit. The area of the output gate can be made smaller than that in the case where there is no integration unit because the transfer paths of the plurality of CCD registers are once integrated in the integration unit. As a result, the area of the portion of the storage section facing the output gate can be made smaller than that in the case where the integrated section is not provided, so that the charge storage capacity of the storage section can be reduced. Further, since the transfer stage having a plurality of transfer electrodes is provided between the integration section and the output gate, the distance between the CCD register and the storage section is increased. As a result, it is possible to prevent the noise generated when the signal charge is transferred in the CCD register from causing induced noise in the storage section. Further, since the convex element isolation regions are formed so as to bite into the merged portions of the transfer paths, the signal charges sent from the respective transfer paths are prevented from flowing back.

(Example) Hereinafter, the present invention will be described in detail based on illustrated examples.

First, a charge transfer device according to an embodiment of the present invention will be described with reference to FIG. 1 showing the structure thereof. The same components as those of the conventional charge transfer device shown in FIG. The difference from the conventional case is that a transfer gate 4 corresponding to an integration unit is provided between the output gate 5 and the CCD registers 2 and 3. As a result, the respective areas of the output gate 5 and the conventional output gate 12 and the charge storage capacities of the floating diffusion layer 8 and the conventional floating diffusion layer 11 are different. The output section II in the charge transfer device shown in FIG. 1 will be described with reference to FIG. 2 which is a partially enlarged view thereof. The same parts as those of the output unit II and the conventional charge transfer device shown in FIG. Here, the CCD register 2 is provided with an element isolation region 22b and a transfer path 22a which is surrounded by the element isolation region 22b and sequentially transfers signal charges. Similarly, the CCD register 3 includes an element isolation region 23b and a transfer path 23a.
Are provided. Unlike the conventional case, a transfer gate 4 is provided between the transfer stages 2a and 3a of the CCD registers 2 and 3 and the floating diffusion layer 8, and a clock pulse φ _T is applied to the transfer gate 4. In a region where the transfer gate 4 is formed, a convex element isolation region 34 is formed so as to bite into a portion where the transfer route 22a of the CCD register 2 and the transfer route 23a of the CCD register 3 meet.

As in the conventional case, each transfer stage 2b, 2c, 2d, ... And transfer stage 3b, based on the applied clock pulse.
Signal charges are transferred from 3c, 3d, ... And transferred to respective transfer stages 2a and 3a corresponding to the final stage. Then, based on the clock pulse φ _T , the transfer gate 4 alternately transfers one of the signal charges stored in the transfer stage 2a and the signal charge stored in the transfer stage 3a. Here, transfer gate 4
The element isolation region 34 is formed in the region in which is formed as described above. Therefore, it is possible to prevent the signal charges sent from the transfer path 22a of the CCD register 2 or the transfer path 23a of the CCD register 3 from flowing back to the transfer path 23a or 22a and mixing the signal charges. The output gate 5 outputs the signal charges transferred from the transfer gate 4 to the floating diffusion layer 8.
As a result, the signal charges transferred from the CCD registers 2 and 3 are alternately flown into the floating diffusion layer 8. After that, the signal charges accumulated in the floating diffusion layer 8 are sequentially read by the source follower circuit 7.

Next, FIG. 3, which is a time chart, shows the output signals output from the floating diffusion layer 8 and the respective pulse timings of the clock pulse φ ₁ , the clock pulse φ ₂ , the transfer pulse φ _T , and the reset pulse RS. Refer to and explain. Compared with FIG. 7 which is a time chart in the conventional case, a transfer pulse φ _T is newly added. Before the signal charge is transferred, the floating diffusion layer 8 is reset by the reset gate 6
Is applied more reset pulse RS, the potential is set potential E ₀
Becomes When the reset pulse RS changes from the high level to the low level, the floating diffusion layer 8 is coupled to the reset gate 6, so that induced noise is generated and the potential becomes E ₀ ′. After this, the transfer stage 2 of the final transfer stage of each of the CCD registers 2 and 3
Signal charges are transferred to the transfer gate 4 from one of the transfer stages in which the applied clock pulse of a and 3a is at the low level while the transfer pulse φ _T is at the high level. Next, the transfer pulse φ _T becomes low level, and the signal charge thereof passes through the output gate 5 and is accumulated in the floating diffusion layer 8. In example FIG. 3, the transfer stage 3a of clock pulses phi ₁ is applied, when the clock pulse phi ₁ is low level, the signal charge transfer gate 4 a transfer pulse phi _T of a high level is applied Transferred. When the transfer pulse φ _T becomes low level, signal charges are transferred from the transfer gate 4 to the floating diffusion layer 8 through the output gate 5, and the potential of the floating diffusion layer 8 becomes E ₁ . After that, the reset pulse RS is applied and the potential of the floating diffusion layer 8 becomes E ₀ , and becomes E ₀ ′ due to the noise of the reset pulse RS. Then from the transfer stage 2a clock pulse phi ₂ is applied, when the clock pulse phi ₂ is at low level, the signal charge is transferred to the transfer gate 4 a transfer pulse phi _T of a high level is applied. When the transfer pulse φ _T becomes low level, the signal charge is transferred from the transfer gate 4 to the floating diffusion layer 8 through the output gate 5, and the potential of the floating diffusion layer 8 becomes E ₂ .
Similarly, the signal charge is transferred from the transfer stage 3a and the potential of the floating diffusion layer 8 becomes E ₃ , and then the signal charge is transferred from the transfer stage 2a and the potential of the floating diffusion layer 8 becomes E _4. . In this way, as in the conventional case, the signal charges are sequentially transferred to the floating diffusion layer 8, accumulated, and output to the source follower circuit 7.

Here, the area of the output gate 5 is smaller than that of the conventional output gate 12. This is because the transfer paths of the signal charges of the two CCD registers 2 and 3 are once integrated by the transfer gate 4 corresponding to the integration section. As a result, the floating diffusion layer 8
Since the area of the portion facing the output gate 5 is smaller than the area of the conventional floating diffusion layer 11, the charge storage capacity is small. Therefore, the charge-voltage conversion gain when the signal charge is output from the floating diffusion layer 8 to the source follower circuit 7 is increased, and the sensitivity is improved. Furthermore, since the amount of signal charges to be handled can be reduced, the CCD register can be downsized.

Although this embodiment has two CCD registers, the same effect can be obtained even if the number of CCD registers is three or more. Further, the clock pulse applied to each transfer stage of the CCD register may have three or more phases. Although the floating diffusion layer is used as the storage portion, if it has a function of storing electric charges, such as a floating gate structure,
Other structures can be used.

Further, in this embodiment, as shown in FIG. 2, the transfer gate 4 and the output gate 5 corresponding to the integrated portion are adjacent to each other, but they may not be adjacent to each other. An example of such a case will be described as another embodiment with reference to FIG. 4 in which an output section is enlarged. The same elements as those of the embodiment shown in FIG. A transfer stage 9 composed of a plurality of transfer electrodes is provided between the transfer gate 4 and the output gate 5. As described above, the configuration may be such that the integration unit and the output gate are not adjacent to each other and the signal charges are transferred through the transfer stage. According to this embodiment, the presence of the transfer stage 9 increases the distance between the CCD register 2 and the 3 floating diffusion layer 8. Therefore, induced noise is generated in the floating diffusion layer 8 under the influence of the clock pulses φ ₁ and φ ₂ applied to the transfer stages 2a, 2b, ... And the transfer stages 3a, 3b, ... Of the CCD registers 2 and 3, respectively. Can be suppressed.

〔The invention's effect〕

As described above, in the charge transfer device of the present invention, the signal charges transferred from the plurality of CCD registers are integrated in the transfer path by the integration unit and then accumulated and output to the accumulation unit via the output gate. Therefore, the area of the storage section facing the output gate is small, and the charge storage capacity is small. As a result, the charge-voltage conversion gain when the signal charges are output from the storage unit and converted into a voltage is increased, and the sensitivity is improved.

Further, since the transfer stage having a plurality of transfer charges is provided between the integration unit and the output gate, the distance between the CCD register and the storage unit is increased, and the transfer of signal charge in the CCD register is increased. It is possible to prevent the noise generated at this time from causing induced noise in the storage unit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a charge transfer device according to an embodiment of the present invention, FIG. 2 is a partially enlarged configuration diagram of a charge transfer device according to an embodiment of the present invention, and FIG. 3 is a charge according to an embodiment of the present invention. FIG. 4 is a partially enlarged block diagram of a charge transfer device according to another embodiment of the present invention, FIG. 5 is a block diagram of a conventional charge transfer device, and FIG. 6 is a conventional charge transfer device. FIG. 7 is a partially enlarged configuration diagram of the device, and FIG. 7 is a time chart of signals in the conventional charge transfer device. 1 ... Photodiode, 2, 3 ... CCD register, 2a, 2b, 2c, 2
d, 3a, 3b, 3c, 3d ... Transfer stage, 4 ... Transfer gate, 5 ... Output gate, 6 ... Reset gate, 7 ... Source follower circuit,
7a ... FET, 7b ... FET, 8 ... Floating diffusion layer, 9 ... Transfer stage, 11 ...
Floating diffusion layer, 12 ... Output gate, 22a, 23a, 32a, 33a ... Transfer path, 22b, 23b, 24, 32b, 33b, 34 ... Element isolation region.

Claims (2)

(57) [Claims] 1. A charge transfer device for transferring a signal charge, wherein the signal charge is transferred in a transfer path surrounded by an element isolation region.
A CCD register unit having a plurality of CCD registers, and an integration unit that integrates each transfer path of the CCD register, and a convex element isolation region is formed so as to bite into a location where each transfer path merges. In addition, the integrated circuit is provided with the signal charges transferred from the CCD register and then output, and the integrated unit has a plurality of transfer electrodes. The signal charges output from the integrated unit are supplied and transferred. After that, a charge transfer device comprising: a transfer stage for outputting and a storage unit for receiving and storing the signal charge output from the transfer stage. 2. A CCD register unit comprising: a first clock pulse and a second clock pulse which are in a reverse phase relationship; and a transfer pulse having a frequency twice that of the first and second clock pulses. Has a first register and a second register each having a plurality of transfer electrodes, and pulses applied to adjacent ones of the transfer electrodes of the first register have opposite phases. Either one of the first and second clock pulses is applied to each of the transfer electrodes of the second register, and the pulses applied to the adjacent transfer electrodes have opposite phases and are opposed to each other. One of the first clock pulse and the second clock pulse is applied so as to have a phase opposite to that of the pulse applied to the transfer electrode of the first register, and the transfer pulse is applied to the integration unit. The charge transfer device according to claim 1, wherein the charge transfer device comprises: