JP3033862B2 - Switching element malfunction prevention circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching element malfunction prevention circuit.

[0002]

2. Description of the Related Art Conventionally, for example, when a failure occurs between a drain and a gate of a field effect transistor (FET) which is a switching element in a short mode, a drive signal generating element for driving and controlling the FET is prevented from being broken.
If a diode is connected in a direction that prevents current from flowing from the gate of the FET to the drive signal generating element, or if the switching element is a bipolar transistor, a current flows from the base of the transistor to the drive signal generating element. The applicant of the present invention has applied for a technique of connecting in a direction that prevents the
-59519).

[0003]

However, FETs
Then, since the diode is connected in the direction to prevent the current from flowing from the gate to the drive signal generating element, it is a short time if a voltage is applied to the drain of the FET when the FET is normally off. In addition, a current flows from the gate to the source via the floating capacitance between the drain and the gate of the FET, and there is a problem of a malfunction in which the FET is turned on for a moment. or,
Similarly, when a voltage is applied to the collector of a transistor when the transistor is off, a current flows to the base and emitter via the stray capacitance between the collector and the base of the transistor, causing a problem that the transistor turns on momentarily. was there.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and prevents the flow of electricity from a switching element to an on / off drive signal generation element to prevent damage to the on / off drive signal generation element. At the same time, an object of the present invention is to prevent the switching element from being turned on due to a malfunction even when an external voltage is applied to the switching element when the switching element is in an off state.

[0005]

In order to achieve the above object, a malfunction preventing circuit for a switching element according to the present invention comprises a switching element, a drive signal generating element for generating a signal for driving the switching element on and off, and a switching element. A rectifying element provided between the element and the drive signal generating element in a direction to prevent a flow of power from the switching element to the drive signal generating element; and the rectifying element between the switching element and the drive signal generating element. And a storage element provided in parallel.

[0006]

According to the switching element malfunction prevention circuit of the present invention having the above configuration, the switching element is driven by the on / off signal from the drive signal generating element. However, if the switching element fails, the switching element becomes high. Even if a voltage is applied, the flow of electricity to the drive signal generating element is prevented by the rectifying element, while the stray capacitance that remains when a high voltage is applied to the switching element when the switching element is off. The charge flows to the storage element, and the switching element does not turn on carelessly.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a piezoelectric element drive circuit according to one embodiment of the present invention. In this piezoelectric element driving circuit, a DC power supply E, a transistor TR1, and a coil L are connected in series to a piezoelectric element CP, and these constitute a charging circuit for the piezoelectric element CP. On the other hand, the piezoelectric element CP, the coil L and the field effect transistor FET
Are connected in series, and these constitute a discharge circuit of the piezoelectric element Cp.

The base of the transistor TR1 is connected via a resistor R1 from a transistor TR3 for turning it on and off, and the base of the transistor TR3 is further connected to a transistor drive control circuit 60 for driving it on and off. The field effect transistor FE
The gate side of T is connected to the drive control circuit 60 via a diode D1. The diode D1 is connected in such a direction as to block the flow of electricity from the gate of the FET to the drive control circuit 60. Further, a capacitor C1 is connected between the gate of the FET and the drive control circuit 60 in parallel with the diode D1.

At both ends of the coil L, diodes D3 and D4 are connected in a direction to prevent a current from flowing from the positive electrode of the DC power supply E, and diodes D5 and D6 flow a current to the cathode of the DC power supply E. Connected in a direction that prevents

Next, the operation of the piezoelectric element driving circuit will be described with reference to FIG. At time T1, it is assumed that the drive start voltage V1 is applied to the transistor TR3 by the input signal from the transistor drive control circuit 60, and the transistor TR1 is turned on. Then, a current flows from the DC power supply E to the piezoelectric element CP through the transistor TR1 and the coil L, and the piezoelectric element CP is charged. On the other hand, when the voltage V1 goes low at time T2, the transistor TR1 is turned off and the charging of the piezoelectric element Cp ends.

Next, at time T3, the transistor FET
When the driving start voltage V2 is applied to the FET and the FET is turned on, the electric charge accumulated in the piezoelectric element Cp is transferred to the coil L and the FET.
And discharge of the piezoelectric element Cp is performed. When the voltage V2 becomes low at time T4, the FET is turned off, the discharge of the piezoelectric element Cp ends, and the power stored in the coil L returns to the power supply. In such a state, conventionally, as shown in FIG.
At the moment when R1 is turned on, a current flows to the source of the FET via the stray capacitance between the drain and the gate of the FET, and the FET is turned on for a short time. Electric current flows. In the present invention, the FET and the transistor drive control circuit 6
Since the capacitor C1 is provided between the FET and the FET, the current flowing through the stray capacitance between the drain and the gate of the FET is V2
Is at a low level, the current flows to the drive control circuit 60, the FET is not turned on by the current, and no through current flows. The current through this stray capacitance is so small that it does not destroy the control circuit.

FIG. 4 shows another embodiment of the present invention. In this embodiment, a bipolar transistor TR4 is used in place of the FET shown in FIG. Practically, the operation and effect of the FET and the TR4 remain unchanged.

[0013]

As is apparent from the above description, according to the present invention, a rectifying element is provided between a switching element and its on / off driving signal generating element, and electric power is supplied from the switching element to the driving signal generating element. While the switching element is turned off, even if a high voltage is applied in the off state of the switching element, the charge remaining there is caused to flow to the storage element provided in parallel with the rectifying element, so that the switching element is inadvertently turned on. Such a malfunction is avoided, and a stable switching circuit is formed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a piezoelectric element driving circuit according to a specific embodiment of the present invention.

FIG. 2 is a voltage and current waveform diagram for explaining the operation of the piezoelectric element drive circuit.

FIG. 3 is a voltage and current waveform diagram of a conventional piezoelectric element drive circuit.

FIG. 4 is a piezoelectric element drive circuit diagram according to another embodiment of the present invention.

[Explanation of symbols]

 FET Field-effect transistor 60 Drive control circuit (including drive signal generation element) D1 Rectifier element C1 Storage element TR4 Bipolar transistor

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-270418 (JP, A) JP-A-2-106166 (JP, A) JP-A-3-18118 (JP, A) JP-A-5-118 57918 (JP, A) JP-A-62-295512 (JP, A) JP-A-3-78313 (JP, A) JP-A-5-5458 (JP, U) JP-A-62-193332 (JP, U) JP-B-54-44586 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 17/00-17/693

Claims (1)

(57) [Claims] A switching element; a driving signal generating element for generating a signal for driving the switching element on and off; and a power supply from the switching element to the driving signal generating element between the switching element and the driving signal generating element. A malfunction preventing circuit for a switching element, comprising: a rectifying element provided to block a flow; and a power storage element provided in parallel with the rectifying element between the switching element and a drive signal generating element.