JP3032218B2 - Processor unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor unit that performs image processing for digitally processing a two-dimensional image, and in particular, processes one pixel of an image in correspondence with one bit of digital data. This is related to a bit map method.

[Conventional technology]

As one of the techniques for digitally processing an image, there is a bit map method in which one pixel of the image is processed in correspondence with one bit of digital data.

FIG. 9 is a diagram for explaining the principle of the conventional bit map system. In the image G, an image composed of 40 pixels (40 bits) in each of the horizontal (X) direction and the vertical (Y) direction is divided into sections D. And performs data processing in units of 8 bits (1 byte) continuous in the X direction.

In this processing method, in order to extract a line segment in the Y direction, a part of the line segment in the X direction including bits constituting the line segment in the Y direction to be processed is held in a register, and the line segment in the Y direction is extracted from the register. Is selected. By repeating this process a plurality of times, bits forming a line segment in the Y direction are extracted from a plurality of line segments in the X direction. When writing a line segment in the Y direction, a part of the line segment in the X direction including bits forming the line segment is held in a register, and an operation is performed on only the bits forming the line segment in the Y direction. A part of the line segment in the X direction is written back. Furthermore, when reversing the direction of a line segment,
The contents of the line to be inverted are stored in a register, and the bits are exchanged using a rotation instruction or a carry bit.

[Problems to be solved by the invention]

According to the processing method described above, the relationship between the address and the data is constituted by line segments whose bit length is the width of the bit map section in the X direction, so that the line segments in the X direction are continuous on the memory. Pixels forming a line segment in the Y direction are discrete. Therefore, the processing method differs between processing a line segment in the X direction and processing a line segment in the Y direction. When processing a line segment in the Y direction, the processing must be repeated by the number of bits of the register. And spend a lot of time.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a processor unit for performing image processing capable of similarly processing a line segment in the X direction and a line segment in the Y direction.

[Means for solving the problem]

The present invention provides a processor unit which can specify an address in the X and Y directions inside the processor unit, accesses an image memory composed of M × M bits in units of M bits, and performs image processing. An X-direction demultiplexer that specifies a column number in the X direction of the image memory; a Y-direction demultiplexer that specifies a row number in the Y direction of the image memory; and either the X-direction or the Y-direction demultiplexer is selected. A demultiplexer selecting means, and an inverting unit for inverting a bit string in the MSB direction of the M-bit data input or output into a bit string in the LSB direction, wherein the input and output stages to the image memory respectively comprise: Selecting the demultiplexer for an address signal instructing the directional and Y-directional demultiplexers No. be added, thereby inputting the added signal to the demultiplexer selection means.

[Operation] The additional signal added to the address signal is inputted to the demultiplexer selecting means to select either the X-direction demultiplexer or the Y-direction demultiplexer, and the address signal is inputted to the X-direction and Y-direction demultiplexer. Then, the column or row number of the image memory composed of M × M bits is decoded and designated.

Therefore, image data in units of M bits is represented by M
A column and a row can be accessed at the same speed in the image memory composed of × M bits, and the image data is accessed to the image memory via the inversion section, so that the left / right inversion and the up / down inversion of the data can be easily performed. Can be done.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of image processing according to the present invention, and shows an example in which the present invention is applied to a processor unit.

In FIG. 1, a processor unit 1 has a two-dimensional register 2 which can be addressed in a two-dimensional direction, and the input and output of this register 2 are connected to first and second inversion units 3a and 3b having the same configuration. ing.

The output of the transfer buffer 5, the operation unit 6, and the input / output buffer 7 are respectively connected to the input of the inversion unit 3a via the internal bus 4, and the output of the inversion unit 3b is connected to the transfer buffer 5, via the internal bus 8. The arithmetic unit 6 and the input / output buffer 7 are connected to respective inputs. The input / output buffer 7 transfers data between the processor unit 1 and other units, and is connected to other units via a system bus 9.

The control unit 10 is connected to the internal bus 4 and decodes the instruction data sent on the internal bus 4 to decode each part of the processor unit 1, that is, the two-dimensional register 2 and the inversion unit 3a.
And 3b, various kinds of control data to the transfer buffer 5, the arithmetic unit 6, and the input / output buffer 7.

FIG. 2 is a configuration diagram showing details of the two-dimensional register 2. The two-dimensional register 2 has a total of 64 latch circuits Rmn (m = n = 0 to 7) arranged in a matrix in the horizontal (X) direction and the vertical (Y) direction with eight circuits each. The data is collected for each column and supplied to the X data output unit 20, and the data is collected for each row and collected in the Y data output unit 21.
Supplied to

The X data output unit 20 receives the input latch circuit R ₀ n of each column.
From the output of to R ₇ n, selects the output of one specified by the control data Cd ₀ ~Cd ₃ to be described later, and outputs it as X data Xd ₀ ~Xd _7. Similarly, the Y data output unit 21 selects one output from the outputs of the latch circuits Rm _{0 to} Rm _{7 in} each row, and outputs it as Y data Yd _{0 to} Yd ₇ .

X data Xd ₀ ~Xd ₇ and Y data Yd ₀ ~Yd ₇ are input to the OR gate group 22, respectively for each corresponding data, namely data Xd ₀ and Yd _0, data Xd ₁ and Yd _1, ..., data Xd ₇ and Yd ₇
Logical OR is taken for each, as the output data Od ₀ ~Od _7.

8-bit input data Id ₀ ~Id ₇ is amplified by the data buffer 23, the latch circuits of the corresponding row and column
Supplied to Rmn. For example, the input data Id ₀ of the first bit
Are all the latch circuits R _{00 to} R ₀₇ and R in the first row and the first column
₀₀ is supplied to to R _70, 2 all the latch circuits of the input data Id ₁ of bit line 2 and the second column R ₁₀ to R ₁₇ and R ₀₁ to R ₇₁
Supplied to Other bits are similarly supplied to all the latch circuits in the corresponding row and column.

Control data Cd ₀ ~Cd ₃ and Ad _0, Ad ₁ is amplified in the control buffer 24, it is supplied to the demultiplexer 25 and 26. However, the control data Cd ₀ is inverted by the inverter 27 and supplied to the demultiplexer 25 as the control data d ₀ . Demultiplexer 25 receives control data
d ₀ and Cd ₁ the X-direction of the latch circuit Rm ₀ ~Rm ₇ outputs a strobe signal Sx ₀ ~Sx ₇ for enabling the ~Cd _3, also Y-direction from the control data Cd ₀ ~Cd ₃ to the demultiplexer 26 and it outputs a strobe signal Sy ₀ to SY ₇ for enabling the latch circuit R ₀ n~R ₇ n.

In this case, the control data Cd ₀ is a bit for designating the X or Y direction, a binary code of 3 bits specifying the control data Cd ₁ ~Cd ₃ Number of rows or columns. Therefore, if the data Cd ₀ is “0” and the data Cd _{1 to} Cd ₃ are “010”, the strobe signal Sx ₁ for selecting the second row in the X direction
There is output second line of the latch circuit R ₁₀ to R ₁₇ is enabled. The data Cd ₀ is "1", if the data Cd ₁ ～Cd ₃ is "011", the latch circuit R ₀₂ in the third column in the strobe signal Sy ₂ is output to select the third row in the Y-direction - R ₇₂ is enabled.

The control data Ad ₀ and Ad ₁ are signals for checking whether the data stored in all the latch circuits Rmn are all “0” or “1”.
And is supplied to the X data output unit 20. Output unit 20
In the data stored in all the latch circuits Rmn is if all "0" and outputs the all 0 detection signal AL _0, outputs the all-1 detection signal AL ₁ if all "1".

FIG. 3 is a configuration diagram of the latch circuit Rmn. The latch circuit Rmn has a flip-flop 30 for latching input data in response to a clock signal φ. The data IN terminal of the flip-flop 30 has an output of an AND gate 31 and an output of an AND gate 32 connected to an OR gate 33. Is entered via AND
Gate 31 receives input data Idm and strobe signal Sxm, and AND gate 32 receives input data Idn and strobe signal Syn. Strobe signals Sxm and Syn are input to the strobe terminal of the flip-flop 30 via the OR gate 34. Also flip flop
The data OUT terminal 30 is connected to the X data output section 20 as described above.
And the input of the Y data output unit 21.

FIG. 4 is a block diagram showing the configuration of the X data output unit 20. The output unit 20 is provided with a selector S ₀ ~S _7, NOR gate N ₀ ~N _7, AND gates A ₀ to A ₇ provided corresponding to each column of the latch circuit Rmn, NOR gate N ₀ to N ₇ Each output of AND gate
To A _8, each output of the AND gate A ₀ to A ₇ are input to the AND gate A _9.

The selector Sn is used to input all the latch circuits R ₀ n to R in the n-th column.
Select any one of the data specified by the control data Cd ₀ ~Cd ₃ from the output of the ₇ n, and outputs it as X data XDN. The output time of the NOR gate Nn output of all the latch circuits R ₀ N to R ₇ n of n-th column to be input is all "0" becomes "1", the AND gates An is the n-th column is input its output when all the latch circuits R ₀ n~R ₇ n outputs are all "1" becomes "1".

Accordingly, when AND gate A ₈ is the control signal Ad ₀ is input, if the total output of the NOR gate N ₀ to N ₇ is "1", i.e. if the output of all the latch circuits Rmn is "0" the output signal AL ₀ becomes "1". Also, AND gate A ₉
Is the AND gate A ₀ when the control signal Ad ₁ is input.
If all outputs to A ₇ is "1", i.e., all the latch circuits
If the output of Rmn is “1”, the output signal AL ₁ is “1”.
Becomes Thus, it is possible to check whether the outputs of all the latch circuits Rmn are all 0 or all 1 by one access.

FIG. 5 is a block diagram showing the configuration of the Y data output unit 21. The output unit 21 includes a selector S ₀ '~S _7' latch circuit
It is provided corresponding to each row of Rmn. Selector Sn 'selects any one of data designated by the control data Cd ₀ ~Cd ₃ from the outputs of all the latch circuits R _n0 to R _n7 in the n-th row to be input and output as Y data Ydn . In this case, the control data Cd ₀ is inverted by the inverter 50 and is input as the control data d ₀ to each of the selectors S ₀ ′ to S ₇ ′.

FIG. 6 is a circuit diagram showing the configuration of the reversing units 3a and 3b, and typically shows the reversing unit 3a.

The reversing portion 3a is composed of an inverter 68. inverting the control data Cd sent logic gates 60-67 and the control unit 9 which is the input of the input data D ₀ to D _7. The logic gate 60 is composed of two AND gates 60a and 60b and an OR gate 60c that performs a logical sum of outputs of the two AND gates 60a and 60b.
The AND gate 60a is input to the input data D ₀ and control data Cd is controlled to the AND gate 60b and the input data D ₇ data d
Is input. Similarly, for the other logic gates 61 to 67,
The AND gate 61a~67a input data D ₁ to D ₇ and control data Cd is input to the AND gate 61b~67b input data D
₆ to D ₀ and the control data d is input.

Therefore, if the control data Cd is "1", the input data D ₀ to D ₇ are output as output data Id ₀ ~Id _7, if control data Cd is "0", the input data D ₀ to D ₇
Has the LSB and MSB are output inverted as output data Id ₇ ~Id _0.

According to this embodiment, stores input data Id ₀ ~Id ₇ can be stored in any row and column of the register of the two-dimensional register 2, also in any row and column of the register of the two-dimensional register 2 Output data Od _{0 to} Od ₇
, The data in the X direction and Y
Direction data can be processed by the same processing method. Further, the reversing units 3a and 3b can easily perform reversal processing of data in the left-right and up-down directions.

FIG. 7 is a block diagram showing a second embodiment of the present invention, showing an example in which the present invention is applied to a memory unit.

In Figure 7, the memory unit 70 is provided with a first to 25 memory blocks MB ₀ to MB ₂₄ of the same structure capable of addressing the two-dimensional directions, each memory block MB ₀ to MB ₂₄ to the internal bus 71 It is connected. This memory block MB ₀
To MB _24, as shown in FIG. 8 (a), the partition D that was drawn from a portion of the image G, block was divided into 5 blocks by a total of 25 blocks in the horizontal and vertical directions # 0 to # 24
Each block is divided into 8 bits in each of the horizontal and vertical directions, for a total of 64 bits, as shown in FIG. The configuration of each of the memory blocks MB _{0 to} MB ₂₄ is the same as that of the two-dimensional register 2 described above.

The partition definition register 72, the mode register 73, and the input / output buffer 74 are further connected to the internal bus 71. The input / output buffer 74 is connected to other units via the system bus 9.

The address signal AD is amplified by the address buffer 75 and supplied to the block address generator 76. In a block address mode described later, the block address generation unit 76 calculates a memory block MB from an input address signal AD.
Block data specifying one of the blocks _{0 to} MB ₂₄ and address data specifying an XY address in the specified block are generated. The block data is transmitted to the block selector 77 and the address data is transmitted via the address bus 78. and supplies each of the memory MB ₀ ~MB _24. Block selector 77
In decodes the block data inputted supplied to the memory blocks MB ₀ to MB ₂₄ corresponding to the output signal.

When the direct address data mode will be described later, the address signal AD, is converted into the address data for designating the XY address of the block data and a memory block that specifies the memory block MB ₀ to MB ₂₄ in the block address generator 76 Output.

Here, the block address mode refers to FIG.
As shown in the figure, in the mode for specifying the pixel in the section D by the memory block address and the XY address in the block,
In the direct address mode, on the other hand, the pixels in the section D are
It is specified directly by the XY address.

Next, the partition definition register 72 specifies the size of the above-described partition D, and rewrites the bit width in the X direction and the bit width in the Y direction when the command CM is input. The contents of the partition definition register 72 are supplied to the block address generator 76 in the direct address mode, and the address signal AD
With the data indicating the address of the memory block and the
It is converted to data indicating the XY address.

The mode register 73 instructs the block address generation unit 76 whether the processing mode is the block address mode or the direct address mode, and stores various control data in the memory block.
Supplied to the MB ₀ ~MB _24.

If the bit width in the X direction of the section D is Lx, the bit width in the Y direction is Ly, the size of one block is Lb, and the XY address in the direct address mode is (Qx, Qy), each data in the block address mode Is expressed as follows.

First, block address Bno And the XY address (Px, Py) in the block is Px = Qy Mod Lb Py = Qx Mod Lb

Therefore, if the bit width Lx in the X direction is 40, the bit width Ly in the Y direction is 40, the size Lb of one block is 8, and the XY address (Qx, Qy) is (20, 18), the block address Bno becomes 1
2. The XY address (Px, Py) in the block is (2, 4).

〔The invention's effect〕

According to the present invention, the following effects can be obtained.

Since the horizontal direction and the vertical direction can be handled the same in the processor, the processing in the horizontal direction and the processing in the vertical direction become the same, and the processing speed can be improved. Also, the horizontal and vertical parameters of the program to be processed can be exchanged as needed, so that the program area can be small. Further, since the image data is accessed to the image memory via the reversing unit, the left / right reversal and up / down reversal processing of the data can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a processor unit, FIG. 2 is a block diagram showing a configuration of a two-dimensional register in FIG. 1, and FIG. 3 is a block diagram in FIG. FIGS. 4 and 5 are block diagrams showing the configuration of an X data output unit and a Y data output unit in FIG. 2, and FIG. 6 is a block diagram showing the configuration of an inversion unit in FIG. Fig. 7, Fig. 7 is a block diagram showing another embodiment in which the present invention is applied to a memory unit, Fig. 8 is a diagram for explaining the operation of Fig. 7, and Fig. 9 is a conventional image processing. It is a figure for explaining a system. 1... Processor unit, 2... Two-dimensional register,
3a, 3b: reverse section, 10: control section, 20: X data output section, 21: Y data output section, 70: memory unit,
72 …… Definition register, 73 …… Mode register, 76…
... block address generating unit, R ₀₀ ~R ₇₇ ...... latch circuit,
MB _{0 to} MB ₂₄ …… Memory block.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06T 1/60 G06F 12/00 580

Claims (1)

(57) [Claims] An address can be specified in an X direction and a Y direction inside a processor unit, and an image memory composed of M × M bits is accessed in units of M bits to perform image processing. An X-direction demultiplexer that specifies a column number in the X direction of the image memory; a Y direction demultiplexer that specifies a row number in the Y direction of the image memory; and one of the X direction and the Y direction demultiplexer. A demultiplexer selecting means for selecting, and an inverting unit for inverting a bit string in the MSB direction of the M-bit data input or output to the input and output stages to the image memory into a bit string in the LSB direction, Select the demultiplexer for an address signal instructing the X and Y direction demultiplexers Processor unit also added, characterized in that the additional signal was set to, is input to the demultiplexer selection means No..