JP3030734B2 - Semiconductor integrated circuit and logic modification method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology, and more particularly, to a technology effective when applied to a logic LSI and its logic change. For example, the logic modification of a logic LSI by a processing technology using a focused ion beam and laser CVD. It is related to useful technology for use in

[0002]

2. Description of the Related Art A logic LSI such as a microprocessor or a gate array used in a computer system, a workstation, or the like, has its logical configuration modified at the time of its development (logic modification).
Often do. The logic correction is performed by changing the pattern of the signal wiring connecting the logic gates. However, if the logic correction is performed from the change of the wiring mask pattern, the development period of the LSI becomes long. Therefore, a spare wiring or a spare gate circuit is provided in a surplus area of the LSI, and if necessary, the spare wiring or the spare gate circuit is used to directly cut the wiring on the LSI chip.
Logic modification is performed by connecting. For the correction of the connection between the spare gate circuit and the wiring performed at this time, a technique combining a focused ion beam (FIB) and laser CVD is used (for example, Japanese Unexamined Patent Publication No. Sho 62-2).
No. 29956).

[0003] In this method, a protective film (insulating film) of an integrated circuit formed on an LSI chip is etched with a focused ion beam to expose a desired wiring, or a wiring to be cut is removed. After being exposed and further cut by a focused ion beam, a conductive pattern (wiring layer) made of molybdenum (Mo) or tungsten (W) is selected between a predetermined spare wiring and a logic gate by using laser CVD. This is a technique for forming a layer (a jumper wire to be described later).

[0004]

However, it has been clarified by the present inventors that the above-described technology has the following problems. In other words, the focused ion beam technique [FIB] usually focuses gallium ions (Ga +) accelerated to 20 to 30 KeV in a region having a diameter of about 0.1 to 1.0 μm to form wiring or interlayer insulation of an LSI chip. The film is perforated by sputtering using gallium ions. Therefore, the positive charge of gallium applied to the LSI causes problems such as destruction of the transistor element inside the LSI or deterioration of its characteristics. In particular, in a device in which a MOS transistor is formed, the gate oxide film is as thin as 10 to 20 nm, so that the positive charge of gallium easily causes the gate breakdown of the MOS transistor or deterioration of characteristics.

More specifically, for example, when a spare gate (NAND gate) 300 (this spare gate is in an electrically floating state) as shown in FIG. Terminal 30
1 is connected to the output terminal of another internal gate and the output terminal 304 is connected to the input terminal of another internal gate), the wiring 301a connected to the input terminal 301 is replaced with a wiring (jumper line) 314 for logic correction. , And a jumper wire 315 may be connected to the output terminal 304. In this case, a hole is formed in the insulating film (not shown) covering the wiring 301a by FIB processing (connection opening 301).
b)). However, normally, since neither the ground terminal nor the power supply terminal is connected to the input side of the spare gate 300, when the FIB process is performed on the wiring 301a (FIG. 6), the static charge (Ga +) generated at this time is generated. Is the wiring 30
1a, the gate electrodes of the p-type MOS transistor 311 and the n-type MOS transistor 321 connected thereto (shown only on the pMOS 311 side in FIG. 6) are charged to the gate oxide film 321b, and the gate is destroyed. Causes the characteristic deterioration.

For this reason, there has been conventionally employed a method of irradiating electrons by providing an electron shower device in a chamber of the FIB device to neutralize positive ions of gallium irradiated from the FIB device (see FIG. 4 described later). However, there is no guarantee that the gallium ion beam is actually neutralized when the LSI chip is irradiated with the gallium ion beam, and the gate breakdown of the MOS transistor cannot be prevented reliably. In particular, when a new gate circuit is added as one mode of logic correction, the input terminal side of the spare gate circuit embedded in the LSI chip in advance is in a state of being electrically floating (floating state). Therefore, when the insulating film covering the input terminal of the gate circuit is processed by FIB, the input terminal is charged with a positive charge of gallium.
Since the input capacitance of the gate of the MOS transistor used in the recent CMOS is 5 to 10 fF, it is assumed that the FI
If the amount of charge charged by B is 1 pC (usually the ion beam current is 100 to 1000 pA, it is considered that such a charge remains after neutralization), the voltage applied to the gate reaches 100 to 200 V. However, the thickness of the gate oxide film of the MOS transistor is 10 to 2
0 nm (withstand voltage of about 20 to 30 V)
When the above voltage is applied, gate breakdown and deterioration of transistor characteristics are caused.

The present invention has been made in view of the above circumstances, and is intended to process an LSI chip with a focused ion beam (FIB) to connect a wiring on the input side of a spare gate circuit to a desired signal line of a logic circuit. A semiconductor integrated circuit and a logic correction method for preventing an internal element (transistor) of the spare gate circuit from causing gate destruction or deteriorating its characteristics due to the charge of the FIB. The purpose is to do. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application is as follows. That is, in a semiconductor integrated circuit in which a plurality of logic gate circuits and a logic correction spare gate circuit are formed, an input terminal of the logic repair spare gate circuit is connected to a ground terminal or a power supply terminal. Further, a wiring layer forming an input terminal of the spare gate circuit for logic correction is insulated from a wiring layer forming a signal line by an insulating film,
In performing a logic correction on this logic circuit, a connection opening is provided in the insulating film with a focused ion beam,
Thereafter, processing for disconnecting the power supply wiring from the wiring layer constituting the input terminal of the spare gate circuit for logic correction is performed.

[0009]

The wiring layer constituting the input terminal of the spare gate circuit is connected to the power supply wiring before being connected to the wiring layer constituting the desired signal line of the logic circuit. (FIB), even when a process for forming a connection opening in the insulating film on the upper surface of the wiring layer constituting the input terminal of the spare gate circuit is performed, the positive charges generated at the time of the FIB process cause the power supply wiring to be removed. This flows out to the ground terminal or the power supply terminal side through the terminal.

[0010]

An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a circuit configuration of a 3-input logic correction spare gate circuit (NAND gate) 100 used in the present embodiment. As shown in FIG.
The D gate 100 has three input terminals 101, 102, 1
03, three pMOSs 111, 112 , 113, and 3
NMOS 121, 122, 123 and output terminal 104
Is adopted. And the input terminal 101
PMOS 111 and nMOS 121 are connected in pairs, and pMOS 112 and nMOS 122 are connected to input terminal 102.
Are paired, and pMOS 113 and nM
The OSs 123 are connected in pairs. The three input terminals 101, 102, and 103 are connected to a discharge A
Branch wiring 10 branched into three l wirings (power supply wiring) 107
7a, 107b and 107c (indicated by dashed lines in the figure) are respectively connected.

The main wiring 107 of the discharge Al wiring 107
The end of d is connected to the ground terminal 108. More specifically, the main wiring 107d is made of, for example, an Al wiring as shown in FIG. 2, and is electrically connected to the diffusion layer 2 of the n − semiconductor substrate 1 through a contact hole 131 provided in a passivation film 130 covering the semiconductor element. It is connected. When the n-semiconductor substrate 1 is grounded,
The discharge Al wiring 107 is connected to the ground terminal.

Spare gate (NAND gate) having the above configuration
Reference numeral 100 denotes logic gates (internal logic gates) 201 and 202 which contribute to the logic configuration at the beginning of the design as shown in FIG. 3, and another spare gate (AN) provided in an extra area of the chip.
D gate, etc.) As with 100A, 100B, 100C, L
It is arranged at a predetermined position on the SI chip 10 and used for logic correction together with other spare gates.

A spare gate (NAND gate) 10 constructed generally as described above and provided in a surplus area of an LSI chip
0 is incorporated in a logic circuit by the following procedure at the time of logic modification. Here, for example, as shown in FIG. 3, the Al wiring 203 (wiring layer forming the signal line) between the two internal logic gates 201 and 202 is cut, and a new NA
When the ND gate 100 is incorporated with the jumper wires 204 and 205 (the input terminal 111 of the NAND gate 100 is connected to the jumper wire 204 (wiring layer for connecting to a desired signal line))
First, the case where the output terminal 104 is connected to the jumper wire 205) is considered.

In this case, first, in order to expose a wiring layer (wiring) 111a (FIG. 1) integrally formed in the same step as the input terminal 111 to the outside, a passivation film (insulating film; The connection opening 111b (shown by a dashed line in FIG. 1) is formed by performing FIB processing on (omitted).

The FIB process (irradiation of gallium ions with a focused ion beam) is performed by a focused ion beam device 300 shown in FIG. FIB device 3
00 denotes an ion source 310, an electrostatic lens 320, a scanning system 330, a sample stage 340, an acceleration power source 3 as shown in FIG.
50, a main power supply 360, and an electronic shower device 370 are main components. Then, gallium ions accelerated by an acceleration power supply from an ion source (liquid gallium) 310 are transferred to a desired position (LSI chip 10) on a wafer mounted on a sample stage 340 via an electrostatic lens 320 and a scanning system 330. Irradiated toward. At this time, the gallium ions are electrically neutralized by the electrons emitted from the electron shower device 370.

As described above, neutralization of gallium ions (Ga
++ e → Ga) is difficult to perform completely, so that some gallium ions remain, but the spare gate (NA
Since the ND gate) 100 has the configuration shown in FIG. 1, the gallium ions (Ga +) remaining without being neutralized are connected to the wiring 111 through the connection opening 111b that has been drilled.
a, and further flows from the main wiring 107d of the discharging Al wiring to the ground terminal 108 via the branch wiring 107a. For this reason, F
During the IB process, the gate of the pMOS 111 and the nMOS 121
No overvoltage is applied to the gate of the gate.

After performing the FIB process in this manner, the input terminal 101 of the spare gate 100 is connected to the internal gate (A
ND gate) 202 (FIG. 3) to be connected to an output terminal 202a by a jumper wire 204 using laser CVD.
Is formed. By this processing, jumper wire 20
4 has one end connected to the output terminal 202a of the gate 202 via the wiring 203 and the other end connected to the connection opening 111.
b, connected to the input terminal 101 of the NAND gate 100 via the wiring 111a (see FIGS. 1 and 3). After the jumper wire 204 is formed in this manner, the branch wiring 107a is cut at a predetermined position (for example, 107a 'in FIG. 1) by FIB processing, so that the output terminal 202a of the internal gate 202 and the spare gate 100 input terminals 11
1 will be connected as shown in FIG.

The branch wiring 107a is connected to the FIB as described above.
Even when cutting is performed by the device, positive charges of gallium ions are generated, and the charges may flow to the wiring 111a. In this case, the wiring 111a is connected to the jumper wire 204a.
Is already connected to the output terminal 202a of the internal gate 202, the charge is discharged from the output terminal side of the gate 202 to a ground terminal or a power supply terminal (both not shown) connected to the output terminal. , And is not stored on the input side of the spare gate 100, that is, on the gate of the MOS transistor. In addition, jumper wires 204 and 205
Is formed, the internal gate 201 and the internal gate 20 are formed.
The insulating film (not shown) covering the wiring 203 connecting
The holes (openings 203a and 203b) are made by IB, and gallium ions flow to the wiring 203. Since the wiring 203 is also connected to the output terminal 202a of the internal gate 202, the gates of these internal gate MOS transistors are connected. There is no destruction by a positive charge and no deterioration in transistor characteristics.

As described in detail above, in the above embodiment, in a semiconductor integrated circuit in which a plurality of logic gate circuits and a logic correction spare gate circuit are formed, the input terminal of the logic repair spare gate circuit is It is connected to a ground terminal or a power terminal. Further, a wiring layer forming an input terminal of the logic correction spare gate circuit is insulated from a wiring layer forming a signal line by an insulating film. When performing logic correction on the logic circuit, the wiring layer is focused on the insulating film. A connection opening is provided by an ion beam, and thereafter, a process of disconnecting a wiring layer forming an input terminal of a spare gate circuit for logic correction and a power supply wiring connected to a ground terminal or a power supply terminal is performed. Therefore, positive charges generated during the focused ion beam processing performed on the insulating film flow out to the ground terminal side,
Gate destruction of the MOS transistor in the spare gate and deterioration of transistor characteristics are avoided.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say. For example, in this embodiment, an example is shown in which a NAND gate is used as a spare gate. However, another logic circuit whose input side is normally in a floating state can be used as a spare gate.

In the above description, the invention made mainly by the present inventor is described in the CMO, which is a field of application which is the background of the invention.
The case where the present invention is applied to an S-type LSI has been described. However, the present invention is not limited to this, and a general logic integrated circuit (for example, BiCMOS) using a MOS transistor is used.
Logic integrated circuit in the form).

[0022]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, F is also used for correcting the wiring of the MOS LSI.
IB technology can be applied, and at this time, the logic can be corrected at a high yield without breaking the spare gate.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a 3-input logic correction spare gate circuit (NAND gate) 100 used in the present embodiment.

FIG. 2 is a perspective view showing a connection state of an Al wiring 107 shown in FIG. 1 to a semiconductor substrate 1.

FIG. 3 shows a logic L provided with an internal gate and a spare gate
FIG. 2 is a plan view schematically showing an SI chip 10.

FIG. 4 is a perspective view showing the overall configuration of a focused ion beam device 300.

FIG. 5 shows a conventional three-input logic correction spare gate circuit (N
FIG. 3 is a circuit diagram showing a circuit configuration of an AND gate (300).

FIG. 6 shows that the positive charge generated by the focused ion beam is MO
FIG. 4 is a perspective view showing a state where a gate of an S transistor is charged.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Logic LSI chip 100 NAND gate (logic spare gate circuit) 101, 102, 103 Input terminal 107 Discharge Al wiring (power supply wiring) 111a Wiring (wiring layer constituting input terminal) 111b Inside of connection opening 201, 202 Logic gate (logic gate circuit) 203 Wiring (wiring layer forming signal line)

Claims (10)

(57) [Claims] 1. A logic correction method for a semiconductor integrated circuit comprising: a plurality of logic gate circuits; and a logic correction spare gate circuit having an input terminal connected to a ground terminal or a power supply terminal. The wiring layer forming the input terminal of the spare gate circuit for correction is insulated from the wiring layer forming the signal line by an insulating film.
Providing a connection opening in the insulating film with a focused ion beam,
Thereafter, the connection between the wiring layer forming the input terminal of the spare gate circuit for logic correction and the power supply wiring is cut off, and the wiring connecting the wiring layer forming the input terminal of the spare gate circuit to a desired signal line is processed. A method for correcting a logic of a semiconductor integrated circuit, comprising forming a layer. 2. The method according to claim 1, wherein said spare gate circuit for logic modification includes a MOS transistor having a gate connected to an input terminal. 3. A first logic gate, a first wire connected to an output terminal of the first logic gate, a second logic gate, and a second wire connected to an input terminal of the second logic gate. A second wiring and a third wiring connecting a ground potential point or a power supply potential point, wherein the first wiring and the second wiring are formed through an opening formed in a passivation film by a focused ion beam. A semiconductor integrated circuit connected by a first jumper wire. 4. The semiconductor integrated circuit according to claim 3, wherein said first wiring and said third wiring are each cut by a focused ion beam. 5. A semiconductor device comprising: a third logic gate; and a fourth wire connected to an input terminal of the third logic gate, wherein the fourth wire and an output terminal of the second logic gate are connected to a second wire.
5. The semiconductor integrated circuit according to claim 4, wherein the first wiring and the fourth wiring are connected by a jumper wire, and the first wiring and the fourth wiring are intermittently connected via a portion cut by a focused ion beam. 6. The second logic gate, which is a spare logic gate, is connected to an output terminal of the first logic gate and a third logic gate to modify logic between the first logic gate and the third logic gate. 6. The semiconductor integrated circuit according to claim 5, wherein the first jumper line and the second jumper line are connected between the first and second input terminals. 7. The first wiring, the second wiring, and the third wiring are formed in a layer between a passivation film and a diffusion layer of a semiconductor substrate, and are opened in the passivation film by cutting with the focused ion beam. 6. The semiconductor integrated circuit according to claim 3, wherein a portion is formed. 8. The jumper wire is formed of molybdenum or tungsten by laser CVD, and is formed in a layer between a passivation film and a diffusion layer of a semiconductor substrate through an opening provided by a focused ion beam. 8. The semiconductor integrated circuit according to claim 3, wherein the wirings are connected to each other. 9. The method according to claim 9, wherein the third wiring is cut by the focused ion beam after the opening is provided by the focused ion beam for connecting the first jumper wire and the first wiring. 9. The semiconductor integrated circuit according to claim 8, wherein: 10. The semiconductor device according to claim 3, wherein the second wiring and the third wiring are formed integrally.
A semiconductor integrated circuit as described in the above.