JP2002305254A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that has high ESD breakdown voltages against all surge cases without causing any malfunction, and to provide a method of manufacturing the device. SOLUTION: This semiconductor device is provided with an internal circuit, an input/output pad, and a branch circuit 27 which is connected to a lead-in wire 35 connecting the internal circuit and input/output pad to each other and outputs electric signals, corresponding to the electric signals impressed upon the wire 35 from its first and second terminals. The device is also provided with a clamp circuit constituted of a MOS transistor 28 which interrupts electrical communication when the absolute value of the difference between the voltage of an electric signal traveling from one terminal side and that of another electrical signal, traveling from the other terminal side is lower than a threshold voltage and realizes electrical communication, when the absolute value is equal to or higher than the threshold voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, to a high-frequency silicon MOSFET having high resistance to generation of sudden high voltage (surge) such as a discharge phenomenon. (Metal Oxide Semicon
The present invention relates to a semiconductor device including a ductor field effect transistor) and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the spread of mobile phones and the use of wireless LAN (L
With the practical use of an ocal area network), high-frequency semiconductor devices, which are indispensable for realizing higher performance, smaller size, and lower cost of these electronic devices, have attracted great interest. Conventionally, materials constituting these high-frequency semiconductor devices include IIs such as GaAs having high electron mobility.
Group IV compound semiconductors have been mainly used. However, in recent years, miniaturization of silicon MOS transistors has rapidly advanced, and it has become possible to manufacture MOS transistors having a gate length of less than 0.2 μm. The silicon MOS transistor having such a fine gate length has a remarkably improved transconductance Gm and an improved high-frequency characteristic, and is therefore applicable to gigahertz-band high-frequency devices. However, a silicon MOS transistor having a shortened gate length for use in a high-frequency device has a smaller size than a conventional device using GaAs or the like.
Resistance to surge is reduced. For this reason, it is necessary to provide a measure for coping with the occurrence of surge such as electrostatic discharge.

Next, measures for preparing for such disturbances as electrostatic discharge will be described. An electrostatically charged object comes into contact with another object, and the discharge phenomenon that occurs between those objects is called ES
It is called D (Electro Static Discharge). When ESD occurs in a semiconductor element, the semiconductor element may be damaged. There are the following three models as typical ESD models. (A) HBM (Human Body Mode) modeling discharge from a charged human body to a semiconductor element
l), (b) MM (Machine Model) modeling the discharge from the charged device to the semiconductor device, and (c) CDM modeling the phenomenon that the charge charged in the semiconductor device itself is discharged to a grounded object. (Charge Device Model). FIG. 59 shows examples of the current waveforms of (a) the HBM and (c) the CDM. As shown in FIG.
It can be seen that a current stress of about 1 A is generated for a relatively long time of 0 ns, but a high current stress of about 10 A is generated within a very short time of 1 ns in the CDM. It can be seen that a high current flows in a short time in any of the models.

[0004] As described above, when ESD occurs, a high current is applied to a semiconductor element in a short time, so that thermal destruction such as melting by Joule heat occurs. Furthermore, in recent years, when a MOS transistor structure, which is the mainstream of LSI (Large-Scale Integration) silicon devices, is used,
In some cases, a high electric field due to ESD is applied to a gate oxide film of a MOS transistor, causing dielectric breakdown. The dielectric breakdown of the gate oxide film due to the ESD is an obstacle to the use of inexpensive silicon semiconductors, and is a serious problem. In order to avoid the dielectric breakdown of the gate oxide film, various protection circuits are formed between the input / output pins and the internal circuit, and measures are taken to prevent the high voltage surge that flows when ESD occurs from transmitting to the internal circuit. Has been taken. This protection circuit is called an ESD protection circuit.
Since the object on the silicon wafer connected to the input / output pins by wire bonding is a pad, the term “input / output pad” will be used instead of the input / output pin in the following description.

As the ESD protection circuit, a circuit configured by connecting an off-state MOS transistor to an input / output signal line is often used (MDKer et. Al., IED).
M, pp. 889-892, 1996). FIG. 60 is a circuit diagram of a semiconductor device using an off-state MOS transistor as an ESD protection circuit. In FIG. 60, an n-channel MOS transistor 117n (hereinafter, referred to as nMOS) and a p-channel MOS transistor 117p (hereinafter, referred to as pMOS) are off. The drain D of the nMOS is connected to an input / output signal line, and its gate G, source S,
The p-conductivity type well (hereinafter, p-well) W is grounded. The drain D of the pMOS is connected to an input / output signal line, and its gate, source, and n-well are connected to an external supply voltage (hereinafter, referred to as Vdd). Since these two MOS transistors 117p and 117n are in the OFF state, no current flows during normal operation, so that normal device operation is not affected.

On the other hand, when a high voltage surge caused by ESD flows from the input / output pad, the pMOS and nM
In the OS, a parasitic bipolar transistor operation described below occurs, and a path for flowing a high current from the drain to the source is formed. FIG. 61 is a view for explaining the operation of the parasitic bipolar transistor of the MOS transistor. Here, it is assumed that the surge of the positive voltage enters the drain of the nMOS. First, a positive voltage surge is applied to the n + diffusion layer of the drain D formed on the silicon substrate 101, and when the voltage increases, the reverse biased n
+ The pn junction of the diffusion layer causes breakdown, and a large number of electron-hole pairs are generated due to the impact ionization (impact ionization) phenomenon. Among the generated electron-hole pairs, the electrons flow to the drain D applied with a positive voltage, and the holes flow to the grounded p-well W.

[0007] Here, the magnitude of the current which holes caused by flowing to the p-well and I _hole, and the resistance value of the p-well and R _sub, voltage drop depth of the p-well of I _hole · R _sub Get up in the direction. Due to this voltage drop, a potential difference is generated in the p-well, and the p-well at a shallow position immediately below the gate of the nMOS is formed.
The potential of the well region rises to a positive potential. At this time, an npn parasitic bipolar transistor is formed by the drain n + diffusion layer, the shallow p-well region immediately below the gate, and the source n + diffusion layer. In this npn parasitic bipolar transistor, a reverse bias voltage is applied to the junction between the drain n + diffusion layer and the shallow p well region below the gate, and the reverse bias voltage is applied to the junction between the shallow p well region below the gate and the source n + diffusion layer. A positive bias voltage is applied. By this voltage application, the parasitic npn bipolar transistor is turned on.

In summary, in an nMOS in which the gate is grounded and in the off state, when a positive voltage is applied to the drain when an ESD occurs, the npn parasitic bipolar transistor is turned on and a large current can flow. Becomes

The same operation as described above occurs when a negative voltage surge enters the drain of the pMOS. Further, when a positive voltage enters the drain of the pMOS, pM
The junction between the drain of the OS and the n-well is in a forward bias state, and current flows to the n-well. The ON operation in this case is an operation that the pMOS normally expects. Also, when a negative voltage surge enters the drain of the nMOS, it is in the forward bias state and the current flows to the p-well. Also in this case, the nMOS
Usually, this is a planned ON operation.

As described above, a large current can be released to GND (ground) or Vdd when an ESD occurs due to the ESD protection circuit using an off-state MOS transistor. As a result, it is possible to prevent a large current from flowing through the internal circuit and to prevent thermal breakdown and dielectric breakdown of the gate oxide film.

Here, in order for the off-state MOS transistor to perform the above-described ESD protection function, FIG.
As shown in FIG. 2, the distance d between the gate electrode of these MOS transistors and the contacts of the source and drain diffusion layers
Must be large enough. A gate electrode, a source,
The distance d between the drain diffusion layer and the contact is, for example,
There is a disclosure that it is necessary to secure 5 μm to 6 μm.
(MDKer et. Al., IEDM, pp. 889-892, 1996). It is said that the reason for increasing the distance d is to avoid a situation in which the surge is directly applied to the gate and a stress is applied to the gate because the resistance is increased by increasing the distance d.

Assuming that the diameter of the contact is c, the width of the source and drain diffusion layers sandwiched between the gate electrodes is 2d + c
Becomes For this reason, in the MOS transistor used for the ESD protection in which the distance d needs to be large, the width of the source and drain diffusion layers also becomes large. For example,
According to the 0.2 μm design rule, c is generally 0.2 μm, so that the width (2d + c) of the source / drain diffusion layers is as large as 10.2 μm to 12.2 μm. Therefore, for example, in order to realize a sufficient ESD protection function, the gate width of the MOS transistor needs to be at least 100 μm. The general parasitic capacitance of the source / drain diffusion layer per unit area in the 0.2 μm design rule, that is, the depletion layer capacitance of the pn junction between the source / drain diffusion layer and the well is 1 fF / μm ² . Therefore, MOS used as an ESD protection element
The parasitic capacitance formed between the source and drain diffusion layers of the transistor and the silicon substrate (well) is 1.02 p
F to 1.22 pF, which is very large.

As described above, the extremely large parasitic capacitance of the ESD protection element has not been a problem in semiconductor memories and logic devices. However, in a high-frequency device using a silicon MOS transistor, this parasitic capacitance becomes a serious problem. Since the magnitude | Z | of the impedance Z of the capacitor C is expressed by 1 / (2πfC), when the frequency becomes high and the frequency f increases, the capacitance C
It can be seen that the magnitude | Z | When the capacitance C is large, the magnitude | Z | of the impedance of the capacitance C is further reduced. In other words, when the large capacitance of the source and drain diffusion layers is connected to the high-frequency signal line, the magnitude of the impedance of these source and drain diffusion layers becomes extremely small at high frequencies. The semi-insulating high-resistance silicon substrate is made of GaAs.
Since a high-quality substrate such as an s substrate cannot be obtained, a low-resistance substrate must be used for the silicon substrate.

FIG. 63 shows a simplified equivalent circuit of an ESD protection circuit using MOS transistors formed on the silicon substrate. In this figure, since the resistance of the silicon substrate to which the capacitor is connected is small, most of the high-frequency signals flowing through the high-frequency signal line flow through the MOS transistor for ESD protection. Therefore, most of the high-frequency signals are lost due to the resistance of the silicon substrate.

As described above, when an ESD protection element is formed using silicon MOS transistors, it is very difficult to realize a high-frequency semiconductor device having high reliability for high-frequency signals. However, since protection against ESD is necessary, several measures have been taken. next,
These measures will be described.

When protecting an internal circuit from an ESD surge entering a high frequency signal input / output pad, it is necessary to protect the following four cases depending on the location of the ground plane. (A) A case where a positive voltage ESD surge flows into the high frequency signal input / output pad and the ground plane is a GND pin. (B) A case where a positive voltage ESD surge flows into the high frequency signal input / output pad and the ground plane is the Vdd pin. Certain cases (C) A negative voltage ESD surge flows into the high frequency signal input / output pad and the ground plane is a GND pin. (D) A negative voltage ESD surge flows into the high frequency signal input / output pad and the ground plane is Vdd. Case that is a pin In the above conventional ESD protection circuit, the case (A)
In response to each of (D) to (D), a surge flows out to the ground plane by the following operation, and the internal circuit is protected. (A) A surge is caused by the parasitic bipolar operation induced by the breakdown of the diffusion layer of the nMOS to ground the ground plane (G
(ND pin). (B) The surge flows out to the ground plane (Vdd pin) by the diode forward operation of the pMOS diffusion layer. (C) The surge flows out to the ground plane (GND pin) by the forward operation of the diode of the diffusion layer of the nMOS. (D) The surge is caused by the parasitic bipolar operation induced by the breakdown of the diffusion layer of the pMOS and the ground plane (V
dd pin).

From the protection operation in each of the above cases, the protection of the internal circuit is performed by utilizing both the breakdown and the forward operation by applying a reverse voltage to the junction between the diffusion layer and the well of the MOS transistor. I know you are.

[0018]

However, in such a protection operation, the ESD protection capability at the time of performing the operation involving the reverse breakdown of the junction of the diffusion layer is lower than the ESD protection capability at the forward operation. (Ker et.al., IEEE J. Solid-St.
ate Circuits, vol. 35, No. 8, pp. 1194-1199, 2000).

For this reason, there is known a method of forming the following protection circuit so as not to affect the characteristics of the high frequency signal input / output pad. That is, a circuit is used in which a pMOS transistor 118p and an nMOS transistor 118n whose gate widths are increased are arranged between the Vdd line and the GND line (FIG. 64). The gate width is determined by the pMOS transistor 11 connected to the high-frequency signal input / output pad.
7p and nMOS transistor 117n. In such a protection circuit, the following protection operation is performed in each of the above cases. (A) The surge is first caused to flow out to the Vdd line mainly by the diode forward operation of the diffusion layer of the pMOS 117p. For this reason, the surge has a large gate width,
It flows into the pMOS 118p having a high D protection capability. This p
The MOS 118p causes breakdown of the diffusion layer due to the surge, causes a parasitic bipolar operation, and turns on to form a path for passing the surge. Thereafter, the surge flows into the nMOS 118n connected to the pMOS 118p, causes the nMOS 118n to perform a forward operation, and flows out to the ground plane GND pin. (B) The surge flows out to the ground plane (Vdd pin) by the diode forward operation of the diffusion layer of the pMOS 117p. (C) The surge flows out to the ground plane (GND pin) by the diode forward operation of the diffusion layer of the nMOS 117n. (D) The surge is first caused to flow out to the GND line by the diode forward operation of the diffusion layer of the nMOS 117n. Next, the above surge has a large gate width,
It flows into the nMOS 118n having a high D protection capability. This n
The MOS 118n causes the breakdown of the diffusion layer due to the surge, causes a parasitic bipolar operation, and turns on to form a path for passing the surge. Thereafter, the surge flows into the pMOS 118p connected to the nMOS 118n, causes a forward operation in the pMOS 118p, and flows out to the ground plane Vdd pin.

As described above, the ES of the MOS transistors 118p and 118n arranged between the Vdd line and the GND line.
Even when the D protection function is used, there are cases where these MOS transistors perform a breakdown operation by applying a reverse voltage. For this reason, excellent ESD protection characteristics cannot be expected in all of the above cases.

In order to overcome the above problem, a method of arranging a transient response clamp circuit 128 between the Vdd line and the GND line as shown in FIG. 65 has been proposed (MD Ker et.a.
l., IEEE J. Solid-State Circuits, vol.35, No.8, pp.1194
-1199, 2000). According to such a circuit, in all cases, outflow of the surge is realized only in the forward direction of the diode. Therefore, the ESD protection capability is improved, and the gate width of the ESD protection circuit MOS transistor connected to the high frequency signal input / output pad can be significantly reduced. Due to the arrangement of the transient response clamp circuit 128, the parasitic capacitance added to the high frequency signal input / output pad is reduced, and it is possible to avoid remarkable deterioration of the high frequency characteristic when the conventional ESD protection circuit is attached.

N which constitutes the above transient response clamp circuit
The MOS is immediately turned on only for an ESD surge whose waveform rises steeply due to the RC circuit configuration.
As a result, it is possible for the ESD surge to flow from the Vdd line to the GND line or from the GND line to the Vdd line.
Further, the above-mentioned transient response clamp circuit operates the Vdd line and the G line at a low voltage at which the MOS transistor connected to the high frequency signal input / output pad does not cause a reverse breakdown operation.
The voltage of the ND line can be clamped. As a result,
With a very narrow gate width and good high-frequency characteristics, the ESD protection operation is realized in all cases only by the diode forward operation.

Also, during normal operation other than the flow of the ESD surge, that is, the normal range of Vdd is applied to the Vdd power supply pin.
When the dd voltage is applied, the transient response clamp circuit 128 does not turn on because the rising waveform of the Vdd voltage is gentle. Therefore, during normal operation, the Vdd line and GND
Because the line is cut off, the transient response clamp circuit has no effect during normal operation. As described above, the ESD protection circuit with the transient response clamp circuit that can reduce the parasitic capacitance is very useful as a high frequency ESD protection circuit.

However, since only the waveform steepness of the signal applied to the Vdd line is the switching reference of the transient response clamp circuit 128, a malfunction may occur during normal operation. Such a malfunction impairs the reliability of the high-frequency device and is not allowed. For this reason, there has been a demand for an ESD protection circuit having high reliability without any room for malfunction.

An object of the present invention is to provide a high-frequency silicon MOS.
It is an object of the present invention to provide a semiconductor device including an FET and having high ESD resistance to all surge cases without causing a malfunction, and a method of manufacturing the same.

[0026]

According to the present invention, there is provided a semiconductor device comprising:
An internal circuit including the semiconductor element, an input / output pad which is a terminal of the internal circuit, and an electric signal corresponding to an electric signal applied to the input line, which is connected to an introduction line connecting the internal circuit and the input / output pad. A branch circuit that outputs signals from the first and second terminals, and an MO disposed between the first and second terminals.
And a clamp circuit including an S transistor. This MOS transistor has a configuration in which the absolute value of the difference between the voltage of the electric signal transmitted from the first terminal and the voltage of the electric signal transmitted from the second terminal is smaller than the threshold voltage of the MOS transistor. , The first terminal side and the second
To the terminal side, and when the absolute value of the voltage difference exceeds the threshold voltage, conduction is realized, and the voltage applied to the internal circuit is clamped so as not to exceed a predetermined value. .

With this configuration, in the normal operation, the protection circuit including the branch circuit and the clamp circuit formed by the MOS transistor can operate only when a surge is applied.
The surge can flow out. For this reason,
The internal circuit can be protected without affecting the internal circuit at all. In addition, since the threshold voltage of the MOS transistor can be made to correspond to the clamp voltage, an arbitrary voltage may be set as the clamp voltage according to the magnitude of the signal voltage during normal operation, the peak voltage of a surge that is likely to occur, and the like. Can be. The switching of the clamp function by the threshold voltage is performed by the voltage value without depending on the steepness of the surge which has been conventionally performed, so that the accuracy is very high and the protection circuit has high reliability. If the branch circuit is configured so as not to cause reverse bias, breakdown, and the like, it is possible to cope with any case of surge and protect the internal circuit thoroughly. However, the above branch circuit is not limited to the case where the surge is transmitted in the forward bias direction, but also includes the case where the surge is transmitted in the reverse bias direction due to the occurrence of breakdown.

The clamp circuit described above may be a clamp circuit composed of only MOS transistors as long as it has the above-mentioned functions.

In the semiconductor device of the present invention, for example,
The MOS transistor is an n-channel MOS transistor, a first terminal is connected to the drain of the n-channel MOS transistor, a second terminal is connected to the source, and a gate and a drain of the n-channel MOS transistor are connected. The p-type well and the source of the n-channel MOS transistor can be connected to each other (claim 2). Similarly, the MOS transistor is a p-channel MOS transistor, and the drain of the p-channel MOS transistor has a first terminal,
The source is connected to the second terminal, the gate of the p-channel MOS transistor is connected to the source, and the n-conductivity well of the p-channel MOS transistor is connected to the drain. 3).

By connecting the wirings of the nMOS transistor or the pMOS transistor constituting the clamp circuit as described above, the difference between the voltages applied to the drain and the source becomes the difference between the voltages applied to the gate and the channel. be able to. As a result, the clamp voltage, which is the potential difference applied to both terminals (drain and source) of the clamp circuit, can be used as the threshold voltage of the MOS transistor. As a result, it is possible to control the voltage of the signal applied from the outside by discharging the voltage to the ground plane as a surge without introducing the voltage to the internal circuit or conducting the signal to the internal circuit as a signal, by controlling the threshold voltage.

In the semiconductor device of the present invention, for example,
It is desirable that the threshold voltage of the n-channel MOS transistor is higher than the voltage applied in the normal operation to the external power supply line connecting the branch circuit and the external power supply. Further, it is desirable that the threshold voltage of the p-channel MOS transistor is higher than the voltage applied to the external power supply line connecting the branch circuit and the external power supply in the normal operation.

By setting the threshold voltage of the clamp circuit as described above, it is possible to cause a voltage higher than the above-mentioned threshold voltage to flow out as a surge without affecting the signal during normal operation at all. Since the threshold voltage can be arbitrarily adjusted by changing the configuration of the MOS transistor, the boundary between the signal voltage and the surge voltage during normal operation can be set very easily.

In the semiconductor device of the present invention, for example,
The gate of the n-channel type MOS transistor can be made of a p-type semiconductor. Alternatively, the gate of the p-channel MOS transistor can be made of an n-type semiconductor.

With this configuration, the work function is increased due to the difference in the conductivity type between the gate and the channel, and a high threshold voltage Vth can be easily obtained.

In the semiconductor device of the present invention, for example,
The branch circuit is a p-channel type M connected together to the feedthrough.
The p-channel MOS transistor is composed of an OS transistor and an n-channel MOS transistor. One of a source and a drain is connected to an introduction line, and the other is connected to a gate, an n-conductivity well, and a first terminal. And the n-channel MOS transistor has one of a source and a drain connected to the introduction line, and the other connected to a gate, a p-conductivity type well, and the second terminal. (Claim 8).

The arrangement of the MOS transistors is equivalent to the arrangement of diodes in an equivalent circuit.
In a normal case, a branch circuit can be formed only by the forward operation of each element. Further, since the gate width of the MOS transistor of the branch circuit can be reduced, the parasitic capacitance can be suppressed to a small value. Therefore, for example, the impedance does not become extremely small with respect to a high-frequency signal. As a result, it is possible to prevent the high-frequency signal from conducting preferentially to the branch circuit. However, depending on the waveform of the surge, the position where the surge is applied, and the like, the surge may not be transmitted to the outside due to only the forward operation of the MOS transistor forming the branch circuit, but may go outside through the reverse operation. .

In the semiconductor device of the present invention, for example,
P-channel type MOS transistor and n-channel type M
Both of the gate widths of the OS transistors can be smaller than the gate widths of the MOS transistors forming the clamp circuit.

With this configuration, the MO constituting the branch circuit is formed.
The two wells of the S transistor can be reduced in size, and the capacitance can be reduced. For this reason, the impedance of the branch circuit does not become very small even for high-frequency signals, and high-frequency signals lost through the branch circuit can be reduced.

In the semiconductor device of the present invention, for example,
A branch circuit is connected to two p-lines connected to the lead-in and arranged in a forward direction from the second terminal to the first terminal.
It can be an n-junction diode (claim 10).

As described above, by arranging two pn junction diodes, a branch circuit can be constituted only by elements that operate in the forward direction, and the internal circuit is completely protected against surges in all cases. can do.

In the semiconductor device of the present invention, for example,
The internal circuit is a silicon MOSFET (Metal Oxide Semicon
The circuit may include a ductor field effect transistor (claim 11).

In the semiconductor device of the present invention, the value of the impurity concentration of the p-conductivity type in the channel portion of the n-channel type MOS transistor forming the clamp circuit is made larger than the value of the impurity concentration of the channel portion of the MOS transistor included in the internal circuit. It can be higher (claim 12). Further, the n-conductivity type impurity concentration in the channel portion of the p-channel MOS transistor constituting the clamp circuit can be made higher than the impurity concentration value in the channel portion of the MOS transistor included in the internal circuit. .

By increasing the impurity concentration of the channel region, inversion in the channel of the MOS transistor can be prevented from occurring even at a high gate voltage. Therefore, the threshold voltage can be easily and accurately increased by adjusting the impurity concentration of the channel region. When the branch circuit is composed of two MOS transistors, the impurity concentration of the channel portion of the MOS transistor of the clamp circuit is determined based on the MOS transistor of the branch circuit instead of the MOS transistor of the internal circuit. It can be made higher than the value of the impurity concentration of the channel portion.

According to the above configuration, a semiconductor device having high ESD resistance, for example, a high-frequency semiconductor device can be obtained using inexpensive silicon. The internal circuit described above may or may not be a high-frequency circuit.

In the above-described semiconductor device of the present invention, the thickness of the gate insulating film of the MOS transistor forming the clamp circuit is adjusted to the thickness of the gate insulating film of at least one of the silicon MOS transistors included in the internal circuit. It can be thicker than it is.

With the above configuration, the threshold voltage can be increased by making the gate insulating film of the n-channel MOS transistor or the p-channel MOS transistor of the clamp circuit thicker than the gate insulating film of a normal MOS transistor. it can. The on / off control of the channel is performed by an electric field immediately below the gate, and the same electric field cannot be generated unless the gate voltage is increased by increasing the thickness. Since the thickness of the gate insulating film can be adjusted arbitrarily, the threshold voltage can be set at an arbitrary high position with good controllability. When the branch circuit is composed of MOS transistors, the gate insulating film of the MOS transistor of the clamp circuit is replaced with the gate insulating film of the branch circuit instead of the MOS transistor of the internal circuit. It can be thicker than that.

In the semiconductor device of the present invention, for example,
The internal circuit may be a high frequency circuit.

According to the above configuration, a branch circuit with reduced parasitic capacitance can be formed so that the impedance for a high-frequency signal is not extremely reduced. For this reason,
Even if the internal circuit includes, for example, a silicon semiconductor element, a semiconductor device having high ESD resistance and excellent high-frequency characteristics can be obtained. The internal circuit may include a silicon MOS transistor, or may include a silicon MOS transistor.
The OS transistor may not be included. Further, the internal circuit may or may not include a III-V group compound semiconductor device such as GaAs.

In the semiconductor device of the present invention, for example,
The branch circuit, the clamp circuit, and the internal circuit can be formed on the same silicon substrate.

According to the above configuration, it is possible to manufacture a semiconductor device which is excellent in surge resistance corresponding to all surges and has good high frequency characteristics, for example, in a compact and inexpensive manner.

A method of manufacturing a semiconductor device according to a first aspect of the present invention includes a branch circuit including first and second conductivity type MOS transistors, and a clamp circuit including the first conductivity type MOS transistor. This is a method for manufacturing a high-frequency semiconductor device provided with a protection circuit. According to this manufacturing method, a well of a first conductivity type MOS transistor of a branch circuit and a well of a first conductivity type MOS transistor forming a clamp circuit are respectively formed on a silicon substrate. And a step of additionally implanting a first conductivity type impurity into a channel portion of a surface layer portion of a well of the first conductivity type MOS transistor of the clamp circuit.
7).

With this configuration, the impurity concentration in the channel region can be made higher than in the normal case, and the threshold voltage corresponding to the boundary between the signal voltage and the surge in the normal operation can be set higher. Since the impurity can be implanted with high accuracy, the threshold voltage can be set with high accuracy. When forming the well, the first conductivity type MO of the branch circuit is formed.
Since it can be performed at the same opportunity as the well formation of the S transistor, the manufacturing process can be simplified.

A method of manufacturing a semiconductor device according to a second aspect of the present invention includes a branch circuit including first and second conductivity type MOS transistors, and a clamp circuit including the first conductivity type MOS transistor. This is a method for manufacturing a high-frequency semiconductor device provided with a protection circuit. In this manufacturing method, a first resist pattern covering a gate of a first conductivity type MOS transistor of a clamp circuit and a second conductivity type MOS transistor of a branch circuit is arranged, and a source and a drain of the first conductivity type MOS transistor of the clamp circuit are arranged. Implanting a first conductivity type impurity into the first conductivity type MOS transistor of the branch circuit; and a second resist covering the source and drain of the first conductivity type MOS transistor of the clamp circuit and the first conductivity type MOS transistor of the branch circuit. The pattern is arranged, and the first conductivity type MOS of the clamp circuit
Implanting a second conductivity type impurity into the gate of the transistor and the second conductivity type MOS transistor (claim 18).

By setting the gate conductivity type of the first conductivity type MOS transistor to the second conductivity type, the threshold voltage can be increased due to the difference in work function. Also in this case, the difference in the work function changes according to the impurity concentration, so that the threshold voltage can be accurately changed by controlling the impurity concentration. The order of the first conductivity type impurity implantation step and the second conductivity type impurity implantation step may be interchanged.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, for example, in the arrangement of the first resist pattern, a simple resist pattern covering only the first conductivity type MOS transistor of the branch circuit is arranged. In the conductivity-type impurity implantation step, the first conductivity-type impurity having a dose smaller than that implanted in the second conductivity-type impurity implantation step can be implanted by using the simple resist pattern.

With this configuration, it is not necessary to provide a resist covering the gate of the MOS transistor of the clamp circuit. Further, when a sidewall is provided in the gate, the LDD has a width of about the maximum thickness of the sidewall, and the width of the LDD can be smaller than that in the case where the resist is provided. Therefore, it is effective for reducing parasitic capacitance, miniaturization, high-speed operation, and the like.

A method of manufacturing a semiconductor device according to a third aspect of the present invention includes a branch circuit including first and second conductivity type MOS transistors, and a clamp circuit including the first conductivity type MOS transistor. This is a method for manufacturing a high-frequency semiconductor device provided with a protection circuit. This manufacturing method includes a first conductivity type and a second conductivity type MOS of the branch circuit.
Disposing a resist pattern covering the first conductivity type MOS transistor of the branch circuit on the gate layer covering the transistor region and the first conductivity type MOS transistor region of the clamp circuit, and implanting a second conductivity type impurity Patterning the gate layer to form the first conductivity type and second conductivity type MOS transistors of the branch circuit and the gate electrode of the first conductivity type MOS transistor of the clamp circuit; A resist pattern covering the gate of the first conductivity type MOS transistor of the clamp circuit is disposed, and the first conductivity type impurity is doped into the source and drain of the first conductivity type MOS transistor of the clamp circuit and the first conductivity type MOS transistor of the branch circuit. And injecting (claim 20).

According to this configuration, it is not necessary to form a resist pattern aimed at the gate of the MOS transistor of the clamp circuit, and the shape of the resist pattern can be simplified.

[0059]

Next, embodiments of the present invention will be described with reference to the drawings. Embodiment 1 FIG. 1 is a diagram showing a silicon MOSFET semiconductor device according to Embodiment 1 of the present invention. The internal circuit is a high-frequency semiconductor device including a silicon MOSFET. A circuit 27 using two off-state MOS transistors is connected to a lead-in line 35 connecting a high-frequency signal input / output pad of the semiconductor device and an internal circuit. The gate width of the two MOS transistors 27p and 27n is determined by the off-state MOS that constitutes the conventional protection circuit.
It can be much smaller than that of a transistor. For this reason, a large capacitor is not formed unlike the MOS transistor constituting the conventional branch circuit, and the impedance does not become extremely small even for a high-frequency signal.
For this reason, the loss of the high-frequency signal can be reduced to a practically acceptable level. As the gate width, for example, the gate width of the nMOS transistor 27n is set to 5 to 10
0 μm, and the gate width of the pMOS transistor 27p can be 5 to 200 μm. More specifically, n
The gate width of the MOS transistor 27n is 25 μm,
The gate width of the pMOS transistor 27p can be set to 50 μm. The above circuit 27 is called a branch circuit.
A first terminal and a second terminal exit from the branch circuit, and the first terminal
Is connected to a Vdd line connected to an external power supply, and the second terminal is connected to a GND line.

In addition to the branch circuit 27, Vdd
Voltage (Vdd) applied to the Vdd line between the line and the GND line
NMO having a large gate width and having the above threshold voltage Vth
An S transistor 28 is provided. The gate width of nMOS transistor 28 having this high Vth is, for example, 10
It can be in the range of 0 μm to 10 mm, more specifically, 1 mm. The MOS transistor 28 having the large threshold voltage Vth is called a clamp element.

Next, the protection operation of the silicon MOSFET semiconductor device will be examined for the above four cases (A) to (D). Case (A): As shown in FIGS. 2 and 3, the positive voltage surge that has flowed into the high-frequency signal input / output pad first flows into the Vdd line due to the diode forward operation of the diffusion layer of the pMOS transistor 27p of the branch circuit 27. . In the nMOS transistor 28 having a high Vth, the source S and the p well W are connected. However, unlike the conventional nMOS transistor in the off state of the ESD protection, the gate G
Is not connected to the source S and the p well W, and the drain D
It is connected to the. Therefore, in case (A), G
Since the ND line is a ground plane, the source S of the high Vth nMOS transistor 28 and the p well W are grounded. In this state, the positive voltage surge 31 flows into the drain D and the gate G, and the drain and the gate are charged to a positive voltage.

When the voltage of the Vdd line becomes higher than the threshold voltage Vth due to the surge inflow, the gate voltage becomes higher than the threshold voltage Vth.
exceeds th. Therefore, the nMOS transistor 28 of the clamp element is turned on (the channel on state in FIG. 3), and current flows from the drain to the source through the channel. That is, the Vdd line is electrically connected to the ground line GND, and the ESD surge flows out to the ground line GND line. As a result, the MO in the branch circuit
The ESD protection operation is performed without causing reverse breakdown in S transistors 27p and 27n. Cases (B) and (C): As described above, the MO of the branch circuit 27 does not pass through the high Vth nMOS transistor
By the forward operation of S transistors 27n and 27p, E
SD protection operation can be performed. Therefore, MO
Neither of the S transistors 27n and 27p causes reverse breakdown.

Case (D): As shown in FIGS. 4 and 5, the negative voltage surge 32 flowing into the high-frequency signal input / output pad flows to the GND line by the forward operation of the nMOS transistor 27n, and the Vdd line and the GND line And flows into the source S of the high Vth nMOS transistor 28 disposed between them. In this case (D), since the ground plane is the Vdd line, the drain D and the gate G of the high Vth nMOS transistor 28 are grounded. Also, a high Vth nMOS
Since the source S of the transistor 28 is connected to the p-well W, the transistor 28 is charged to a negative voltage by the inflowing negative voltage surge.

When the charging voltage, that is, the absolute value of the voltage of the GND line becomes higher than the threshold voltage Vth of the nMOS transistor 28, the high Vth nMOS transistor 28 is turned on. In the on state, current will flow from the drain to the source through the channel. That is, G
The ND line and the Vdd line on the ground plane are electrically connected, and the ESD surge flows out to the Vdd line on the ground plane. Also in this case, the MOS transistor 27 of the branch circuit
No reverse breakdown of p, 27n occurs,
An ESD protection operation can be performed.

According to the above configuration, in all cases (A) to (D) in which a surge is applied, the M
The ESD protection operation can be realized without causing reverse breakdown in the OS transistors 27p and 27n. Therefore, the gate width of the MOS transistor of the branch circuit 27 connected to the high-frequency signal input / output pad can be reduced. Therefore, it is possible to obtain a high ESD resistance while reducing the parasitic capacitance and avoiding the deterioration of the high frequency characteristics. Further, since the clamp element 28 between the Vdd line and the GND line is a voltage clamp circuit, unlike the transient response type, a malfunction does not occur and a highly reliable device can be provided.

During normal operation, this high Vth nM
The source S and the p-well W of the OS transistor 28 are grounded, and the voltage of the Vdd line is applied to the drain D and the gate electrode G. Normal MOS transistor is connected to Vdd line and GND
When the device is arranged between the Vdd line and the Vdd line, the normal MOS transistor is completely turned on under the above voltage condition, causing a short circuit between the Vdd line and the GND line, and the device does not operate normally. However, this nMOS transistor 28
Has a threshold voltage Vth higher than Vdd during normal operation, so that during normal operation the potential difference between the gate electrode and the p-well is less than Vth. Therefore, during normal operation, the nMOS transistor of high Vth maintains the off state, and does not affect the normal operation of the device.

As described above, in the present invention, the voltage applied between the Vdd line and the GND line can be clamped without affecting the normal operation and causing no malfunction at a desired voltage. Therefore, it is possible to obtain a high-frequency semiconductor device using silicon MOS transistors having high ESD resistance and high reliability. Further, by reducing the gate width of the two MOS transistors in the branch circuit, the parasitic capacitance is reduced,
Deterioration of high frequency characteristics can be avoided.

It should be noted that, depending on the waveform of the surge and the position to which the surge is applied, a surge that is transmitted in the reverse operation may occur due to the breakdown. Even in such a case, the normal operation is not affected at all, and when a surge occurs, the internal circuit can be protected from the surge by the clamp element. In the case where the surge is transmitted by the reverse operation due to the breakdown, the same occurs in the following embodiments. (Embodiment 2) FIG. 6 is a diagram showing a silicon MOSFET semiconductor device according to Embodiment 2 of the present invention. The second embodiment is different from the first embodiment in that the MOS transistor 28 of the clamp element is a pMOS, and the other configuration is the same as that of the first embodiment. In FIG. 6, in the high Vth pMOS transistor 28, the drain D and n
The well G is connected to the well W, and the gate G is connected to the source S without being connected to the drain D and the n-well W.

When a high Vth pMOS transistor is used for the clamp element 28, the protection operation is the same as when an nMOS transistor is used, and the same effect can be obtained. For example, the gate width of the nMOS transistor 27n arranged on the high frequency signal input / output pad is 5-10.
0 μm, and the gate width of the pMOS transistor is 5 to 5.
200 μm. Further, the gate width of the pMOS transistor arranged in the clamp circuit 28 is set to, for example, 10
It can be 0 μm to 10 mm.

According to this embodiment, the voltage between the Vdd line and the GND line can be clamped at a desired low voltage against the inflow of the ESD surge. For this reason, the MOS transistor of the branch circuit 27 does not cause reverse breakdown, and in all cases, the forward operation causes
SD protection operation can be performed. As a result, high ESD resistance can be ensured without causing a malfunction, and deterioration of high frequency characteristics due to lower parasitic capacitance can be avoided. (Embodiment 3) FIGS. 7 to 22 show a method of manufacturing a silicon MOSFET semiconductor device according to Embodiment 3 of the present invention. Silicon MO in Third Embodiment
In the SFET semiconductor device, the p-type impurity concentration in the channel of the high Vth nMOS transistor is
Higher than the mold impurity concentration. In the present embodiment,
High pth of the channel of the high Vth nMOS transistor 28
The type impurity concentration is realized by additional implantation of p-type ions. For the description of the subsequent manufacturing process,
Regions such as a drain, a channel, and a well are not shown in the drawing.

First, a trench isolation,
An isolation oxide film 2 such as LOCOS isolation is formed, and then a well is formed (FIG. 7). Next, the channel region (p) of the high Vth nMOS transistor is
In addition, p-type ions are implanted on the surface side of the well (FIG. 8). By implanting the added p-type ions into the channel region, a high threshold voltage Vth can be secured.

Thereafter, a gate insulating film 4 such as an oxide film or a nitride film is formed, and an undoped polycrystalline silicon film 5 serving as a gate electrode is formed thereon (FIG. 9). Next, the polycrystalline silicon film 5 is patterned to form a gate electrode 5a (FIG. 10). Thereafter, a resist 30 is disposed in the pMOS region, and n-type ions are implanted in the source and drain regions of the nMOS to form an LDD (Lightly Doped Drain).
omain) (FIG. 1)
1). Further, a resist 30 is arranged in the nMOS region, and p-type ions are implanted in the source and drain regions of the pMOS to form a p-type region (not shown) of the LDD (FIG. 12). Next, a sidewall 6 is formed on the side surface of the gate electrode 5a by an insulating film made of any of an oxide film, a nitride film, and a combination of an oxide film and a nitride film (FIG. 13).

Further, after a resist is arranged in the pMOS region, n-type ions (not shown) are formed by implanting n-type ions into the source and drain of the nMOS (FIG. 14).
At this time, an n-type impurity is implanted into both the gate of the high-Vth nMOS transistor 28 and the gate of the other nMOS transistor 27n to be n-type. Thereafter, a resist is arranged in the nMOS region, and p-type ions are implanted into the source and drain regions of the pMOS to form ap + -type region (FIG. 15).

Next, an insulating film 7 made of an oxide film or the like for preventing silicide is formed (FIG. 16).
(FIG. 17). Next, the insulating film 7 other than the high Vth nMOS region is removed by etching (FIG. 18). Thereafter, the silicide film 8 is connected to the nMOS and pM connected to the high frequency signal input pad.
The gate electrode 8a is deposited on the OS and patterned.
And source and drain electrodes 8b (FIG. 1).
9). As silicide, titanium silicide, cobalt silicide, or the like can be used. Next, an interlayer insulating film 9 is deposited and planarized (FIG. 20). Thereafter, a contact hole 11 penetrating the interlayer insulating film 9 is opened (FIG. 2).
1) Fill a metal film and deposit a metal film on the interlayer insulating film. The metal film filling the contact hole 11 forms a contact 14 such as a tungsten plug which is electrically connected to a lower electrode. The metal film formed on the interlayer insulating film is patterned to form a first-layer metal wiring 1.
5 (FIG. 22).

Thereafter, the steps of forming an interlayer insulating film, forming a via hole, forming a second-layer metal wiring, and the like are continued, and metal wirings are formed in a required number of layers. Finally,
A passivation film serving as a protective film is formed, a pad is opened, and the manufacturing process ends.

According to the above-described manufacturing method, the silicon MOSFE including the high Vth nMOS in the protection circuit in which the p-type impurity concentration of the channel is higher than the impurity concentration inside the p-well.
The T semiconductor device can be easily integrated on one substrate and manufactured. The threshold voltage Vth of the nMOS transistor 28 is adjusted by adjusting the p-type impurity concentration additionally implanted into the channel region of the nMOS transistor.
It can be arbitrarily and easily controlled. (Fourth Embodiment) FIGS. 23 to 31 are views showing a method for manufacturing a silicon MOSFET semiconductor device according to a fourth embodiment of the present invention. Silicon M in Embodiment 4
In the OSFET semiconductor device, the n-type impurity concentration in the channel portion of the high Vth pMOS transistor is higher than the n-type impurity concentration in the n-well. In the present embodiment, a high n-type impurity concentration in the channel of the pMOS transistor 28 of high Vth is realized by additional implantation of n-type ions.

First, a trench isolation,
An isolation oxide film 2 such as LOCOS isolation is formed, and then a well is formed (FIG. 23). Next, n-type ions are additionally implanted into the channel region (n-well surface side) of the high Vth pMOS transistor using the resist 30 (FIG. 24). By implanting the added n-type ions into the channel region, a high threshold voltage Vth can be secured.

Thereafter, a gate insulating film 4 such as an oxide film or a nitride film is formed, and an impurity-free polycrystalline silicon film 5 serving as a gate electrode is formed thereon (FIG. 25). Next, the polycrystalline silicon film 5 is patterned to form a gate electrode 5a (FIG. 26). Thereafter, a resist 30 is arranged in a region other than the nMOS transistor 27n, and n
N-type ions are implanted into the source and drain regions of the MOS to form an n-type region (not shown) of an LDD (Lightly Doped Domain) (FIG. 27). Further, a resist 30 is arranged in the region of the nMOS transistor 27n, and the pMO
P-type ions are implanted into the source and drain regions of the S transistor 27p and the high Vth pMOS transistor 28 to form an LDD p-type region (not shown) (FIG. 2).
8). Next, a sidewall 6 is formed on the side surface of the gate electrode 5a by an insulating film made of any of an oxide film, a nitride film, and a combination of an oxide film and a nitride film (FIG. 2).
9). Further, the pMOS transistor 27p and the high V
After a resist is arranged in the region of the pMOS transistor 28 of the th, n-type ions (not shown) are formed by implanting n-type ions into the source and drain of the nMOS transistor 27n (FIG. 30). Thereafter, the nMOS transistor 27
A resist is disposed in the n region, and p-type ions are implanted into the source and drain regions of the pMOS transistor 27p and the high Vth pMOS transistor 28 (FIG. 31).

Thereafter, by using the same manufacturing method as in the third embodiment, the silicon MOS of the present embodiment is
An FET semiconductor device can be manufactured.

According to the above-described manufacturing method, the silicon MOSFET semiconductor device of the present embodiment can be easily manufactured integrally on one substrate, and the threshold voltage Vth of pMOS transistor 28 arranged as a clamp element can be obtained. Can easily be raised. The threshold voltage Vth is adjusted by adjusting the concentration of p-type impurities additionally implanted into the channel region of the nMOS transistor.
It can be arbitrarily controlled. Fifth Embodiment FIG. 32 is a cross-sectional view showing a high Vth nMOS transistor forming a clamp element of a silicon MOSFET semiconductor device according to a fifth embodiment of the present invention. The present embodiment is characterized in that the gate of the high Vth nMOS transistor 28 is formed of p-type polycrystalline silicon. In a normal nMOS transistor, the gate is formed of n-type polycrystalline silicon.

In the high Vth nMOS transistor according to the present embodiment, the gate is made of p-type polycrystalline silicon by utilizing the difference in work function, so that the high threshold voltage Vth
Can be realized. Therefore, without increasing the number of masks, a high Vth nMO is applied between the Vdd line and the GND line.
An S transistor can be arranged to form a clamp element. As a result, it is possible to obtain a low-cost, high-performance silicon MOSFET semiconductor device having high ESD resistance.

As an example of manufacturing such a semiconductor device, a pMOS is connected to the gate of a high Vth nMOS transistor 28.
At the time of p-type ion implantation into the source and drain of the transistor 27p, p-type ions are formed in a resist mask offset structure in parallel.

First, a trench or a LO
An isolation oxide film 2 such as a COS isolation film is formed, and a well is further formed. Next, after forming a gate insulating film 4 such as an oxide film or a nitride film, an impurity-free polycrystalline silicon film 5 is formed thereon (FIG. 33). This undoped polycrystalline silicon film 5 is patterned to form a gate electrode 5a (FIG. 34). Next, a resist 30 is disposed in the pMOS transistor region, and n-type ions are implanted into the source and drain regions of the nMOS transistor 27n and the high Vth nMOS transistor 28, thereby forming an LD.
An n-type region of D is formed (FIG. 35). Then, FIG.
A p-type ion is implanted into the source and drain regions of the pMOS transistor 27p to form a p-type region of the LDD, as shown in FIG. Next, a sidewall of a film made of an oxide film, a nitride film, or a combination of an oxide film and a nitride film is formed on the side surface of the gate electrode 5a (FIG. 3).
7).

Next, a resist is arranged as shown in FIG. 38, and n-type ions are implanted into the source, drain and gate of the nMOS transistor 27n and into the source and drain of the high Vth nMOS transistor 28. As shown in FIG. 38, at this stage, no n-type ions are implanted into the gate of the high Vth nMOS transistor 28. High Vth
The resist arranged in the region of the nMOS transistor 28 is a resist having a resist mask offset structure for implanting n-type ions into the source and drain without implanting into the gate. Due to the resist having this structure, the LDD 24 has a shape extending outside the sidewall as shown in FIG.

Next, a resist is arranged as shown in FIG. 39, and p-type ions are implanted into the source, drain and gate of the pMOS transistor 27p and into the gate of the high Vth nMOS transistor 28. The resist arranged in the region of the high Vth nMOS transistor 28 is a resist for implanting p-type ions into the gate and not implanting the ions into the source and drain.

According to the above-described manufacturing method, the threshold voltage Vth of the nMOS transistor 28 used for the clamp element can be easily increased. Sixth Embodiment FIGS. 40 and 48 are cross-sectional views showing a high Vth pMOS transistor forming a clamp element of a silicon MOSFET semiconductor device according to a sixth embodiment of the present invention. In this embodiment, the pMO of high Vth
The feature is that the gate of the S transistor 28 is formed of n-type polycrystalline silicon. In a normal pMOS transistor, the gate is formed of p-type polycrystalline silicon. As described above, by forming the gate of the pMOS transistor 28 with n-type polycrystalline silicon, a higher Vth can be realized due to a difference in work function. By this forming method, without increasing the number of masks
A clamp element having a high Vth pMOS transistor can be formed at low manufacturing cost.

The high Vth p having the above-mentioned n-type gate region
There are several types of MOS transistor structures and manufacturing methods. As an example, a structure and a manufacturing method of a (V) high Vth pMOS transistor of (X), (Y), and (Z) will be described. (X): As an example of the structure of a high Vth pMOS transistor having an n-type gate region, a structure shown in FIG. 40 can be given. On both sides of the channel on the surface of the n-well 21, p of the LDD extending outside the sidewall is provided.
A − type region 24 is arranged, and source and drain regions 22 and 23 of ap + type region are formed continuously from these wide p − type regions. N-type gate region 5a is formed from n + -type polycrystalline silicon. The method of manufacturing this high Vth pMOS transistor is as follows.

First, a trench isolation,
An isolation insulating film such as LOCOS isolation is formed, and a well is further formed. Next, a gate insulating film 4 is formed of an oxide film, an oxynitride film, or the like, and an impurity-free polycrystalline silicon film 5 is formed thereon (FIG. 41). Thereafter, gate electrode 5a is formed by patterning polycrystalline silicon film 5 (FIG. 42). Next, a resist is arranged as shown in FIG. 43, and n-type ions are implanted into the source and the drain of the nMOS transistor 27n to form an n − -type region of the LDD.

Next, the pMOS transistor 27p and the high Vth p
Source and drain p-type ions with the MOS transistor 28 are implanted to form an LDD p-type region. Thereafter, a sidewall is formed on the side surface of the gate electrode by using any insulating film such as an oxide film, a nitride film, and a combination of an oxide film and a nitride film (FIG. 45).

Thereafter, the resist is arranged as shown in FIG. 46, and the source, drain,
Also, the gate of the high Vth pMOS transistor 28 is
Implant n-type ions. The resist over the high Vth pMOS transistor 28 implants n-type ions into the gate,
The source and the drain are arranged so that n-type ions are not implanted. Thereafter, a pMOS transistor 27p and a high Vth pMOS transistor 28 are further added.
P-type ions are implanted into the source and drain of FIG.
7). In this p-type ion implantation step, a high Vth pMOS
Since ion implantation is performed using a resist covering the sidewalls of the transistor 28 as a mask, the LDD 24
As shown in FIG. 0, the shape extends to the outside of the sidewall 6.

The subsequent manufacturing steps are the same as the steps in the other embodiments. With the above steps, high V
A high threshold voltage Vth can be obtained by making the gate of the th pMOS transistor 28 n-type. (Y): Another example of the structure of a high Vth pMOS transistor having an n-type gate region is the structure shown in FIG. On both sides of the channel on the surface of the n-well 21, LDs not extending outside the sidewall 6 are provided.
A p-type region 25 of D is arranged, and the source and drain regions 42, 43 of the p + -type region are connected to these wide p-type regions.
Are formed. N-type gate region 5a is formed from n + -type polycrystalline silicon. This high Vth pMOS
The method for manufacturing the transistor is as follows.

In the manufacturing process of (Y), the source and drain of the nMOS transistor 27n and the pMOS of high Vth are formed by disposing the resist shown in FIG.
The steps up to the step of implanting n-type ions into the gate of the transistor 28 are the same. In the process so far,
N-type ions are implanted into the gate of the high Vth pMOS transistor 28. Next, as shown in FIG.
A resist is arranged only in the region of the MOS transistor 27n, and p-type ions are implanted. In the implantation of the p-type ions, the dose is made smaller than the dose of the n-type ions implanted earlier. Therefore, a high Vth pMOS
The gate of transistor 28 remains n-type. Also, the high Vth pMOS transistor 28 in FIG.
When p-type ions are implanted into the source and drain of the semiconductor device, p-type ions are implanted using the sidewalls as a mask.
D takes a shape that does not extend outside the sidewall.

As a result, a high Vth pMOS transistor having an n-type polycrystalline silicon gate can be easily manufactured while simplifying the arrangement of the resist and reducing the manufacturing cost. (Z): In this case, high V with n-type gate region
The structure of the th pMOS transistor is the same as the structure shown in FIG. On both sides of the channel on the surface of the n-well 21, the p-
A mold region 24 is arranged, and source and drain regions 22 and 23 of the p + -type region are formed continuously from these wide p − -type regions. N-type gate region 5a is formed from n + -type polycrystalline silicon. The method of manufacturing this high Vth pMOS transistor is as follows.

First, an isolation insulating film is formed on the silicon substrate 1, a well is formed, a gate insulating film 4 is formed, and an impurity-free polycrystalline silicon film 5 is formed thereon. Are the same as the steps up to FIG. 41 in (X).

Thereafter, by disposing the resist shown in FIG. 50, the nMOS transistor 27n and the high Vth nMO
N-type ions for the gate of the S transistor 28 are implanted. Thereafter, the polysilicon film 5 is patterned to form a gate electrode 5a (FIG. 51). Next, the arrangement of the resist shown in FIG.
n-type ions are implanted into the source and drain of n
Is formed.

Next, the pMOS transistor 27p and the high Vth pMOS
Source and drain p-type ions with the transistor 28 are implanted to form a p-type region of the LDD. Thereafter, sidewalls are formed on the side surfaces of the gate electrode by using any insulating film such as an oxide film, a nitride film, and a combination of an oxide film and a nitride film (FIG. 54).

Thereafter, the resist is arranged as shown in FIG. 55, and the source, drain,
Implant n-type ions. Thereafter, the resist is further arranged as shown in FIG.
Then, p-type ions are implanted into the source and drain of the high Vth pMOS transistor 28. In this p-type ion implantation step, a resist 30 is disposed so as to cover the sidewall of the high Vth pMOS transistor 28, and p-type ion implantation is performed using the resist as a mask. For this reason, LD
The region of D also extends outside the sidewall, and as shown in FIG. 40, a high Vth pMOS having an enlarged LDD.
You will get a transistor.

The subsequent manufacturing steps are the same as those in the other embodiments. With the above steps, high V
A high threshold voltage Vth can be obtained by making the gate of the th pMOS transistor 28 n-type.

As described above, as a method of manufacturing the clamp element 28, the gate insulating film may be thickened by any method in order to increase the threshold voltage Vth. (Embodiment 7) FIG. 57 is a circuit diagram showing a silicon MOSFET semiconductor device according to Embodiment 7 of the present invention. A diode type branch circuit 47 using a pn junction diode is arranged on a high frequency signal input / output pad, and a Vdd line and a GN
A high Vth nMOS transistor 28 as a clamp element is arranged between the nMOS transistor 28 and the D line. The junction area of the pn junction diode is, for example, 10 μm ^{2 to} 10 mm ² . In a normal case, a pn junction diode connected to the Vdd line is an element for conducting a positive voltage, and a pn junction diode connected to the GND line is an element for conducting a negative voltage. The gate width of the high Vth nMOS transistor 28 is, for example, 1
The thickness is set to 00 μm to 10 mm.

The diode-type branch circuit 47 is functionally the same as the branch circuit in which the pMOS and the nMOS in the off state are arranged. Therefore, the voltage of the Vdd line and the GND line can be clamped at a desired low voltage with respect to the inflow of the ESD surge. Also, without causing reverse breakdown of the diode,
D protection operation can be performed. As a result, it is possible to achieve a high ESD resistance without causing a malfunction and to obtain a silicon MOSFET semiconductor device having good high-frequency characteristics. (Eighth Embodiment) FIG. 58 is a circuit diagram showing a silicon MOSFET semiconductor device according to an eighth embodiment of the present invention. A diode type branch circuit 47 using a pn junction diode is arranged on a high frequency signal input / output pad, and a Vdd line and a GN
A high Vth pMOS transistor 28 is arranged between the gate and the D line. The only difference from the seventh embodiment is that a high Vth pMOS transistor is used as the clamp element 28. As described above, the high-Vth MOS transistor constituting the clamp element 28 may be either p-type or n-type.
The same effect can be obtained. Therefore, according to the present embodiment, a silicon MOSFET that achieves high ESD resistance without malfunction and has good high-frequency characteristics
A semiconductor device can be obtained.

Although the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. Not limited. The scope of the present invention is shown by the description of the claims, and further includes all modifications within the meaning and scope equivalent to the description of the claims.

[0102]

According to the present invention, a high-frequency silicon MOSF which does not degrade high-frequency characteristics, operates reliably by a surge voltage in response to a surge in any case, and can protect an internal circuit including a silicon MOSFET.
An ET semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 shows a silicon MO according to a first embodiment of the present invention.
FIG. 2 is a configuration circuit diagram of an SFET semiconductor device.

FIG. 2 is a diagram showing a flow of a positive voltage surge when a positive voltage surge enters the silicon MOSFET semiconductor device of FIG. 1;

FIG. 3 is a sectional view showing a flow of a positive voltage surge at a high Vth serving as a clamp element.

FIG. 4 is a diagram showing a flow of a negative voltage surge when a negative voltage surge enters the silicon MOSFET semiconductor device of FIG. 1;

FIG. 5 is a sectional view showing a flow of a negative voltage surge at a high Vth serving as a clamp element.

FIG. 6 shows a silicon MO according to a second embodiment of the present invention.
FIG. 2 is a configuration circuit diagram of an SFET semiconductor device.

FIG. 7 shows a silicon MOSFET according to the third embodiment of the present invention.
FIG. 13 is a cross-sectional view of a stage in which a separation film is formed on a silicon substrate in manufacturing the protection circuit portion of the T semiconductor device.

FIG. 8 is a cross-sectional view showing a step of arranging a resist and additionally implanting p-type ions into a high Vth nMOS channel region.

FIG. 9 is a cross-sectional view at a stage where a resist is removed to form a gate insulating film and a gate layer.

FIG. 10 is a cross-sectional view at a stage where a gate electrode is formed by patterning a gate layer.

FIG. 11 is a cross-sectional view of a stage where a resist is arranged and n-type ions are implanted into an nMOS to form an n − -type region of an LDD.

FIG. 12 is a cross-sectional view at the stage when p-type ions are implanted into a pMOS to form a p-type region of an LDD.

FIG. 13 is a cross-sectional view at a stage where a sidewall is formed on a side surface of a gate electrode.

FIG. 14 is a cross-sectional view at the stage when n-type ions are implanted into the source and drain of an nMOS.

FIG. 15 is a cross-sectional view at the stage when p-type ions are implanted into the source and drain of a pMOS.

FIG. 16 is a cross-sectional view at the stage when an insulating film for preventing silicide is formed.

FIG. 17 is a cross-sectional view of a stage where a resist is arranged on a high Vth nMOS region.

FIG. 18 is a cross-sectional view at a stage where an insulating film for preventing silicide is removed by etching using a resist as a mask.

FIG. 19 shows a pM of a branch circuit formed by forming a silicide film.
FIG. 4 is a cross-sectional view at a stage where OS and nMOS electrodes are formed.

FIG. 20 is a cross-sectional view at the stage when an interlayer insulating film is formed.

FIG. 21 is a cross-sectional view at the stage when a contact hole is opened in an interlayer insulating film.

FIG. 22 is a cross-sectional view of a stage where a metal film is formed so as to fill a contact hole and deposit the contact hole on the interlayer insulating film.

FIG. 23 shows a silicon MOSF according to the fourth embodiment of the present invention.
FIG. 9 is a cross-sectional view at a stage where an isolation film is formed on a silicon substrate in manufacturing the protection circuit portion of the ET semiconductor device.

FIG. 24 is a cross-sectional view at the stage of additionally implanting n-type ions into a high Vth pMOS channel region.

FIG. 25 is a cross-sectional view at a stage where a gate insulating film and a gate layer are formed.

FIG. 26 is a cross-sectional view of a stage where a gate electrode is formed by patterning a gate layer.

FIG. 27 is a cross-sectional view at the stage where n-type ions are implanted into an nMOS to form an n − -type region of an LDD.

FIG. 28 is a cross-sectional view at the stage when p-type ions are implanted into a pMOS to form ap − -type region of an LDD.

FIG. 29 is a cross-sectional view of a stage where a sidewall is formed on a side surface of a gate electrode.

FIG. 30 is a cross-sectional view at the stage when n-type ions are implanted into the source and drain of the nMOS.

FIG. 31 is a cross-sectional view at the stage when p-type ions are implanted into the source and drain of a pMOS.

FIG. 32 shows a silicon MOSF according to the fifth embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a clamp element made of a high Vth nMOS having a gate made of p-type polycrystalline silicon in the ET semiconductor device.

FIG. 33 is a cross-sectional view of a stage in which a gate insulating film and a gate layer have been formed in the manufacture of the nMOS of FIG. 32;

FIG. 34 is a cross-sectional view at the stage where the gate electrode is formed by patterning the gate layer.

FIG. 35 is a cross-sectional view at a stage where n-type regions of LDD are formed by implanting n-type ions into nMOS.

FIG. 36 is a cross-sectional view at the stage when p-type ions are implanted into a pMOS to form ap − -type region of an LDD.

FIG. 37 is a cross-sectional view of a stage where a sidewall is formed on a side surface of a gate electrode.

FIG. 38 is a cross-sectional view at the stage when n-type ions are implanted into the source and drain of the nMOS.

FIG. 39 shows the source, drain and high V of pMOS.
FIG. 9 is a cross-sectional view at the stage when p-type ions are implanted into a th gate.

FIG. 40 shows a silicon MOSF according to the sixth embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a clamp element made of a high Vth pMOS having a gate made of n-type polycrystalline silicon in the ET semiconductor device (X).

FIG. 41 is a cross-sectional view showing a stage where a gate insulating film and a gate layer are formed in the manufacture of the pMOS of FIG. 40;

FIG. 42 is a cross-sectional view at the stage where the gate electrode is formed by patterning the gate layer.

FIG. 43 is a cross-sectional view at the stage when n-type ions are implanted into an nMOS to form an n − -type region of an LDD.

FIG. 44 is a cross-sectional view at the stage when p-type ions are implanted into a pMOS to form ap − -type region of an LDD.

FIG. 45 is a cross-sectional view of a stage where a sidewall is formed on a side surface of a gate electrode.

FIG. 46 is a cross-sectional view at the stage when n-type ions are implanted into the source, drain, and gate of the nMOS and the gate of the high-Vth pMOS.

FIG. 47 is a cross-sectional view at the stage when p-type ions are implanted into the source, drain, and gate of the pMOS and the source and drain of the high Vth pMOS.

FIG. 48 shows a silicon MOSF according to the sixth embodiment of the present invention.
FIG. 15 is a cross-sectional view showing another high Vth pMOS clamp element having a gate made of n-type polycrystalline silicon in the ET semiconductor device (Y).

FIG. 49 shows that the source, drain, and gate of the pMOS and the source, drain, and gate of the high Vth pMOS have n
FIG. 9 is a cross-sectional view at a stage where p-type ions having a dose smaller than the dose of n-type ion implantation into a MOS are implanted.

FIG. 50 shows a silicon MOSF according to the sixth embodiment of the present invention.
FIG. 22 is a cross-sectional view in which a resist is arranged on the gate layer in the manufacture of another clamp element formed of a high-Vth pMOS in which the gate is made of n-type polycrystalline silicon in the ET semiconductor device (Z).

FIG. 51 is a cross-sectional view of a stage where a gate electrode is formed by patterning a gate layer.

FIG. 52 is a cross-sectional view showing a stage where n-type regions of an LDD are formed by implanting n-type ions into an nMOS.

FIG. 53 is a cross-sectional view at the stage when p-type ions are implanted into a pMOS to form a p − -type region of an LDD.

FIG. 54 is a cross-sectional view of a stage where a sidewall is formed on a side surface of a gate electrode.

FIG. 55: nMOS source, drain and gate
FIG. 4 is a cross-sectional view at a stage where mold ions are implanted.

FIG. 56 is a cross-sectional view at the stage when p-type ions are implanted into the source, drain, and gate of the pMOS and the source and drain of the high Vth pMOS.

FIG. 57 shows a silicon MOSF according to a seventh embodiment of the present invention.
In the ET semiconductor device, a branch circuit is formed by a pn junction diode, and a clamp element is configured by a high Vth nMOS.

FIG. 58 shows a silicon MOSF according to the eighth embodiment of the present invention.
In the ET semiconductor device, a branch circuit is formed by a pn junction diode, and a clamp element is configured by a high Vth pMOS.

FIG. 59 is a diagram showing an example of an ESD current waveform.

FIG. 60 shows E using a MOS transistor in an off state.
It is an SD protection circuit diagram.

FIG. 61 shows an E using an off-state MOS transistor.
FIG. 5 is a diagram illustrating a parasitic bipolar operation when an ESD occurs in the SD protection circuit.

62 is a plan view showing the arrangement of the gate and the source / drain contacts of the MOS transistor in the ESD protection circuit of FIG.

63 is a simplified equivalent circuit diagram of the ESD protection circuit of FIG. 60 and a diagram for explaining the outflow of a high-frequency signal to a silicon substrate.

FIG. 64 is a configuration diagram illustrating an example of a conventional ESD protection circuit.

FIG. 65 is a configuration diagram showing another example of the conventional ESD protection circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate, 2 isolation insulating film, 4 gate insulating film, 5 gate layer, 5 a gate electrode, 6 side wall, 7 silicide prevention insulating film, 8 a, 8 b silicide film electrode, 9 interlayer insulating film, 11 contact hole , 14 plug wiring, 15 first layer metal wiring, 21
Well, 22, 42 source, 23, 43 drain, 24, 25 LDD, 27, 47 branch circuit, 27
nMOS transistor of n branch circuit, pMOS transistor of 27p branch circuit, 30 resists, 35 introduction lines, S source, D drain, G gate, W well.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 F term (Reference) 5F038 BH04 BH05 BH07 BH13 DF02 5F048 AA02 AC01 AC03 BB03 BB06 BB07 BB16 BB18 BC06 BC20 BD04 BE03 BF07 CC09 CC13 CC15 CC18 CC19 DA25 DA27 DA30

Claims (20)

[Claims] 1. An internal circuit including a semiconductor element, an input / output pad serving as a terminal of the internal circuit, and a lead connected between the internal circuit and the input / output pad, and applied to the lead. A branch circuit for outputting an electric signal corresponding to the electric signal from the first and second terminals, and a MOS disposed between the first terminal and the second terminal
A clamp circuit constituted by a transistor, wherein the absolute value of the difference between the voltage of the electric signal transmitted from the first terminal and the voltage of the electric signal transmitted from the second terminal is When the voltage is lower than the threshold voltage of the MOS transistor, the conduction between the first terminal side and the second terminal side is cut off, and when the absolute value of the voltage difference becomes equal to or higher than the threshold voltage, the conduction is stopped. And a semiconductor device for clamping the voltage applied to the internal circuit so as not to exceed the predetermined value. 2. The semiconductor device according to claim 1, wherein said MOS transistor comprises an n-channel MOS transistor.
The first terminal is connected to the drain of the transistor, the second terminal is connected to the source, and the gate and drain of the n-channel MOS transistor are connected to each other. 2. The semiconductor device according to claim 1, wherein the well and the source are connected. 3. The p-channel MOS transistor, wherein the MOS transistor comprises a p-channel MOS transistor.
The first terminal is connected to the drain of the transistor, the second terminal is connected to the source, and the gate and the source of the p-channel MOS transistor are connected to each other. The semiconductor device according to claim 1, wherein the well and the drain are connected. 4. The semiconductor device according to claim 2, wherein a threshold voltage of the n-channel MOS transistor is higher than a voltage applied in a normal operation to an external power supply line connecting a first terminal of the branch circuit to an external power supply. 3. The semiconductor device according to claim 1. 5. An absolute value of a threshold voltage of the p-channel MOS transistor is higher than a voltage applied in an ordinary operation to an external power supply line connecting a first terminal of the branch circuit to an external power supply. The semiconductor device according to claim 3. 6. The gate of the n-channel MOS transistor is made of a p-type semiconductor.
Or the semiconductor device according to 4. 7. The p-channel MOS transistor according to claim 3, wherein a gate of the p-channel MOS transistor is made of an n-type semiconductor.
Or the semiconductor device according to 5. 8. The branch circuit includes a p-channel MOS transistor and an n-channel MOS transistor connected together to the lead-in line, wherein the p-channel MOS transistor is one of a source and a drain. One is connected to the introduction line, the other is connected to the gate, the n-conductivity type well, and the first terminal, and the n-channel MOS transistor has one of a source and a drain connected to the introduction line. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the gate, the p-type well and the second terminal. 9. The semiconductor device according to claim 8, wherein the gate width of each of the p-channel MOS transistor and the n-channel MOS transistor is smaller than the gate width of the MOS transistor forming the clamp circuit. 10. The branch circuit according to claim 1, wherein said branch circuit is two pn junction diodes connected to said lead-in line and arranged in a forward direction from said second terminal to said first terminal. 8. The semiconductor device according to any one of claims 7 to 7. 11. The internal circuit is a silicon MOSFET.
(Metal Oxide Semiconductor Field Effect Transisto
The semiconductor device according to claim 1, wherein the semiconductor device is a circuit including r). 12. A p-type impurity concentration value in a channel portion of an n-channel MOS transistor included in the clamp circuit is higher than an impurity concentration value in a channel portion of a MOS transistor included in the internal circuit. Item 12. The semiconductor device according to item 11. 13. The n-type impurity concentration in a channel portion of a p-channel type MOS transistor constituting the clamp circuit is higher than a value of an impurity concentration in a channel portion of a MOS transistor included in the internal circuit. 3. The semiconductor device according to claim 1. 14. The gate insulating film of a MOS transistor constituting the clamp circuit is thicker than the gate insulating film of at least one of the silicon MOS transistors included in the internal circuit. The semiconductor device according to claim 11. 15. The semiconductor device according to claim 1, wherein said internal circuit is a high-frequency circuit. 16. The semiconductor device according to claim 1, wherein said branch circuit, said clamp circuit, and said internal circuit are formed on a same silicon substrate. 17. A MOS of a first conductivity type and a second conductivity type.
A method for manufacturing a high-frequency semiconductor device, comprising: a protection circuit having a branch circuit including a transistor and a clamp circuit including a MOS transistor of a first conductivity type, wherein a first conductivity type of the branch circuit is provided on a silicon substrate. And the second
Forming a well of a conductive type MOS transistor and a well of a first conductive type MOS transistor forming a clamp circuit by injecting impurities of respective conductive types; and a first conductive type MOS transistor of the clamp circuit. And further implanting a first conductivity type impurity into the channel portion of the surface layer portion of the well. 18. A MOS of a first conductivity type and a second conductivity type.
A method for manufacturing a high-frequency semiconductor device including a protection circuit having a branch circuit including a transistor and a clamp circuit including a first conductivity type MOS transistor, wherein a gate of a first conductivity type MOS transistor of the clamp circuit is provided. And a first resist pattern covering the second conductivity type MOS transistor of the branch circuit is disposed, and a first resist pattern is provided on the source and drain of the first conductivity type MOS transistor of the clamp circuit and the first conductivity type MOS transistor of the branch circuit. A step of implanting a conductive impurity; a source and a drain of a first conductive MOS transistor of the clamp circuit; and a first conductive MOS of the branch circuit.
Arranging a second resist pattern covering the transistor,
The gate of the first conductivity type MOS transistor of the clamp circuit and the second conductivity type MOS transistor
Implanting a conductive impurity. 19. A method of disposing a first resist pattern, wherein a simple resist pattern covering only a first conductivity type MOS transistor of the branch circuit is disposed, and the simple resist pattern is used in the first conductivity type impurity implantation step. Implanting a first conductivity type impurity with a dose smaller than the dose implanted in the second conductivity type impurity implantation step;
A method for manufacturing a semiconductor device according to claim 18. 20. MOS of a first conductivity type and a second conductivity type
A method for manufacturing a high-frequency semiconductor device including a protection circuit having a branch circuit including a transistor and a clamp circuit including a first conductivity type MOS transistor, wherein a first conductivity type and a second conductivity type of the branch circuit are provided. A resist pattern covering the first conductivity type MOS transistor of the branch circuit is disposed on a gate layer covering the MOS transistor region of the first conductivity type and the first conductivity type MOS transistor of the clamp circuit; Implanting; and patterning the gate layer to form a first conductivity type and a second conductivity type MOS transistor of the branch circuit and a gate electrode of a first conductivity type MOS transistor of the clamp circuit; A second conductivity type MOS transistor and a first conductivity type MOS transistor of the clamp circuit; By placing a resist pattern covering over preparative, first the clamp circuit
Implanting a first conductivity type impurity into the source and drain of the conductivity type MOS transistor and the first conductivity type MOS transistor of the branch circuit.