JP3024508B2 - Semiconductor device having two-layer electrode structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a two-layer electrode structure, such as an EPROM.

[0002]

2. Description of the Related Art An EPROM of this type includes a source / drain region of a second conductivity type formed on a substrate surface having a well region of a first conductivity type and electrically separated from each other. Phosphorus-doped polycrystalline silicon (polysilicon: Poly-S) formed over a semiconductor substrate including at least a channel region via a first gate oxide film
i) and a control gate made of polycrystalline silicon provided on the floating gate with a second gate oxide film (interlayer insulating film) interposed therebetween.

Here, when the thickness of the second gate oxide film is reduced due to miniaturization of the element, there arises a problem that the withstand voltage of the second gate oxide film is reduced. Therefore, in the device disclosed in Japanese Patent Publication No. Hei 5-87993, when the thickness of the second gate oxide film is set to 600 ° which is smaller than the conventional thickness, the phosphorus concentration of the floating gate is set to 4 × 10 ²⁰ c.
m ⁻³ to 8 × 10 ²⁰ cm ^{−3 so} as to improve the withstand voltage in the second gate oxide film.

[0004]

However, when the device is further miniaturized, the thickness of the second gate oxide film becomes smaller than that disclosed in the above publication. Therefore, the relationship between the thickness of the second gate oxide film and the withstand voltage was examined. 5 to 9 relating to this study, polycrystalline silicon for forming a floating gate is referred to as 1Poly, doping phosphorus into polycrystalline silicon is referred to as phosphorus diffusion, and a second gate oxide film is formed. The film thickness is referred to as the inter-Poly film thickness, and the dielectric breakdown voltage is referred to as the Poly inter-breakdown voltage.

The phosphorus concentration in the floating gate is proportional to the phosphorus diffusion time,
When the phosphorus diffusion time is changed under the condition of 900 ° C. and 900 ° C., the phosphorus concentration changes as shown in FIG. From this figure, when the phosphorus diffusion time at 900 ° C. is 26 minutes, the phosphorus concentration is about 5.5 × 10 ²⁰ cm ⁻³ . This phosphorus concentration falls within the phosphorus concentration range of the above-mentioned prior art.

When a phosphorus-doped floating gate is formed under such phosphorus diffusion conditions, the relationship between the thickness of the second gate oxide film and its dielectric strength is shown in FIG. In FIG. 6, the thickness of the second gate oxide film was calculated by measuring the capacitance between the floating gate and the control gate and converting the capacitance between the capacitance and the gate area. The withstand voltage was set to a voltage applied when a voltage was applied between the floating gate and the control gate and a current flowing therebetween became a predetermined value (for example, 10 nA).

From this figure, it can be seen that in a region where the thickness of the second gate oxide film is about 600 ° like the above-mentioned conventional one, a sufficient withstand voltage of 8.0 MV / cm can be obtained. It can be seen that when the film thickness is very small, that is, 400 ° or less, the withstand voltage is greatly reduced.
The present invention has been made in view of the above problems, and an object of the present invention is to improve the withstand voltage of an oxide film when the thickness of the oxide film formed between electrode layers in a semiconductor device having a two-layer electrode structure is 400 ° or less. I do.

[0008]

Means for Solving the Problems The present inventors have made various studies on the point that the withstand voltage is reduced when the thickness of the second gate oxide film is 400 ° or less. If the phosphorus in the floating gate exceeds the solid solution limit, phosphorus segregates in the second gate oxide film or at the interface between the second gate oxide film and the floating gate. In this case, when the thickness of the second gate oxide film is large, the segregated phosphorus does not cause a problem in withstand voltage.

However, when the thickness of the second gate oxide film is reduced, it is considered that weak spots are formed due to the segregated phosphorus and the dielectric breakdown voltage is reduced. That is, when the thickness of the second gate oxide film is small, the segregation amount of phosphorus becomes relatively large, and it is considered that the dielectric breakdown voltage is reduced. FIG. 7 shows the relationship between the phosphorus diffusion time and the sheet resistance of the floating gate. Note that the data at each phosphorus diffusion time in the figure is shown as an average ± 3σ _n-1 of the measured values at n = 5 points per wafer. From this figure, when the phosphorus diffusion time is 26 minutes or more, the change in the sheet resistance is small and the phosphorus in the floating gate is in a supersaturated state. That is, when the phosphorus concentration is about 5.5 × 10 ²⁰ cm ⁻³ , the phosphorus in the floating gate is in a supersaturated state. In such a supersaturated state, the thickness of the second gate oxide film is 400 ° or less. Then, it is considered that the dielectric breakdown voltage decreased due to the segregation of phosphorus.

From FIG. 7, when the phosphorus diffusion time is 15 minutes or less, phosphorus in the floating gate is not in a supersaturated state due to the relation with the sheet resistance, and the phosphorus concentration at that time is as shown in FIG.
From about 3 × 10 ²⁰ cm ⁻³ or less. Therefore, when the phosphorus concentration is about 3 × 10 ²⁰ cm ⁻³ or less, the phosphorus in the floating gate does not become supersaturated, and the amount of segregation of phosphorus in the second gate oxide film decreases. Therefore, the second
It is considered that even if the thickness of the gate oxide film becomes 400 ° or less, the dielectric breakdown voltage does not decrease.

FIGS. 8 and 9 show the results of the study based on the above considerations. FIGS. 8A, 8B and 9A show the case where the thickness of the floating gate is 2000 ° and the phosphorus diffusion time is changed to 10, 15 and 26 minutes at 900 ° C., respectively. This is the withstand voltage characteristic of FIG. When the phosphorus diffusion time was changed to 10 minutes, 15 minutes, and 26 minutes, the phosphorus concentration in the floating gate was about 2 from FIG.
× 10 ²⁰ cm ^-3 , about 3 × 10 ²⁰ cm ^-3 , about 5.5 × 10
²⁰ cm ^-3 . From these figures, it can be seen that the phosphorus concentration is about 3 × 1
It can be seen that when the pressure is 0 ²⁰ cm ⁻³ or less, the withstand voltage characteristics are good.

Further, when the phosphorus diffusion condition is 950 ° C. for 20 minutes, the phosphorus is further supersaturated as shown in FIG. 7, and at this time, the dielectric breakdown voltage characteristic further deteriorates as shown in FIG. ing. The present invention has been made in view of the various studies described above, and the features thereof are as described in each claim.

That is, according to the first aspect of the present invention, the first electrode layer (4) formed on the semiconductor substrate (1a) via the first insulating film (3), A second insulating film (5) formed on the electrode layer (4) via a second insulating film (5);
In the semiconductor device having a two-layer electrode structure including the electrode layer (6), the second insulating film (5) has a thickness of 400.
The first electrode layer (4) is polycrystalline silicon doped with phosphorus and has a phosphorus concentration of 2 × 10 ^20.
It is characterized in that it is set in cm ^-3 or more or One 3 × 10 ²⁰ cm ^-3 or less.

According to the second aspect of the present invention, the first gate insulating film (3) formed on the semiconductor substrate (1a).
A source / drain region (7, 8) formed on the surface of the semiconductor substrate (1a); and a first gate insulating region on a channel region (9) between the source / drain regions (7, 8). 2 × 10 ²⁰ cm ^-3 formed through the film (3)
Above or One 3 × 10 ²⁰ cm ^-3 of polycrystalline silicon doped with phosphorus under the following floating gate (4)
And a second gate insulating film (5) formed on the floating gate (4) and having a thickness of 400 ° or less, and polycrystalline silicon formed on the floating gate via the second gate insulating film. And a control gate (6) comprising a semiconductor memory device.

According to a third aspect of the present invention, a step of forming a first gate insulating film (3) on a semiconductor substrate (1a), and a step of forming a polycrystalline silicon on the first gate insulating film (3). film (14) forming a polycrystalline silicon film or phosphorus 2 × 10 ²⁰ cm ^-3 or more one to (14) 3 × 10
A step of doping at a concentration of ²⁰ cm ^-3 or less, a step of patterning the phosphorus-doped polycrystalline silicon film to form a floating gate (4), and a step of forming a film thickness of 400 ° or less on the floating gate (4). Forming a second gate insulating film (5); forming a control gate (6) made of polycrystalline silicon on the floating gate via the second gate insulating film (5); Forming a surface of the semiconductor substrate (1a) immediately below the floating gate (4) as a channel region, and forming source / drain regions (7, 8) on the surface of the semiconductor substrate (1a) on both sides of the channel region (9); The method is characterized by a method of manufacturing a semiconductor memory device having:

According to a fourth aspect of the present invention, the first electrode layer (4) formed on the semiconductor substrate (1a) via the first insulating film (3), and the first electrode layer (4) In a semiconductor device having a two-layer electrode structure including a second electrode layer (6) formed on a second insulating film (5) via a second insulating film (5), the second insulating film (5) is The first electrode layer (4) is formed by thermal oxidation and has a thickness of 4
00 ° or less, and the first electrode layer (4) is polycrystalline silicon doped with phosphorus, and has a phosphorus concentration of
It is characterized in that it is set to 2 × 10 ²⁰ cm ^-3 or more or One 3 × 10 ²⁰ cm ^-3 or less. According to the invention described in claim 5, the first substrate formed on the semiconductor substrate (1a).
A gate insulating film (3), source / drain regions (7, 8) formed on the surface of the semiconductor substrate (1a), and a channel region (9) between the source / drain regions (7, 8). the first is formed through a gate insulating film ^{(3), 2 × 10 20} cm -3 or more or one 3 × 10 ²⁰ cm ^-3 of polycrystalline silicon doped with phosphorus under the following floating gate ( 4), a second gate insulating film (5) formed on the floating gate (4) by thermally oxidizing the floating gate and having a thickness of 400 ° or less; and a second gate insulating film. And a control gate (6) made of polycrystalline silicon formed on the floating gate. In the invention according to claim 6,
A step of forming a first gate insulating film (3) on the semiconductor substrate (1a); a step of forming a polycrystalline silicon film (14) on the first gate insulating film (3); phosphorus 2 × the silicon film (14) 10 ²⁰ cm ^-3 or more or one 3
Doping at a concentration of × 10 ²⁰ cm ⁻³ or less; patterning the phosphorus-doped polycrystalline silicon film to form a floating gate (4); and thermally oxidizing the floating gate (4). Forming a second gate insulating film (5) having a thickness of 400 ° or less on the floating gate (4);
A control gate (6) made of polycrystalline silicon on the floating gate via the gate insulating film (5)
Forming a channel region on the surface of the semiconductor substrate (1a) immediately below the floating gate (4);
The semiconductor substrate (1) on both sides of the channel region (9)
a) forming a source / drain region (7, 8) on the surface; In the present invention, a step of forming a first gate insulating film (3) on the semiconductor substrate (1a), and a step of forming a polycrystalline silicon film (14) on the first gate insulating film (3). ), And adding phosphorus to the polycrystalline silicon film (14) in an amount of 2 × 10 ²⁰ cm ⁻³ or more and 3 × 10 ²⁰
a step of doping at a concentration of not more than cm ^-3 , a step of patterning the phosphorus-doped polycrystalline silicon film to form a floating gate (4), a step of thermally oxidizing the floating gate, and forming the floating gate by thermal oxidation Removing the deposited oxide film, forming a second gate insulating film having a thickness of 400 ° or less on the floating gate, and forming the second gate insulating film on the floating gate through the second gate insulating film (5). A step of forming a control gate (6) made of polycrystalline silicon; and a step of forming a surface of the semiconductor substrate (1a) immediately below the floating gate (4) as a channel region, and the semiconductor substrate (1a) on both sides of the channel region (9). Forming a source / drain region (7, 8) on the surface. There. Further, in the invention described in claim 8, in the second gate insulating film forming step,
By further oxidizing the floating gate
Forming the second gate insulating film.
ing.

The symbols in parentheses of each of the above means are as follows:
It shows the correspondence with specific means described in the embodiments described later.

[0018]

According to the first aspect of the present invention, 2
In a semiconductor device having a layered electrode structure, the thickness of an interlayer insulating film formed between electrode layers is set to 400 ° or less, the first electrode layer is made of phosphorus-doped polycrystalline silicon, and the phosphorus concentration is 2 ×. 10 ²⁰ cm ^-3 one or more 3 × 1
It is set to 0 ²⁰ cm ^-3 or less. Therefore, the amount of segregation of phosphorus from the first electrode layer to the interlayer insulating film can be reduced, so that the withstand voltage of the interlayer insulating film can be improved. The present invention can be applied to a case where an interlayer insulating film is formed by thermally oxidizing a first electrode layer.

According to the second aspect of the present invention, EPRO
In a non-volatile memory such as M, the withstand voltage of the interlayer insulating film between the floating gate and the control gate when the interlayer insulating film is set to 400 ° or less can be improved. In addition,
The floating gate is thermally oxidized.
Can be applied when forming an interlayer insulating film.
You.

According to the third aspect of the present invention, a nonvolatile memory such as the EPROM according to the second aspect can be manufactured. According to the invention described in claim 6, the nonvolatile memory such as the EPROM described in claim 5 can be manufactured. According to the invention described in claim 7,
The phosphorus concentration of the floating gate is set to 3 × 10 ²⁰ cm ⁻³ or less, the amount of phosphorus segregated into the interlayer insulating film can be reduced, the withstand voltage can be improved, and the floating gate is thermally oxidized. Since the second gate insulating film is formed later, the surface convex portion of the floating gate is flattened, the upper and lower edges are rounded, and the dielectric strength of the interlayer insulating film is improved. it can. In this case, the re-emission concentration 2
× 10 ²⁰ cm ^-3 or more. Claims
As shown in FIG. 8 , in the second gate insulating film forming step, the second gate insulating film can be formed by further oxidizing the floating gate.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows a cross-sectional structure of an EPROM. (A) is a cross section in the gate length direction, and (b) is a cross section in the gate width direction. In FIG. 1, a P-type well region 1a is formed in an N-type or P-type silicon semiconductor substrate 1, and an oxide film (hereinafter referred to as LOC) is formed in the well region 1a by LOCOS.
An OS region is formed.

On the element region, a gate oxide film (first gate insulating film) 3, a floating gate (first electrode layer) 4, an interlayer insulating film (second gate insulating film) 5, and a control gate (first gate insulating film) (Two electrode layers) 6 are sequentially laminated, and these are covered with an insulating film 11. An N-type source region 7, a drain region 8 and a channel region 9 are formed in the element region. Further, an Al electrode wiring 10 is formed for the source region 7 and the drain region 8 (the Al electrode wiring of the control gate 6 is not shown in FIG. 1), and a protective film 12 is formed on the entire surface of the device. Have been.

[0023] Here, in this embodiment, with a 330Å thickness of the interlayer insulating film 5, and the phosphorus concentration of the floating gate 4 and about 3 × 10 ²⁰ cm ^-3.
A method of manufacturing the EPROM will be described with reference to FIGS. In these figures, FIG.
The manufacturing process is illustrated by the cross-sectional configuration in the gate width direction.

First, a pad oxide film 3a is formed on a semiconductor substrate 1.
After that, a LOCOS oxide film 2 is formed by a LOCOS method using a nitride film (Si ₃ N ₄ ) 13 to perform element isolation for other element regions (FIG. 2A). Then, after removing the nitride film 13 and the pad oxide film 3a, the gate oxide film 3 is formed and ion implantation is performed to form the channel region 9 (FIG. 2B).

After that, a thickness of 200
A polycrystalline silicon 14 of 0 ° is deposited (FIG. 2C).
After the deposition of this polycrystalline silicon 14, POCl at 900 ° C.
Phosphorus diffusion is performed in _three atmospheres for a time period of 15 minutes, and the phosphorus concentration in the polycrystalline silicon 14 is set to about 3 × 10 ²⁰ cm ⁻³ (FIG. 3A).

Next, the floating gate 4 is formed by selective etching and patterning using a resist mask 15 by photolithography (FIG. 3B). Thereafter, a thermal oxide film 16 is formed by a thermal oxidation method. For example, oxidation is performed at 1050 ° C. at DryO _{2 for} 5 minutes to form a 500 ° thermal oxide film 16 (FIG. 3C).

Next, the thermal oxide film 16 is formed by a wet method, for example,
It is removed by etching with hydrofluoric acid.
Is formed by a thermal oxidation method. For example, 1050 ° C, D
Oxidation is performed for 2 minutes using ryO ₂ to form a 330 ° interlayer insulating film 5 (FIG. 4A). Also, threshold adjustment of peripheral transistors, for example, Nch transistors and Pch transistors is performed by ion implantation.

Then, polycrystalline silicon 6 having a thickness of 3700 ° is formed on the entire surface of the element by the CVD method, and phosphorus is doped in the same manner as the formation of floating gate 4. In this case, the phosphorus concentration in the polycrystalline silicon is about 5 × 1
0 ²⁰ cm ^-3 . Then, patterning is performed using a resist mask to form a control gate 6 (FIG. 4).
(B)).

Thereafter, an oxide film is formed around the control gate 6 again by using thermal oxidation, a source region and a drain region are formed by ion implantation, and an insulating film 11 is formed (FIG. 4C). . Then, a contact hole for forming an Al electrode wiring is formed in the insulating film 11, an Al electrode wiring for a source, a drain, and a control gate is formed. Finally, a protective film 12 is formed to complete the EPROM shown in FIG. You.

According to the above-described manufacturing method, when phosphorus is doped into the polycrystalline silicon 14 for forming a floating gate, the polycrystalline silicon 14 is not heated for 1 hour in a POCl ₃ atmosphere at 900 ° C.
Since phosphorus diffusion is performed for 5 minutes, the phosphorus concentration in the polycrystalline silicon 14 is about 3 × 10 ²⁰ cm ⁻³ from FIG. Therefore, even if the thickness of the interlayer insulating film 5 is set to 330 °, the phosphorus in the floating gate 4 is not in a supersaturated state, and the amount of phosphorus segregated at the interlayer insulating film 5 or at the interface between the interlayer insulating film 5 and the floating gate 4 is small. . Therefore, the withstand voltage characteristics of the interlayer insulating film 5 are as shown in FIG.
Insufficient withstand voltage such as initial failure and intermediate failure can be reduced.

In the above-described manufacturing method, the floating gate 4 made of polycrystalline silicon is oxidized twice during the formation of the interlayer insulating film 5 (FIGS. 3C and 4).
(A)). Therefore, the surface protrusions of the floating gate 4 are flattened by the second oxidation, and the upper and lower edges of the floating gate 4 are improved to have rounded shapes. This can also improve the withstand voltage of the interlayer insulating film 5. .

In the above embodiment, the present invention is applied to an EPRO.
M, but applied to EEPROM, FLAS
The present invention can be applied to a semiconductor device having a two-layer electrode structure such as an H memory, a DRAM, and a two-layer Poly-Si capacitor. In this case, by improving the breakdown voltage of the above-described interlayer insulating film, the charge loss of the nonvolatile memory is reduced, and the two-layer Po
It is possible to obtain effects such as a reduction in charge loss of the ly-Si capacitor and an improvement in capacitance accuracy.

When the present invention is applied to an EPROM, a FLASH memory, or the like, there is an effect that the dielectric breakdown life of the first insulating film serving as a hot carrier injection region is further improved as shown in FIG. In FIG. 10, a constant current is applied between the first electrode layer (floating gate) on the first insulating film (oxide film) and the substrate to measure the dielectric breakdown lifetime of the first insulating film. 9 shows the results of a current TDDB test. In this test, under the condition of a temperature of 30 ° C., the area S of the first insulating film to be a hot carrier injection region was set to 100 μm ² , and the current density was set to −
The life, at which the cumulative failure rate becomes 50% when 10 mA / cm ² is obtained, is multiplied by the current density to obtain the total charge amount Q _BD per unit area that the first insulating film has passed before the failure. I'm trying to get

When the poly-phosphorus diffusion time is changed, the total charge Q _BD changes as shown in FIG. That is, the shorter the 1 Poly phosphorus diffusion time, the more the first
The dielectric breakdown life of the insulating film is improved. This is because, when the concentration of phosphorus in the first electrode layer is increased, phosphorus segregates in the first insulating film or at the interface between the first insulating film and the first electrode layer, whereby the first insulating film It is thought that the dielectric breakdown life of the GaN decreases. Therefore, as shown in the above-described embodiment, 1P
By lowering the phosphorus concentration in the first electrode layer by setting the polyphosphorus diffusion time to 15 minutes or less, the dielectric breakdown life of the first insulating film can be improved.

As an insulating film between the semiconductor substrate and the first electrode layer, an insulating film having a laminated structure of an oxide film and a nitride film or an oxynitride-based insulating film can be used other than the oxide film. . Further, although the interlayer insulating film 5 is formed of an oxide film, the interlayer insulating film 5 may be an insulating film having a laminated structure of an oxide film and a nitride film or an oxynitride-based insulating film.

Further, in the above embodiment, the gate electrode is formed of polycrystalline silicon. However, the gate electrode may have a laminated structure of polycrystalline silicon and a high melting point metal. Note that the same effect as described above can be obtained even when phosphorus is doped into polycrystalline silicon constituting the floating gate and the control gate simultaneously with the formation of polycrystalline silicon.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a cross-sectional structure of an EPROM according to an embodiment of the present invention, wherein FIG. 1A is a cross-sectional view in a gate length direction, and FIG.

FIG. 2 is a manufacturing process diagram of the EPROM shown in FIG. 1, showing a process up to depositing polycrystalline silicon 14;

FIG. 3 is a process drawing showing a step that follows the step of FIG. 2 and shows the steps up to the first oxidation of the floating gate 4;

FIG. 4 is a process diagram showing a process following FIG. 3;

FIG. 5 is a diagram showing the relationship between phosphorus diffusion time and phosphorus concentration.

FIG. 6 is a diagram showing the relationship between the thickness of a second gate oxide film and the withstand voltage.

FIG. 7 is a diagram illustrating a relationship between a phosphorus diffusion time and a sheet resistance of a floating gate.

FIG. 8 (a) is a diagram showing the withstand voltage characteristics when the phosphorus diffusion time is set to 900 minutes at 900 ° C., and FIG. 8 (b) shows the withstand voltage characteristics when the phosphorus diffusion time is set to 15 minutes at 900 ° C. FIG.

FIG. 9 (a) is a diagram showing the withstand voltage characteristics when the phosphorus diffusion time is set to 900 ° C. and the phosphorus diffusion time is set to 26 minutes; FIG.

FIG. 10 is a diagram showing a result of a constant current TDDB test for measuring a dielectric breakdown lifetime of a first insulating film.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate, 2 LOCOS oxide film, 3 gate oxide film, 4 floating gate, 5 interlayer insulating film, 6
... Control gate, 7 ... Source region, 8 ... Drain region, 9 ... Channel region.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-5-259476 (JP, A) JP-A-6-29543 (JP, A) JP-A-8-17949 (JP, A) JP-A-8-949 298295 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (8)

(57) [Claims] 1. A first electrode layer formed on a semiconductor substrate via a first insulating film, and a second electrode formed on the first electrode layer via a second insulating film. In a semiconductor device having a two-layer electrode structure consisting of two layers, the thickness of the second insulating film is 400 ° or less, and the first electrode layer is polycrystalline silicon doped with phosphorus, and has a phosphorus concentration of There one or 2 × 10 ²⁰ cm ^-3 or more 3 × 1
A semiconductor device having a two-layer electrode structure, which is set at 0 ²⁰ cm ⁻³ or less. A first gate insulating film formed on a semiconductor substrate; a source / drain region formed on a surface of the semiconductor substrate; and a first gate insulating film on a channel region between the source / drain regions. 2 × 10 ²⁰ cm ^-3 formed via a gate insulating film
A floating gate made of polycrystalline silicon doped with phosphorus at or One 3 × 10 ²⁰ cm ^-3 inclusive, is formed on the floating gate, the thickness is 400
(4) A semiconductor memory device comprising: a second gate insulating film described below; and a control gate made of polycrystalline silicon formed on the floating gate with the second gate insulating film interposed therebetween. 3. A step of forming a first gate insulating film on a semiconductor substrate, a step of forming a polycrystalline silicon film on the first gate insulating film, and adding 2 × phosphorus to the polycrystalline silicon film. More than 10 ²⁰ cm ^-3
A step of doping at a concentration of 3 × 10 ²⁰ cm ⁻³ or less; a step of patterning the phosphorus-doped polycrystalline silicon film to form a floating gate; Forming a control gate made of polycrystalline silicon on the floating gate via the second gate insulating film; and forming a surface of the semiconductor substrate immediately below the floating gate as a channel region. Forming source / drain regions on the surface of the semiconductor substrate on both sides of the channel region. 4. A first electrode layer formed on a semiconductor substrate via a first insulating film, and a second electrode formed on the first electrode layer via a second insulating film. In the semiconductor device having a two-layer electrode structure including a first layer and a second layer, the second insulating film is formed by thermally oxidizing the first electrode layer and has a thickness of 400 ° or less; the first electrode layer is a polycrystalline silicon doped with phosphorus, one or phosphorus concentration 2 × 10 ²⁰ cm ^-3 or more 3 × 1
A semiconductor device having a two-layer electrode structure, which is set at 0 ²⁰ cm ⁻³ or less. 5. A first gate insulating film formed on a semiconductor substrate, a source / drain region formed on a surface of the semiconductor substrate, and a first gate insulating film formed on a channel region between the source / drain regions. 2 × 10 ²⁰ cm ^-3 formed via a gate insulating film
A floating gate made of polycrystalline silicon doped with phosphorus at or One 3 × 10 ²⁰ cm ^-3 inclusive, on the floating gate, is formed by thermally oxidizing the floating gate, the thickness is less 400Å And a control gate made of polycrystalline silicon formed on the floating gate with the second gate insulating film interposed therebetween. 6. A step of forming a first gate insulating film on a semiconductor substrate, a step of forming a polycrystalline silicon film on the first gate insulating film, and adding 2 × phosphorus to the polycrystalline silicon film. More than 10 ²⁰ cm ^-3
A step of doping at a concentration of 3 × 10 ²⁰ cm ⁻³ or less; a step of patterning the phosphorus-doped polycrystalline silicon film to form a floating gate; and a step of thermally oxidizing the floating gate to form a floating gate. A second layer having a thickness of 400 ° or less on the gate
Forming a control gate made of polycrystalline silicon on the floating gate via the second gate insulating film; and forming a surface of the semiconductor substrate immediately below the floating gate as a channel region. Forming a source / drain region on the surface of the semiconductor substrate on both sides of the channel region. 7. A step of forming a first gate insulating film on a semiconductor substrate, a step of forming a polycrystalline silicon film on the first gate insulating film, and adding 2 × phosphorus to the polycrystalline silicon film. More than 10 ²⁰ cm ^-3
Doping at a concentration of 3 × 10 ²⁰ cm ⁻³ or less; forming a floating gate by patterning the phosphorus-doped polycrystalline silicon film; thermally oxidizing the floating gate; Removing the oxide film formed by the above step; forming a second gate insulating film having a thickness of 400 ° or less on the floating gate; and forming a second gate insulating film on the floating gate through the second gate insulating film. Forming a control gate made of crystalline silicon; and forming a source / drain region on the surface of the semiconductor substrate on both sides of the channel region using the surface of the semiconductor substrate immediately below the floating gate as a channel region. A method for manufacturing a semiconductor memory device, comprising: 8. The method according to claim 8, wherein in the second gate insulating film forming step,
By further oxidizing the floating gate
Forming the second gate insulating film.
A method for manufacturing a semiconductor memory device according to claim 7.