JP3022777B2 - Memory controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller, and more particularly, to a memory controller having a variable current driving capability of an output buffer.

[0002]

2. Description of the Related Art An output buffer circuit having a variable driving capability is known. For example, Japanese Patent Application Laid-Open No. 5-67961 describes an output buffer circuit of this type.
This is shown in FIG. The output buffer circuit 20 supplies a control signal of H level or L level to the control signal input terminal 23 to control the driving capability of the buffer circuit 24 constituting the final output stage in two stages. That is, the buffer circuit 2
4 is turned on when the output line 22 is driven, and the other is turned on together with the one when the output line is driven, or is always turned off, based on a control signal supplied from the outside. To keep. This allows
In this configuration, the driving capability of the output buffer circuit 20 is changed in two stages according to the use conditions.

[0003] In computer systems, the capacity of memories used has become larger and larger, and in particular, memories having a multi-bank configuration tend to be employed. In such a memory having a multi-bank configuration, since the number of banks connected to the output line of the memory controller is large, the load capacity of the output line becomes particularly large. Especially large. In this case, it is conceivable to employ the output buffer circuit described in the above publication.

[0004]

However, the output buffer circuit described in the above-mentioned publication can control the driving capability in two stages. In any case, the output buffer circuit takes into consideration the connected load capacity and the required operation speed. Then, there is no change in selecting a transistor having a driving ability corresponding to the above. That is,
After the output buffer is selected, control in two stages is possible, but the driving capability of the output buffer cannot be changed according to the load capacity.

The present invention provides a memory controller which has an output buffer capable of easily outputting a driving capacity corresponding to a load capacity, thereby simplifying the design of the output buffer and preventing occurrence of a malfunction of the memory. The purpose is to do.

[0006]

In order to achieve the above object, a memory controller according to the present invention is based on an output buffer for outputting a memory control signal and a signal waveform of an output line connected to an output terminal of the output buffer. And a driving capability control signal generating unit for outputting a driving capability control signal, and a driving capability adjusting unit for adjusting the driving capability of the output buffer according to the driving capability control signal.

In a preferred embodiment of the memory controller of the present invention, the output buffer is constituted by a plurality of buffer elements, and the driving capability adjusting means performs the adjustment by selecting the number of the plurality of driven buffer elements. To be configured.

It is also preferable that the plurality of buffer elements comprise an output line charging transistor and an output line discharging transistor, respectively, and that the driving capacity adjusting means controls the charging transistor and the discharging transistor individually. It is an aspect. In this case, a particularly optimal signal waveform is obtained.

According to the memory controller of the present invention, an optimum driving capability can be realized regardless of the magnitude of the load capacity. For this reason, noises such as excessive overshoot and undershoot do not occur, and malfunction of the memory can be prevented.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail based on embodiments of the present invention. FIG. 1 is a block diagram showing a memory system including a memory controller 10 according to an embodiment of the present invention. In this memory system, in this memory system, a large number of commonly connected banks 12 constituting a load of an output buffer 11 of a memory controller 10 are connected to an output line 13 for transmitting a memory control signal.
It is connected to the. In FIG. 1, only one output buffer 11 and one output line 13 are shown for the sake of convenience, but these are arranged by the number of control signals.

The memory controller 10 has a plurality of output buffers 11 each outputting one memory control signal,
A common driving capability detection circuit 15 for detecting the signal waveform of each output buffer 11 and a common output buffer variable circuit 16 for receiving the output of the driving capability detection circuit 15 and controlling the driving capability of the output buffer 11 are provided. Each output buffer 11 is provided with a plurality of buffers 14 connected in parallel.
The plurality of memory control signals include, for example, a column address strobe (CAS) and a row address strobe (RA
S), a write enable signal (WE), an address signal,
And a data signal.

When the memory system is constructed, the driving capability of each output buffer 11 is selected so as to maximize the driving capability regardless of the size of the load capacity of the memory 12, so that the driving capability of the output buffer 11 is optimized. The control to be a value is performed for each control signal. The drive capability detection circuit 15 operates periodically or intermittently, sequentially detects a memory control signal output from each output buffer 11 to the memory 12 via the output line 13, and based on that, detects each output line 1.
The driving capability control signals A and B corresponding to No. 3 are sequentially output. The output buffer variable circuit 16 outputs the driving capability control signal A
And B, control a large number of buffers 14 connected in parallel in each output buffer 11 so that each output buffer 11
Has the function of sequentially adjusting the driving capability of

2 (a) to 2 (d) show signal waveforms of output lines corresponding to each case of the driving capacity of the output buffer, for explaining the operation of the memory controller of FIG. As shown in FIG. 2A, when the output buffer has a large driving capability and an overshoot occurs on a certain output line, the driving capability detecting circuit compares the overshoot with a predetermined reference value. Based on the result of the comparison, predetermined driving capability control signals A and B are output in order to lower the driving capability of the output buffer of the output line in which overshoot occurs by one rank.

The driving capability control signals A and B are sent to an output buffer variable circuit, and the output buffer variable circuit lowers the driving capability of the output buffer by one rank based on the driving capability control signals A and B. That is, the driving of one of many buffers connected in parallel is stopped. This operation is repeated until a signal waveform shown in FIG. 2B is obtained, and a signal waveform without excessive overshoot is obtained.

Further, even when an undershoot occurs in the output line as shown in FIG. 2 (c), the drive capability detection circuit detects the undershoot by comparing it with a predetermined reference value, and the undershoot occurs. In order to lower the driving capability of the output buffer of the output line by one rank, predetermined driving capability control signals A and B are output. Driving ability control signals A and B
Is sent to the output buffer variable circuit, and the output buffer variable circuit lowers the driving capability of the output buffer by one rank based on the control signal. That is, the driving of one of many buffers connected in parallel is stopped. This operation is repeated until a waveform as shown in FIG. 2B is obtained, and a signal waveform without excessive undershoot is obtained.

As shown in FIG. 2D, when the driving capability is too small, the driving capability detection circuit outputs the driving capability control signals A and B to raise the driving capability by one rank. The output buffer variable circuit raises the driving capability of the output buffer by one rank based on the driving capability control signal. That is, the buffer driven in the output buffer is set to 1
Add one.

For example, in the case of a buffer employing a CMOS transistor, a P-channel transistor for charging the output line and an N-channel transistor for discharging from the output line are provided in order to obtain a more optimal signal waveform.
Additional (individual) drive can also be performed. in this case,
The above-mentioned overshoot or undershoot can be individually and substantially reduced to zero.

FIG. 3 is a timing chart showing the waveform of the driving capability control signal in the memory controller shown in FIG. The driving capability control signal is output periodically, for example, at predetermined time intervals. In each output period, the start notice period for notifying the output of the control signal and the control signal for each output line are sequentially output. , And an end notification period for notifying the end of the output of the control signal.

In the start notice period, the drive control signal A is set to the low level and the drive control signal B is sent for four clocks. Thereby, it is notified that an individual drive control signal corresponding to each output line will be output next. In each control signal output period, the control signal A forms a clock, and the driving capability control signal B forming an individual control signal corresponding to one control line is output during two clocks. That is, the individual control signal is configured as a 2-bit signal output during two clocks.

The fact that the individual control signal is at the H level for two clock periods, that is, the individual control signal = (H, H) means that the current driving capability is high and the driving capability needs to be reduced by one rank. . In addition, the fact that the individual control signal is at the H level in the first clock period and at the L level in the next clock period, that is, the individual control signal = (H, L) has a low current driving capability, so the driving capability needs to be raised by one rank Similarly, the individual control signal = (L, L) is
This means that the current driving capability is appropriate. Therefore,
In the case shown, RAS ₀ , RAS ₁ , CAS ₀ , address, and data indicate that the current driving capability is “high”, “low”, “suitable”, “high”, “low”, respectively. ing.

In the end notification period, the driving capability control signal B forms a clock, and the driving capability control signal A
Is set to the H level. This notifies that the output of the drive control signal has ended.

In the output buffer variable circuit, the driving capability of each output buffer is adjusted based on the driving capability control signals A and B. First, the content of the control for increasing, decreasing, or maintaining the current state of the drive capacity for each output line is stored in its internal register, and the number of parallel buffers in each output buffer is determined based on the internal register. Is increased or decreased or maintained. The detection of the drive signal waveform and the adjustment of the drive capability of the output buffer are repeated until an optimal signal waveform is obtained for each control signal.

In the memory controller of the above embodiment, the plurality of output buffers, each of which outputs a memory control signal, have the same configuration itself among output buffers and different memory controllers, while maintaining the optimum configuration. Signal waveforms can be obtained individually. This simplifies the design of the output buffer and prevents malfunction of the memory. Conventionally, it has been difficult to design an output buffer of a memory controller due to the large and variable load capacity of the memory.

In the above-described embodiment, an example is shown in which a common drive capability detection circuit and an output buffer variable circuit are provided for a large number of output lines. One drive capability detection circuit and an output buffer variable circuit may be provided.

As described above, the present invention has been described based on the preferred embodiments. However, the present invention is not limited to the configuration of the above-described embodiment, and various modifications may be made from the configuration of the above-described embodiment. And the modified memory controller,
It is included in the scope of the present invention.

[0026]

As described above, according to the memory controller of the present invention, a memory controller having an appropriate driving capability can be easily realized without individually considering the size of the load capacity of the memory. In addition, noise due to excessive overshoot or undershoot does not occur, and the occurrence of malfunction of the memory can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory controller according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of a drive signal for explaining an operation of the memory controller of FIG. 1;

FIG. 3 is a timing chart showing a waveform of a driving capability control signal in the memory controller of FIG. 1;

FIG. 4 is a block diagram of a conventional output buffer circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Memory controller 11 Output buffer 12 Memory 13 Output line 14 Buffer element 15 Drivability detection circuit 16 Output buffer variable circuit 20 Output buffer circuit 21 Input terminal 22 Output terminal 23 Control signal input terminal 24 Final stage output buffer

Claims (3)

(57) [Claims] 1. A plurality of output buffers each outputting a memory control signal, and a signal waveform of an output line disposed in common with the plurality of output buffers and connected to each output terminal of the plurality of output buffers. A drive capability control signal generating unit for sequentially outputting a drive capability control signal corresponding to each output buffer based on the output buffer; and a drive capability adjustment unit for adjusting the drive capability of each output buffer in accordance with each drive capability control signal. A memory controller characterized in that: 2. The output buffer according to claim 1, wherein each of the output buffers is constituted by a plurality of buffer elements, and the driving capability adjusting means performs the adjustment by selecting the number of the plurality of driven buffer elements. A memory controller as described. 3. The plurality of buffer elements each include an output line charging transistor and an output line discharging transistor, and the driving capability adjusting means controls the charging transistor and the discharging transistor individually. Item 3. The memory controller according to item 2.