JP3018975B2 - ATM protocol processing controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is implemented in a terminal connected to an ATM-LAN and has an SAR function of an AAL layer,
The present invention relates to an ATM protocol processing controller having an ATM layer cell multiplexing / demultiplexing function, and more particularly to a transmission traffic control for realizing a traffic shaping function for a plurality of logical connections.

[0002]

2. Description of the Related Art In an ATM, when a logical connection (VC) that can be uniquely identified by VPI / VCI is set,
Depending on the type of traffic to be transferred on the logical connection, it is possible to request the network and end system for communication quality such as how much delay is allowed and the transmission rate. In practice, four traffic service classes (C
(BR: fixed rate service, VBR: variable rate service, ABR: service that changes the rate in response to network congestion, UBR: unspecified, unguaranteed service) Request transmission rate.

[0003] AT required to connect to ATM-LAN
The M-protocol processing controller needs to realize cell transmission according to the VC according to the service class declared at the time of setting the VC, in accordance with the transmission rate also declared at the time of setting the VC.

As a traffic shaping function supported by an existing ATM protocol processing controller, for example, four rate queues are provided by hardware in correspondence with two priorities, and peak rates are defined in correspondence with the rate queues. A method in which a cell is transmitted by accessing a plurality of VCs registered in a rate queue at a given rate in a round-robin manner, and a VC transmitting a cell from a transmission rate of the entire VC.
Are prepared in advance, and the hardware implements the method by accessing the table at regular intervals and transmitting a cell corresponding to the described VC.

As an ATM protocol processing controller having the traffic shaping function, Tran
Switch's SARA chip, the controller with the function described below, Integrated Device Technology's ATM
There is an SAR chip (IDT77201).

[0006]

However, in such a conventional apparatus, in order to realize transmission traffic control in accordance with a service class and a transmission rate defined by an ATM protocol declared for VC, an ATM protocol is required. It is necessary for the driver of the processing controller to be aware of the transmission rate corresponding to the VC. In addition, when the VC is set, it is necessary to review the schedule of the entire transmission rate.

For example, as in the above-described known example, it is necessary to allocate a peak rate to a rate queue and create a table in advance for a schedule.

In general, a network card connected to an ATM-LAN has a configuration in which a local processor for a driver of an ATM protocol processing controller is not mounted in order to reduce costs. Control needs to be performed.

An object of the present invention is to flexibly cope with traffic control in accordance with various service classes and transmission rates specified by an ATM layer in an ATM protocol processing control.

It is another object of the present invention to implement a traffic shaping function in accordance with a transmission rate declared for VC in both hardware and firmware.

It is another object of the present invention to monitor the total transmission rate on all VCs and to always assign an optimum transmission rate to each VC.

[0012]

SUMMARY OF THE INVENTION The feature of the present invention is that an ATM is used.
The protocol processing controller has means for managing cell transmission intervals in VC units, means for transmitting cells when the cell transmission time has arrived, and means for scheduling when the cell transmission time has arrived simultaneously in a plurality of VCs. A point is that a cell transmission processing unit which is a hardware circuit is provided, and traffic shaping is simultaneously realized for a plurality of VCs.

The ATM protocol processing controller further comprises a memory for storing a CPU core and firmware executed by the CPU core, and a memory for arranging a table used by the firmware. A function to manage the transmission interval,
By having a function of selecting an optimum transmission rate for each VC, a function of monitoring the total transmission rate, and the like, a service class declared for VC, such as Burst Tole, is provided.
One of the features of the present invention is to realize traffic control in accordance with a parameter such as lance and a transmission rate.

Further, one of the features of the cell transmission management section is that it has means for changing the transmission rate every time a plurality of cells are transmitted and means for periodically transferring cells.

With such a configuration, it is possible to realize a traffic shaping function for a plurality of VCs in the cell transmission manager. Further, it is possible to change the cell transmission rate every time a plurality of cells are transmitted. As cell transmission interval management methods, cell transmission at a fixed cycle,
It is possible to select from cell transmission at a fixed time from the completion of cell transmission.

Further, both the cell transmission management unit and the firmware executed by the CPU core can simultaneously realize a traffic shaping function for a plurality of VCs. The processing performed by the cell transmission management unit and the firmware is performed by a data cell and a management cell, or a VC for which a high transmission rate is declared and a V for which a low transmission rate is declared.
C and the like.

For each VC, simply declaring the parameters of the service type defined in the ATM protocol and the transmission rate, the firmware executed by the CPU core
It is possible to calculate the cell transmission interval according to C and manage the transmission of the management cell.

Further, the total transmission rate of the VC being transmitted is monitored, and when the total transmission rate exceeds the transfer band of the transmission line,
The transmission rate can be reduced corresponding to the service class for each VC.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) A first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing an example of the configuration of an ATM card 108 which mounts an ATM protocol processing controller 110 to which the present invention is applied and connects a computer to an ATM-LAN. The computer comprises a main processor 100 and a main memory 102, a processor bus 104 and a PC.
It is connected to the ATM card 108 via the MCIA connection unit 106. The ATM card 108 includes an ATM protocol processing controller 110 having an interface function with a computer and an AAL / ATM function, and a P card having a PHY function.
HY protocol processing controller 114, buffer memory 112 used for cell division / assembly, transformer 116,
A metal cable connector 118 is provided, which is connected to the branch HUB 122 via the metal cable 120 and
It constitutes an M-LAN. The ATM protocol processing controller 110 is a PCMCIA I / F unit 13 that implements a physical interface as PCMCIA.
2. Host I / F for transmitting and receiving control information related to a transmission request from the main processor, a reception report from the ATM card, and the like.
Unit 134, a host DMAC 136 that performs data transfer between the main memory 102 and the buffer memory 112, a cell transmission DMAC 140 that performs cell transmission between the buffer memory 112 and the PHY protocol processor 114, a cell reception DMAC 142 that performs cell reception, and a PHY protocol processing unit 1
An arbiter 138 for controlling buffer memory access competition by the cell transmission / reception interface unit 146, the DMACs 136, 140, 142, or the CPU core 128, and a cell as a hardware circuit for realizing a traffic shaping function at the time of cell transmission. A transmission management unit 148, a CPU core I / F unit 130 that connects the processing unit to the CPU core 128, and a CPU core 12
8. F storing the firmware executed by the CPU core
It comprises a ROM 124 and a RAM 124 in which tables and the like managed by the CPU core are arranged.

FIG. 2 is a diagram showing an example of the configuration of a communication protocol in an ATM and an example of a processing operation defined by the communication protocol. It is assumed that AAL5 is applied as the AAL layer. The ATM card 108 has a C of the AAL layer.
Protocol processing below the PCS layer is executed by the ATM protocol processing controller 110 and the PHY protocol processing controller 114.

The outline of the transmission process and the reception process will be described below.

ATM protocol processing controller 110
Receives the transmission request from the main processor 100, the main processor 100 DMA-transmits the transmission CPCS-PDU prepared on the main memory 102 to the buffer memory 112 using the host DMAC 136. After that, the CPCS-PDU in the buffer memory 112 is divided into 48B, a cell header is added, and transmission is requested to the PHY protocol processing controller 114. Note that the cell transmission DM
The AC 140 calculates the CRC32 while transmitting the cell, and inserts the calculation result of the CRC32 into the trailer of the CPCS-PDU.

ATM protocol processing controller 110
Receives the reception report from the PHY protocol processing controller 114, deletes the cell header from the received cell, and assembles the CPCS-PDU on the buffer memory 112.
The cell reception DMAC 142 receives C while receiving cells.
Calculate RC32, and when CPCS-PDU assembly is completed,
Check C32. When the CPCS-PDU assembly is completed, the host DMAC 136 makes the buffer memory 1
Main memory 102 designated by main processor 100 from 12
The received CPCS-PDU is DMA-transferred upward. After the transfer is completed, the completion of the reception is notified from the ATM protocol processing controller 110 to the main processor 100 by an interrupt or the like.

FIG. 3 shows the configuration of the buffer memory 112. The buffer memory 112 includes a transmission management table 300 used by the ATM protocol processing controller 110 to perform cell transmission processing, a reception management table 312 used for cell reception processing, and a plurality of transmission buffers 314 for storing transmission CPCS-PDUs. (314A, 314
B, 314M) and a plurality of reception buffers 316 (316A, 316B, 3) for storing reception CPCS-PDUs.
16N). The entry 310 of the transmission management table 300 is prepared for a logical connection (VC) that can be identified by the VPI and VCI of the cell header,
Area 302 for saving the calculation result, cell header 304 added at the time of cell transmission, number of transmission cells 306 to be continuously transmitted by the ATM protocol controller, transmission pointer 308 indicating the position of the next transmitted cell payload in the transmission buffer, It consists of. The ATM protocol processing controller 110 implements traffic shaping in the cell transmission management unit 148 using the transmission management table 300.

FIG. 4 is a block diagram showing the function of the cell transmission manager 148 of the present invention. Cell transmission management unit 14
In step 8, the cell transmission interval is managed in correspondence with the VC, and when the cell transmission time is reached, a cell transmission request is issued to the cell transmission DMAC so that various transmission rates (number of cells / second) specified for each VC are obtained. In addition, cell multiplexing of a plurality of VCs is performed to realize traffic shaping. The cell transmission management unit 148 includes a management entry 404 (404A, 4A) for managing the cell transmission interval corresponding to the VC.
04B, 404N), a transmission request register 406 for receiving a 1-cell transmission request from the CPU core 128 to flexibly perform traffic control, and a Cl for cell transmission interval management.
ock 402, a plurality of management entries 404, or C
It comprises a scheduler section 400 for scheduling a cell transmission request from the PU core 128 and a transmission report register 408 for reporting the completion of cell transmission to the CPU core. The number of management entries corresponds to the number of VCs that can be simultaneously managed by the cell transmission management unit. The management entry 404 includes a ctl register 401 (4) for activating cell transmission interval management.
10A, 410B, 410N), and position information (S) of the transmission management table (SMT) 300 provided on the buffer memory.
SMT index register 412 (412A, 412B, 412N) for setting the MT index), and rate value register 414 for setting the cell transmission interval.
(414A, 414B, 414N), count register 416, which is a work area for cell transmission interval management
(416A, 416B, 416N) and c
A timer processing unit 418 (418A, 418B, 418) that manages cell transmission intervals using the out register 416.
N). When activating the cell transmission interval management, the CPU core 128 needs to set the above four registers.

Next, a traffic control method realized by using the cell transmission management unit 148 will be described with reference to processing flows shown in FIGS. In these flows, the processes of the timer processing unit 418, the scheduler unit 400, and the cell transmission DMAC 140 of the cell transmission processing unit 148 are shown.

FIG. 5 is a process flow showing the counting process of the timer processing unit 418. When a signal is input from the Clock 402 for a predetermined time, for example, every μsec, it is checked whether or not an activation request has been issued to the management entry 404 from the set value of the ctl register 410 (502). If there is no activation request, the process ends.
The set value of the nt register 416 is checked, and if "0", the process is terminated (504).
“1” is subtracted from the set value of the unt register 416 (5
06). Thereafter, the setting of the count register 416 is checked again (508), and if "0", a time out signal is issued to the scheduler unit 400 (51).
0). At the same time, the SMT index
0 (510). The timer processing unit 418 stops the processing until there is a restart request from the scheduler unit 400 (514).

6 and 7, the scheduler section 400
5 is a processing flow showing a scheduling process of FIG.

FIG. 6 is a processing flow when the scheduler section 400 performs a random scheduling process for starting cell transmission. The presence or absence of the Time out signal from the timer processing unit 418 of each management entry 404 and (602,
604, 606), the CPU core 128 continues to check the setting (608) of the transmission request register 406 in order, and if there is a cell transmission request, the cell transmission DMAC 140
Is started (610). By repeatedly performing the above-described scheduling processing, a plurality of Time out signals from the timer processing unit 418 of each management entry 404 and C
A cell transmission request by the setting of the transmission request register by the PU core is randomly received, and the cell transmission request for a plurality of VCs is treated equally.

FIG. 7 is a processing flow in the case where the scheduler section 400 performs scheduling processing with a priority function for starting cell transmission. The priority is the management entry 404
It is assumed that the smaller number has the higher priority (the management entry 1 404A has a higher priority than the management entry 2 404B, and the management entry n-1 has the management entry n,
404N). Schedule section 40
In the case of 0, first, the timer processing unit 418 of the management entry 404
Check the Time out signal from the
2). If there is no Time out signal, the CPU core 1
It is checked whether or not the transmission request register 406 has been set (step 608).
140 is started (610). If there is a Time out signal, Time out is sequentially assigned from the management entry 1.
The presence or absence of a signal is checked (602, 604), and if there is a cell transmission request, the cell transmission DMAC 140 is started (6).
10). Cell transmission DMAC 14 for one management entry
After the activation, the CPU core 128 checks the setting of the transmission request register 406 (608). If there is a cell transmission request, the cell transmission DMAC 140 is activated (610), and the time from the timer processing unit 418 of the management entry 404 is returned.
Cell transmission by the out signal and cell transmission by the setting of the transmission request register 406 by the CPU core 128 are performed alternately. By repeatedly performing the above-described processing, the scheduling processing supporting the priority order is realized.

FIG. 8 is a processing flow showing the cell transmission DMAC activation processing in the scheduler section 400. After starting by passing the SMT index to the cell transmission DMAC 140 (702), it waits until the transmission of one cell is completed (704). Cell transmission DMAC 140
When a signal indicating that the cell transmission has been completed and the number of transmitted cells of the SMT has become "0" is received, a stop request is issued to the timer processing unit (706, 708, 710). The transmission report register 408 is loaded with the SMT index (7
12) An interrupt signal is issued to notify the CPU core 128 (714). When only the cell transmission completion signal is received from the cell transmission DMAC 140, a restart request is issued to the timer processing unit (716, 718, 720).

FIG. 9 is a processing flow showing the cell transmission completion processing of the timer processing unit 418. Scheduler section 400
When the request is received, the timer processing unit 418 recovers from the stop state, and depending on the type of the request (802), if the request is a restart request, the rate val of the management entry 404
The value set in the ue register 414 is stored in the count register 41.
6 (804), and if the request is a stop request, the ctl register 410 of the management entry 404 is set to "inactive".
e "(806).

FIG. 10 is a processing flow showing the processing of the cell transmission DMAC 140 activated by the scheduler section 400. SMT specified by scheduler unit 400
48 bytes are read from the transmission pointer 308 in the entry 310 of the SMT 300 indicated by the index, a cell header 304 is added before the read data to create a cell, and DMA transfer is performed to the cell transmission / reception I / F unit 146 by DMA (90
2). 48 bytes are added to the transmission pointer 308 in the entry 310 (904), and “1” is obtained from the transmission cell number 306.
Is subtracted (906). The value of the number of transmission cells 306 is checked (908).
To the transmission completion and the transmission cell number “0” (910),
If it is not "0", only the transmission completion is notified to the scheduler section 400 (912).

Next, a processing flow of firmware executed by the CPU core 128 when using the function of the cell transmission management unit 148 will be described with reference to FIGS.

FIG. 11 is a processing flow of the firmware when the cell transmission management for the VC is performed using the management entry 404. SMT3 on the buffer memory 112
The transmission buffer 314 head address is set in the transmission pointer 308 of the entry 310 corresponding to the VC in 00 (1).
002), the transmission buffer 31
4 is set (1004). SMT is stored in the SMTindex register 412 of the management entry 404.
The position information of the entry 310 of 300 is set (100
6). The cell transmission interval is calculated (1008), and the calculated value is set in the rate register 414 and the count register 416 of the management entry (1010, 101).
2,1014). After that, “A” is stored in the ctl register 410.
"active" is set, and cell transmission management is performed by the timer processing unit 418 (1016).

FIG. 12 is a flow chart showing processing when cell transmission management is performed by firmware. The clock is defined by the firmware, and the next cell transmission time is calculated in advance from the transmission rate. One cell transmission processing is performed for a VC whose next cell transmission time exceeds the current time (110).
2). The position of the data to be transmitted is set to the transmission pointer 308 of the entry 310 corresponding to the VC of the SMT 300 (1104), and "1" is set to the number of transmission cells 306 (1106). SMTind in the transmission request register 406
ex and the scheduler unit 4 of the cell transmission management unit 148
00 is requested to activate the cell transmission DMAC (1108).
Thereafter, if there is a cell to be transmitted, the next cell transmission time is calculated from the transmission rate (1110).

FIG. 13 shows the firmware processing when an interrupt from the cell transmission management unit 148 is accepted. When the cell transmission management is performed using the management entry 404, the transmission buffer 314 is released and set to the empty state (1202, 1204), and if there is an untransmitted transmission buffer, the cell transmission is performed using the management entry 404. Is performed (1206). When the management entry 404 is not used (when cell transmission is requested from the transmission request register according to FIG. 11), if all data in the transmission buffer 314 has been transmitted, the transmission buffer is released (120).
2, 1208, 1210). For the next cell transmission,
According to the flow of FIG.

As shown in this embodiment, in the ATM protocol processing controller 110 in which the cell transmission management unit 148 having the above-described functions is mounted, the cell transmission to the VC managed by the cell transmission management unit 148 is executed by the CPU core. Since cell shaping can be performed together with cell transmission from firmware, the cell transmission management function of the cell transmission unit is used for VCs with a high transmission rate, and the firmware is used for firmware for VCs with a low transmission rate. It is possible to perform cell transmission management. Further, even for simultaneous transmission of a number of VCs exceeding the number of management entries held by the cell transmission management unit 148, the cell transmission can be managed by the firmware, so that the number of simultaneously transmittable VCs is not limited by hardware. .

(Embodiment 2) A second embodiment of the present invention will be described with reference to FIGS.

FIG. 14 is a diagram showing a method of managing the cell transmission interval in the cell transmission manager 148. The management method of the timer processing unit of the cell transmission management unit shown in the first embodiment is the same as that of FIG.
This corresponds to the restart method of No. 4. In this system, the timer processing unit 4 receives a restart request from the scheduler unit 400 that has received the cell transmission completion notification from the cell transmission DMAC 140.
18 starts counting the cell transmission interval again. When a Time out signal to the scheduler unit 400 is issued from two management entries 404 simultaneously (the management entries 1 and 404A and the management entries 2 and 40 in FIG. 14).
4B), the scheduling function of the scheduler unit 400 uses the management entries 2 and 40 as shown in FIG.
After receiving the request for request of 4B and transmitting the cell, the cell of the management entry 1404A is transmitted. For this reason, two
When two Time outs occur, the interval at which the actual transmission is performed is delayed by Δt from the cell transmission interval registered in the management entry 1404A. The magnitude of Δt is about 2.7 μsec when the transmission speed of the line is 155 Mbps.

After the delay has occurred, the restart method for counting the cell transmission interval from that time is in accordance with the Virtual Scheduling Algorithm specified by the UNI. In the new data transmission, as shown in the free-run method in FIG.
Although a certain amount of change in the transmission interval is permitted, periodic transfer of cells at a constant interval is always required from the start of transfer.

The free-run system for realizing a constant cell transmission interval shown in FIG. 14 is implemented by the timer processing unit 418 shown in FIGS.
And the processing flow of the scheduler unit 400.

FIG. 5 is a process flow showing the counting process of the timer processing unit 414. Upon receiving the signal from the Clock 402, the timer processing unit 418 starts the processing described in the first embodiment (502, 504, 506, 508). After issuing a Time out signal to the scheduler unit 400 (510), the VC using the management entry 404
Requesting the free-run system, the rate register is stored in the count register 416 without stopping the timer processing unit.
The set value of the value register 414 is loaded, and a count process is subsequently performed (512, 516).

FIG. 8 is a processing flow showing the cell transmission DMAC activation processing in the scheduler section 400. When the cell transmission completion signal is received from the cell transmission DMAC 140 (the number of transmission cells of the SMT 300 is not “0”), in the case of the free-run system, the timer processing unit has already started counting the next cell transmission time. It is not necessary to issue a restart request to the timer processing unit.

As shown in the present embodiment, the cell transmission management unit manages the time of the cell transmission interval by the free-run system, and realizes the periodic transfer for data transfer such as voice and video.

(Embodiment 3) FIG. 1 shows a third embodiment of the present invention.
This will be described with reference to FIGS.

FIG. 15 is a diagram showing the configuration of the cell transmission manager 148 of the present invention. The cell transmission management unit 148 includes a plurality of management entries 404, a scheduler unit 400, a transmission request register 406, a reception report register 408, and a Clock.
402, a rate setting processing unit 1402 for loading a new cell transmission interval for each of a plurality of cells into a rate value register 414 of the management entry.

FIG. 16 shows the configuration of the buffer memory 112. The buffer memory 112 stores the transmission management table 30
0, reception management table 312, multiple transmission buffers 31
4, a plurality of reception buffers 316, a rate entry 15 capable of setting a plurality of cell transmission intervals to be changed for each transmission of a plurality of cells
08 (1508A, 1508B). The rate entry 1508 is prepared for each VC.
The pointer information is managed by the entry 310 of the SMT 300 corresponding to the VC. Entry 31 of SMT300
0 is used as a CRC result 302, a cell header 304, a transmission cell number 306, a transmission pointer 308, a continuous transmission number 150 for setting how many cell transmission intervals a cell transmission interval is changed, and a cell transmission counter of the cell transmission DMAC 140. Number counter 1504, rate entry 15
It is composed of a rate entry pointer 1506 that manages the 08 pointer information.

When performing cell transmission management using the management entry 404, the firmware executed by the CPU core 128 sets the transmission pointer 308 of the SMT 300, the number of transmitted cells 306, and the register of the management entry. In addition, when changing the cell transmission interval for each transmission of a plurality of cells, a plurality of cell transmission intervals are set in the rate entry 1508, and S
The head address of the rate entry is set in the MT rate entry pointer 1506, and the number of cells to be transmitted at the same cell transmission interval is set in the continuous transmission number 1504. For example, when the cell transmission interval is changed for each cell transmission, “1” is set to the continuous transmission number 1502 of the SMT 300.

FIG. 17 is a diagram illustrating the rat transmission of the cell transmission management unit 148.
5 is a processing flow showing processing of an e setting processing unit 1402.
The scheduler section 400 activates the rate setting processing section 1402 in the transmission DMAC activation processing, and executes the SMT index
Pass x. This processing is performed in the part of processing A722 in FIG. In response to this, the rate setting processing unit 1402 activates the cell transmission DMAC 140 by passing the SMT index in order to transfer the rate value in the rate entry 1508 on the buffer memory 112 (160).
2). Upon receiving the transfer of the rate value, the rate setting processing unit 1402 loads the rate value into the rate value register 414 of the management entry 300 corresponding to the SMT index (1604, 1606).

FIG. 18 is a processing flow showing the rate value transfer processing by the cell transmission DMAC 140 started by the rate setting processing unit 1402. rate setting processing unit 1
SMT indicated by SMT index specified from 402
Rate entry pointer 1 in 300 entries 310
The rate value is read from 506 and the rate setting processing unit 1
DMA transfer is performed to 402 (1702). Entry 310
It is checked whether or not the continuous number counter 1504 in “1” is “0” (1704).
Is loaded into the continuous number counter 1504 (17).
06). "1" is subtracted from the continuous number counter 1504 (1708), and only when the continuous cell number counter 1504 becomes "0", the rate entry pointer 1506 is updated to point to the next rate value (1710, 171).
2).

As shown in this embodiment, since the cell transmission manager can change the cell transmission interval for each of a plurality of cell transmissions, the transmission rate can be changed even during 1 CPCS PDU transfer, and flexible traffic control is realized. I do.

(Embodiment 4) FIG. 1 shows a fourth embodiment of the present invention.
This will be described with reference to FIGS. 9 to 21.

FIG. 19 shows an example of the configuration of a transmission traffic management table 1802 created on the RAM 126 in order to control the transmission traffic for a plurality of VCs in the firmware executed by the CPU core 128. The transmission traffic management table 1802 stores CBR, V for each VC.
Area 1804 indicating a service class such as BR, area 1806 indicating the current transmission rate, counter 1808 for the number of continuous transmission cells, PCR (peak cell rate), SCR
(Sustainable cell rate), ACR (Availabel ce
ll rate), MCR (Minimum cell rate), burst and other traffic management parameter groups 1810.

For example, when CBR is selected as the service class, for example, PCR is defined as the traffic management parameter 1810, and PCR is set as the current rate 1806. In VBR, for example, PCR, SCR, and burst are defined as the traffic management parameters 1810. In order to monitor the burst, the continuous transmission cell number 1808 is used. As the current rate 1806, either PCR or SCR is set. In ABR, traffic management parameters 1810 include, for example, MCR, PC
R, ACR, etc. are defined. ACR is defined in accordance with ABR, reflecting the congestion state between MCR and PCR,
This ACR is set as the current rate 1806.

The traffic control performed by the firmware executed by the CPU core 128 will be described with reference to FIGS.

FIG. 20 shows a processing flow of the cell transmission interval defining processing corresponding to the service class. CPCS-PD
When the transmission request of U is received, a transmission rate corresponding to the service class of the VC is selected as follows, and the management entry 40 of the cell transmission management unit 148 is selected from the selected transmission rate.
Rate value register 414 in 4
The cell transmission interval set in the t register 416 is calculated (1920). When the service class of the VC is CBR (1902), the PCR is set to the current rate 1806 of the transmission traffic management table 1802 (1904).
In the case of VBR (1906), if the number of continuous transmission cells 1808 is larger than the number of bursts, the current rate 1806 is set to SC.
R is set to (1908, 1912), otherwise, PCR is set (1910). In the case of ABR, first, the presence or absence of ACR reduction is checked (1914), and if necessary, the ACR is reduced (1916). The ACR is set to the current rate 1806 (1918).

FIG. 21 is a flowchart of the overall rate monitoring process performed each time the ATM protocol processing controller 110 receives a transmission request. V that received the transmission request
To check if cell transmission is currently being performed on C,
Current rate 19 in transmission traffic management table 1802
Check whether 06 is "0" (200
2). When transmission is being performed, the current transmission rate is registered in the current rate 1806 of the transmission traffic management table 1802. If the transmission has not been performed, the transmission rate is set to the current rate 1806 of the traffic management table 1802 according to FIG. 19 (2004). It is checked that the sum of the current rates 1806 in the traffic management table 1802 is equal to or less than the transmission bandwidth (200).
6). If the transmission speed of the transmission path is 155 Mbps, the transmission band is about 365 kcell / sec. If the transmission band is exceeded, the current rate is reset for all VCs currently transmitting to guarantee the transmission rate. When CBR is selected as the service class, the current rate is not changed (2008). In the case of VBR, the current rate is set to SCR (2010, 2012). In the case of ABR, the current rate is set to MCR, and the MCR is set in the ACR of the traffic management parameter 1810 of the traffic management table 1802 (2014).

As shown in the present embodiment, the firmware executed by the CPU core can perform processing corresponding to various service classes by using the cell transmission management unit 148. In addition, by performing band control, it is possible to guarantee a transmission rate specified for VC.

[0061]

According to the present invention, the SAR function of the AAL layer, which is implemented in a terminal connected to the ATM-LAN,
In an ATM protocol processor having a layer cell multiplexing / demultiplexing function, in addition to a cell transmission / reception function, a means for managing a cell transmission interval for VC, a means for scheduling a cell transmission request, and a means for receiving a cell transmission request. By providing a cell transmission management unit, which is a hardware circuit having a means for transmitting cells by means of a cell, and a CPU core, it is possible to perform traffic control corresponding to a service class declared for VC and a transmission rate.

Further, the traffic shaping function according to the transmission rate specified for each VC can be realized by both the cell transmission management unit and the firmware executed by the CPU core for a plurality of VCs.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of an ATM card on which an ATM protocol processing controller to which the present invention is applied is mounted.

FIG. 2 is a diagram illustrating an example of a communication protocol configuration in an ATM and an example of a processing operation defined by the communication protocol.

FIG. 3 is a diagram illustrating a configuration example of a buffer memory;

FIG. 4 is a diagram illustrating a configuration example of a cell transmission management unit according to the present invention.

FIG. 5 is a flowchart illustrating a count process in a timer processing unit.

FIG. 6 is a flowchart showing a random scheduling process in the scheduler unit.

FIG. 7 is a flowchart illustrating scheduling processing with priority in the scheduler unit.

FIG. 8 is a flowchart illustrating a cell transmission DMAC activation process in the scheduler unit.

FIG. 9 is a flowchart showing a cell transmission completion process in a timer processing unit.

FIG. 10 is a flowchart showing a cell transmission process in a cell transmission DMAC.

FIG. 11 is a flowchart illustrating processing when a management entry is used in firmware executed by a CPU core.

FIG. 12 is a flowchart illustrating a cell transmission management process in firmware executed by a CPU core.

FIG. 13 is a flowchart illustrating transmission completion processing in firmware executed by the CPU core.

FIG. 14 is a diagram illustrating a method of managing a cell transmission time in a cell transmission management unit.

FIG. 15 is a diagram illustrating a configuration example of a cell transmission management unit according to the present invention when a transmission rate is changed for each transmission of a plurality of cells.

FIG. 16 is a diagram illustrating a configuration example of a buffer memory when a transmission rate is changed for each transmission of a plurality of cells.

FIG. 17 is a flowchart illustrating a process of a rate setting processing unit.

FIG. 18 is a flowchart showing a rate value transfer process in a cell transmission DMAC.

FIG. 19 is a diagram illustrating a configuration example of a transmission traffic management table.

FIG. 20 is a flowchart showing a cell transmission interval defining process corresponding to a service class in firmware executed by the CPU core.

FIG. 21 is a flowchart showing an overall rate monitoring process in firmware executed by a CPU core.

[Explanation of symbols]

108 ATM card 110 ATM protocol processing controller 112 Buffer memory 114 PH
Y protocol processing controller, 128 CPU core,
130: CPU I / F, 136: Host DMAC,
138: Arbiter, 140: Cell transmission DMAC, 142
... Cell reception DM, 146 ... Cell transmission / reception I / F section, 148
... Cell transmission management unit, 300 ... Transmission management table, 400
... Scheduler unit, 402 Clock, 404 management entry, 406 transmission request register, 408 transmission report register, 410 ctl register, 412 SMT
index register, 414 ... rate value
Register, 416 ... count register, 418 ... timer processing unit, 1402 ... rate setting processing unit, 1508 ...
Rate entry, 1802 ... Transmission traffic management table

────────────────────────────────────────────────── ─── Continuation of front page (56) References Hiroshi Shimizu et al. “ATM-LAN” (7.5.1995), Soft Research Center, P.S. 115-116 and P.E. 200-203 (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 12/28

Claims (3)

(57) [Claims] An interface circuit for a host computer interface circuit, a buffer memory for holding transmission / reception data, an interface circuit for a PHY protocol processing controller for connection to an ATM-LAN, a main memory in the computer, and the buffer A first data transfer device for transferring data between memories, a second data transfer device for transmitting a packet in the buffer memory as a 53-byte cell, and a received cell as a packet on the buffer memory Third data transfer device and CPU
A core, a first memory for storing firmware that the CPU core executes, data which the CPU core used
In ATM processing controller and a second memory for storing data, the plurality logical connections, the function of managing the cell transmission interval logical connection unit, wherein
During cell transmission by firmware executed by CPU core
An interface for setting an interval, a function for requesting cell transmission when the cell transmission time arrives , and
Means for storing a cell transmission request, and managing a cell transmission interval;
At least one of the logical connections
Performs scheduling of one or more cell transmission requests and cell transmission requests from firmware , and selects the selected cell transmission request.
Requesting the second data transfer device for cell transmission according to
ATM protocol processing controller, characterized in that it comprises a hardware circuit having a that function. 2. An ATM protocol processing controller according to claim 1.
And the ATM protocol processing controller.
PHY protocol processing controller with interface function
AT having a controller, a transformer, and a cable connector
M communication adapter. 3. Physical interface as PCMCIA
Equipped with a host computer interface circuit for realizing
2. The ATM protocol processing controller according to claim 1,
And the ATM protocol processing controller.
PHY protocol processing controller with interface function
, PCMC having transformer, cable connector
IA-compliant ATM communication card.