JP2970598B2 - ATM controller that automatically selects the optimal size reception memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is implemented in a router device or an adapter card and uses an ATM (Asyncronous Transaction).
fer Mode; Asynchronous transfer mode) A that realizes the transmission method
More particularly, the present invention relates to an ATM control LSI having a function of detecting a cell to be received and temporarily storing the cell in a reception buffer memory.

[0002]

2. Description of the Related Art In an ATM transmission system, a transmitting device includes:
The packet having an arbitrary length is divided into a fixed length of 48 bytes, and a header of 5 bytes is added to each of the divided packets to form a 53-byte cell.

Each time the cell arrives, the receiving device determines whether the cell should be received, performs appropriate processing such as header separation and error code checking, and then transfers the cell to the reception memory. To recover the packet.

[0004] In such an ATM transmission system, cell discarding may occur due to a difference in cell processing capability inherent in a transmission / reception-side transmission device. One of the causes of cell loss is a reception buffer memory underrun on the receiving side.

[0005] The reception buffer memory underrun is
When the receiving buffer memory in the device is completely consumed,
This occurs when the next cell arrives before refilling the memory and the storage destination cannot be obtained.

When a cell is discarded due to an underrun state, the packet is retransmitted, and the retransmitted packet traverses the line, resulting in inefficient use of the line.

Normally, as shown in FIG. 2, a receiving side of a transmission apparatus using the ATM transmission system mainly has an ATM control LSI 3 for realizing a part of the ATM protocol function by hardware, and a table for storing a reception memory address. Table memory 4 used as a control of the controller,
And a CPU 5 for managing the memory, and a memory 6 for storing the received packets.

The software executed by the CPU 5 first secures a reception buffer memory area for storing reception data, and stores the address information in the ATM controller LSI 3.
Is set in Table 4 to be accessed.

Each time a cell arrives, the ATM controller LSI 3 accesses the table memory 4 to acquire and transfer the address of the receiving memory 6 for storing the cell data. When the remaining amount of the reception memory area becomes small, the ATM control LSI 3 issues an alarm to the CPU 5 through means such as an interrupt signal. CPU that received the warning
5 executes addition and replenishment of memories.

An underrun does not occur if the process of replenishing the memory performed by software by the CPU 5 is sufficiently quicker than when the free space of the receiving buffer memory reaches zero (0). However, when the number of channels extending to the partner station increases, the number of reception buffer memories also increases, the frequency of replenishment increases, and the processing of the CPU 5 becomes more severe.

The frequency of replenishment of the memory by the CPU depends on the size of the memory capacity allocated to the reception buffer memory in advance, the setting of a boundary line for notifying an alarm, and the incoming cell rate.

[0012] The memory capacity to be mounted on the own station device, and C
Although the processing speed of the PU can be grasped, the cell rate from the partner station differs depending on the transmission capacity of the partner station, the application running on the higher rank, etc. There are many.

It is desirable to secure a sufficient memory area so as to be able to handle any cell rate channel. However, mounting a large number of memories increases the cost of the system, and therefore, should be avoided, and a method for effectively utilizing the limited memory capacity is required.

In the prior art, the allocation of the memory capacity is often determined by estimating the number of channels to be established with the partner station or the rate of each channel from the environmental conditions in which the device is introduced.

[0015] Among the packets exchanged with the other station, the VPI / VCI (virtual path identity) is used.
Signaling packet, resource management cell, OAM (Operation, Administratio) that can be grasped from the value of fier / virtual channel identifier
Since it can be understood that the size of a packet is small for an (n, Maintenance) cell or the like, a relatively small reception buffer memory is prepared to store the packet.

For a channel for exchanging other general data, a unitary fixed size is allocated. Thus, a reception buffer memory having a plurality of types of sizes is prepared statically.

Further, the cell rate allowable by the apparatus and the number of channels that can be simultaneously established can be grasped from the set memory capacity and the processing capacity of the CPU.

The partner station and the own station are both CAC (Connection
If the Admission Control) control method is supported, the cell discard rate is estimated when a channel connection request is issued from the partner station, and when the cell discard rate becomes equal to or less than a predetermined allowable cell discard rate. There is also a method that permits only connection.

[0019]

According to the conventional memory setting method in the ATM controller, the reception buffer memory area is fixedly assigned to any channel from a predetermined memory resource, or the rate is determined in advance. Assigned based on guesswork.

[0020] Of these, when the assignment is fixed,
Since the cell rate is high, the reception buffer memory where replenishment processing occurs frequently cannot use the reception buffer memory that has sufficient capacity due to the low speed, and the memory can be used according to various cell rates. Space cannot be allocated efficiently. The empty memory area cannot be used depending on the cell speed and type of the channel.

In the latter case, if there is a large difference between the predicted rate and the actual cell rate, it is possible that memory replenishment may not be in time.

When a limited memory capacity is allocated to each channel as a reception buffer memory, a large capacity is used for a channel having a high cell rate in order to reduce software processing of the CPU and to avoid underrun. It is desirable that the receiving buffer memory is allocated a small receiving buffer memory for a channel having a low rate.

Accordingly, the present invention has been made in view of the above problems, and has as its object to reduce the number of CPU processes and the frequency of underruns. An object of the present invention is to provide an ATM controller for automatically selecting a reception buffer memory having an appropriate size according to a cell rate.

[0024]

In order to achieve the above object, an ATM controller of the present invention is mounted on a router device or an adapter card on an ATM network, and determines whether or not to receive an incoming cell. after the processing, such as checking a header separation and error codes, the size from each other
Is holds the remaining amount of the different address information and the respective receive buffer memory for each receive buffer memory to the table, the ATM controller for restoring the transferred packet according to the address information, the received cell of a plurality of channels at the same time If the means for a certain period observed cell rate of each channel of the plurality of channels, said tape
On the information obtained by the table address information and the means
Based on the cell rate of each channel
The address of each of the receive buffer memories,
Means for automatically selecting the reception buffer memory suitable for each channel in association with each other.

[0025]

Embodiments of the present invention will be described below. In the embodiment of the present invention, an ATM controller mounted on a router device or an adapter card of a terminal on an ATM network observes a cell interval time for each reception channel, and responds to the cell rate grasped thereby. The CPU is characterized in that the CPU is provided with a means for selecting an appropriate one from among the reception buffer memories prepared by dividing the size stepwise in advance.

In the embodiment of the present invention, the interval between cells actually arriving is monitored, the cell rate of the channel is grasped, and the cell buffer is prepared from the reception buffer memory prepared in advance in steps of different sizes. A large receiving buffer memory is allocated to a channel with a high rate, and a small receiving buffer memory is allocated to a channel with a low rate.

Thus, by dynamically selecting a suitable receiving buffer memory according to the cell rate of the channel, it is possible to avoid an urgent need for the CPU to replenish the memory and to reduce the possibility of underrun. It contributes not to reduce the transmission line utilization efficiency. Further, the memory resources can be used efficiently.

That is, a channel having a slow cell rate is not unnecessarily sharing a large reception buffer memory, and a useless empty area is reduced. Further, since a small cell receiving buffer memory is not provided for a fast channel, the CPU does not need to frequently replenish the memory capacity.

[0029]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

The ATM controller according to one embodiment of the present invention monitors the cell rate, and selects an optimum one from among the receive buffer memories prepared in a plurality of sizes according to the obtained cell rate. It incorporates possible means.

FIG. 1 is a block diagram of an ATM transmission device 1
FIG. 3 is a diagram illustrating a configuration of an embodiment when the present invention is applied to a TM controller.

Referring to FIG. 1, before starting reception, C
The software executed by the PU 5 secures a reception buffer memory area for storing received data in the memory 6 in advance.
One reception buffer memory area includes a data buffer 7 in which received data is actually stored, and a pointer area 8 in which a plurality of addresses pointing to the data buffer are bundled.

At the last stage of each pointer area, a link pointer pointing to the next pointer area is set.
Each pointer is linked in a chain.

Although the number of reception buffer memory areas depends on the number of reception channels and the amount of memory mounted on the apparatus, this embodiment exemplifies a case where three reception buffer memory areas are prepared.

The reception buffer memory area 1 is assumed to store data of a channel having a high cell rate and a large size of one packet, and has a number of pointer areas and a data buffer in which one pointer area is bundled. Is increased, and the size of each data buffer itself is also ensured large. The remaining reception buffer memory 2 and reception buffer memory 3 are also set at the same time, but the number of pointer areas, the number of data buffers bundled in the pointer area, and the size of the data buffer itself are as follows: (Reception data buffer 1) > (Reception data buffer 2)> (Reception data buffer 3)

Subsequently, the processing of the CPU 5 stores an address indicating the head pointer area of the reception buffer memory area in a table accessed by the ATM controller 3.
Set in memory 4.

At this time, the position of the address to be set in the table memory 4 determines the position to be set according to the size of the reception data buffer area. That is, the setting method is restricted so that the ATM controller 3 can determine the size order of the reception buffer memory.

In the present embodiment, the reception buffer having the largest size is stored in the table memory 4 in ascending order of address.
The memory 1 is set as the reception buffer memory 2 at the next address.

The table memory 4 is provided with an unused pointer area of each reception buffer memory area and an area for storing the size of the data buffer, and the CPU 5 sets initial values.

Further, in this area, a warning level is set for each of the reception buffer memory areas to warn when the remaining number of unused pointer areas reaches there.

In the case of the reception buffer memory 1, since the cell rate is high, the warning level is set with a sufficient margin.

In this embodiment, the ATM controller 3
A three-channel connection of A, B and C is established with the partner station 2. Originally, full-duplex communication should be performed between the local station and the partner station 2 and a transmission / reception channel should be established. However, since the present invention relates to reception, a diagram and description regarding processing on the transmission side will be described. Omitted.

The cell of channel A means a channel having a relatively high cell rate because a large number of cells are transmitted per unit time, followed by the middle stage of channel B and the low speed of channel C.

Upon receiving the cell, the ATM controller 3 of the own station temporarily stores the cell in the built-in FIFO 3-1.

The cell stored in the FIFO 3-1 is compared with the VPI / VCI field in the header and the contents of the header table 3-2 provided in the ATM controller 3 to determine whether there is a matching VPI / VCI. It is checked whether it is.

If there is no matching header, it is determined that a cell of a new channel has arrived, and the VPI / VCI value is set in the header table 3-2. At this time, the value of the timer 3-3 at the time of the incoming call is stored together.

Timer 3 built in ATM controller 4
-3 is a counter that counts up as needed, and plays a role of a clock for measuring a cell interval.

The same VP is already stored in the header table 3-2.
When the I / VCI exists, the cell rate of the channel can be known by referring to the counter value of the timer 3-3 again and comparing it with the previous value.

The ATM controller 3 selects a reception buffer memory corresponding to the interval time between cells.

For example, when the observed cell interval is determined by the timer 3
If the count value of "-3" is "50", the ATM controller 3 selects the reception buffer memory 1 in which the pointer is stored at the youngest address of the table memory, and counts the value of the timer 3-3. Is "100", the reception buffer memory located at the second position is
If the count value of the timer 3-3 is "150" or more, the pointer area address of the reception buffer memory 3 is obtained.

At this time, means for arbitrarily setting the correspondence between the cell interval value and the memory address can also be provided.

If the incoming cell rate is a fixed rate that does not change with time, the cell rate can be known by measuring the interval between the first cell and the second cell. , It is necessary to measure the interval between a plurality of cells.

In this case, it is conceivable to measure the number of cell intervals and take statistics. However, during that time, the data cannot be transferred to the reception buffer memory, so that the ATM controller 3
It is necessary to increase the built-in FIFO.

Further, as means for observing the cell rate, means for obtaining a peak cell rate and an average cell rate within a predetermined observation period as described in, for example, JP-A-8-191309. Etc. are referred to. This method can also be applied.

Since the cell of channel A arrives and the interval between the first cell and the second cell is less than or equal to "50" in the count value of the timer 3-3, the ATM controller reads the reception buffer data from the table memory. The address of the pointer area of the memory 1 is read.

Next, the address of the first data buffer stored at the address of the pointer area is read.
Then, the cell data of channel A is transferred to the data buffer.

Each time a cell arrives and is transferred to the data buffer, the data buffer size of the status of the reception buffer memory in the table memory is decremented by the transfer byte. Empty data buffer is "0"
Is reached, the address of the new data buffer is obtained from the pointer area.

All data points to one pointer area
When the buffer is exhausted, the next pointer area pointed to by the link pointer is used. At this time, the remaining number of the pointer area of the reception buffer memory 1 in the table memory 4 is decremented. When decrementing the number of remaining pointer areas, the number of warnings is compared with a preset number of warnings.
Notify PU5.

When the CPU 5 receives the notification from the ATM controller 3, the CPU 5 adds a new pointer area to the end of the pointer area forming the chain in the reception buffer memory 6, and further stores the remaining pointer area in the table memory 4. To refill the memory.

In the channels B and C, the reception buffer memory is selected according to the cell rate in the same manner as described above. Channel B, which is medium speed,
The channel C to the memory 2 is transferred to the reception buffer memory 3.

[0061]

As described above, according to the present invention,
The ATM controller can automatically and dynamically select a suitable receive buffer memory according to the cell rate of the channel. This reduces the number of receive buffers that are frequently replenished, which avoids the need for CPU software to be dependent on the cell rate of the channel and reduces the frequency of underrun.

As a result, according to the present invention, it is possible to contribute to the improvement of the performance of the entire apparatus, and it is possible to effectively use the limited memory resources according to the channel.

[Brief description of the drawings]

FIG. 1 is an ATM transmission device equipped with an ATM controller according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 ATM transmission device (reception side) 2 ATM transmission device (transmission side) 3 ATM controller 3-1 Reception FIFO 3-2 Header table 3-3 Timer 4 Table memory 5 CPU 6 Memory 7 Data buffer 8 Pointer area 9 Reception Buffer address

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 12/28 H04L 13/08

Claims (3)

(57) [Claims] 1. A mounted to the router device or adapter card on the ATM network, and determines whether to receive an incoming cell, after processing such as checking a header separation and error codes, size each other holds the different remaining amount of each receive buffer memory address information and the respective receive buffer memory to the table, the ATM controller for restoring the transferred packet according to the address information <br/>, a cell of a plurality of channels when receiving at the same time, the plurality
Means for observing the cell rate of each channel of the channel for a certain period of time, and the cell rate of each channel, based on the address information in the table and the information obtained by the means.
The address of each receive buffer memory of different size
Means for automatically selecting the reception buffer memory suitable for each channel by associating the reception buffer with the channel . 2. The observation result information of an interval time between cells for each reception channel, wherein the ATM controller according to claim 1
And the address information held in the table
An ATM controller for selecting the reception buffer memory based on the following . 3. An AT controller mounted on a router device or an adapter card of a terminal on an ATM network, means for observing an interval time between cells for each reception channel for a plurality of reception channels; a plurality of receive buffer memory that is prepared separately, the address information and each of the receive buffer memory
A table for holding the remaining amount of the reception buffer memory, and observation result information of the cell interval time for each reception channel
And the address information held in the table
From among the plurality of reception buffer memories ,
The optimal receive buffer memory according to the cell rate ascertained, such as allocating a large receive buffer memory for a channel with a high cell rate and a small receive buffer memory for a channel with a low cell rate. and means for selecting, ATM control apparatus characterized by.