JP3017212B1 - Multiplier PLL circuit and control method thereof - Google Patents

Abstract

Kind Code: A1 A PLL circuit which uses a VCO (Voltage Controlled Oscillator) whose drive capability can be switched, has low frequency sensitivity, and has a wide controllable frequency range, and a control method thereof. A phase comparison circuit, a charge pump, a VCO,
A PLL circuit comprising a loop constituted by a frequency dividing circuit, comprising a selection means for determining a driving capability of the VCO, and outputting a selection signal for switching the driving capability of the VCO to the VCO according to the determination result; The VCO receives the selection signal and selects a driving transistor from among a plurality of transistors of an inverter forming a ring oscillator, thereby switching the driving capability, and using a control bias voltage among a plurality of transistors forming the inverter. By setting the ratio of the controlled transistors to be relatively small, the frequency sensitivity to a change in the control bias voltage supplied to the VCO is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a PLL (Phase L
Coked Loop (Phase Locked Loop) circuit
The present invention relates to a technique for controlling the frequency sensitivity of an LL circuit.

[0002]

2. Description of the Related Art An example of the configuration of a conventional PLL circuit is shown in FIG.
Shown in Referring to FIG. 11, a phase comparison circuit 21 and a charge pump 22 for receiving and charging / discharging a phase difference signal from the phase comparison circuit 21, smoothing the capacitance terminal voltage with a low-pass filter, and outputting a voltage corresponding to the phase difference. A voltage controlled oscillator (referred to as “VCO”) 23 whose oscillation frequency is varied based on a control voltage from the charge pump 22, and a frequency dividing circuit 24.
The oscillation frequency is variably controlled by the control voltage 29 from the control circuit 2 and the control voltage 28 from the temperature detection circuit 20. The frequency dividing circuit 24 has a frequency dividing value set by a frequency multiplying signal 27 which is a control signal for setting and controlling the frequency multiplying factor of the PLL circuit.

The conventional PLL circuit having such a configuration has a wide variation in output frequency depending on the manufacturing process and temperature.
To compensate for this, the frequency sensitivity, ie, V for a constant change in control voltage (control bias voltage), is
The change of the output frequency of CO is large.

The fact that the frequency change with respect to the control bias voltage is large means that when noise is applied to the control bias, the effect is large, and the output frequency fluctuates greatly, leading to an increase in the jitter of the output of the PLL circuit.

[0005]

Recently, as the operating frequency of the PLL circuit increases, the ratio of the jitter to the clock cycle increases.

In the conventional PLL circuit, a circuit for generating a control bias voltage for the VCO has been devised such as to reduce noise. However, in order to improve the noise resistance of the circuit itself, it is necessary to control the control bias voltage. It is an issue to reduce the rate of frequency change and reduce output frequency sensitivity.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made based on the recognition of the above-mentioned problems, and an object of the present invention is to use a VCO (voltage-controlled oscillator) capable of switching drive capability, have a low frequency sensitivity, and control a frequency range that can be controlled. And a control method thereof.

[0008]

SUMMARY OF THE INVENTION The present invention, which achieves the above-mentioned object, determines the driving capability of a VCO and, in accordance with the result of the determination,
Means for outputting a selection signal for switching the driving capability of the VCO to the VCO, wherein the VCO receives the selection signal and switches a driving transistor from a plurality of transistors of a ring oscillator including an inverter including a plurality of transistors. The drive capability is switched by selection, and at this time, the ratio of the control bias transistor is set to be small, so that the frequency sensitivity to a change in the control bias is reduced.

[0009]

Embodiments of the present invention will be described. The PLL circuit according to the present invention is a digital VCO
And the control of the oscillation frequency by the control bias voltage (analog signal) for the VCO.

In the present invention, the switching of the driving capability of the VCO, that is, the number of the driving transistors included in the inverter constituting the ring oscillator of the VCO is performed only once at the time of initializing the circuit.
Only the oscillation frequency control by the control bias voltage is performed on the VCO.

That is, in the present invention, the variation in the manufacturing process can be reduced by the VC
The correction is performed by switching the driving capability of O, and the temperature variation and the phase correction during the circuit operation are performed by the control voltages (control bias voltages) output from the respective temperature detection circuits and the phase comparison circuits.

An embodiment of the present invention will be schematically described with reference to FIG. Referring to FIG. 4, the PLL circuit according to this embodiment includes a phase comparison circuit 21,
A PLL circuit comprising a loop composed of a charge pump 22, a VCO 23, and a frequency dividing circuit 24 further includes a selecting circuit 19 and a temperature detecting circuit 20.
Determines the drive capability of the VCO 23 at the time of circuit initialization, and selects a drive signal for switching the drive capability of the VCO 23 according to the determination result (switches on / off the drive transistor array included in the inverter of the ring oscillator of the VCO 23). VCO2
Output to 3.

The VCO 23 receives the selection signal 30 and switches the driving capability by selecting a driving transistor from a plurality of transistors of the inverter forming the ring oscillator. The frequency sensitivity to the change of the control bias is reduced by setting a small ratio of the transistor array (the transistor array in which the control voltage from the charge pump and the control voltage from the temperature detection circuit are input to the gate as the bias voltage). A PLL circuit characterized in that:

FIG. 1 is a flowchart showing an outline of a control flow according to an embodiment of the present invention.

Referring to FIG. 1, in initializing a circuit, first, a reference for measuring the performance of a VCO is set (step I).

Subsequently, the selection circuit 30 measures the driving capability of the VCO 23 (Step II), and selects a (SELECT) signal 3 for switching the driving capability according to the measurement result.
0 is output to the VCO 23.

The measurement of the driving capability of the VCO uses a fixed pulse count time set from the reference clock (input clock) and the multiplication control signal 27. By using an external signal, it is possible to always determine the driving capability of the VCO based on a fixed reference irrespective of the manufacturing process and temperature variation of the circuit itself.

The VCO switches the driving capability of the VCO by selecting a driving transistor from a plurality of transistors of a ring oscillator in which an inverter composed of a plurality of transistors is cascaded in a ring shape (step
III).

At the time of switching, the frequency sensitivity to a change in the control bias can be reduced by setting the ratio of the control bias transistor to a small value.

During circuit operation, the phase difference between the reference clock input to the PLL circuit and the output clock is compared, and the oscillation frequency of the VCO is finely adjusted by the control bias so that the phase difference becomes 0 (steps IV to IV).
VI). In addition, VC is controlled by a control signal from the temperature detection circuit 20.
Fine adjustment of the oscillation frequency of O23 is also performed.

As described above, in the present invention, the frequency sensitivity is low by combining the coarse adjustment by switching the driving capability of the VCO and the fine adjustment by the control bias.
In addition, it is possible to widen the controllable frequency range.

[0022]

Embodiments of the present invention will be described with reference to the drawings. FIG. 4 is a diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 4, the VCO 23 and the selection (SELECT)
The circuit 19 includes a circuit 19, a phase comparator (PD) 21, a charge pump (CP) 22, a temperature detection circuit (TSENSE) 20, and a frequency divider (DIV) 24.

The phase comparator 21 includes a reference clock (input clock) 26 and a VCO divided by a frequency divider 24.
23, outputs a phase difference detection result, and outputs the result through the charge pump 22 to the VCO 23 as a control voltage (control bias voltage) for phase correction.
Output to

The temperature detection circuit 20 detects a change in the ambient temperature during the operation of the circuit, and outputs a control voltage (control bias voltage) 28 for temperature correction to the VCO 23. As the temperature detection circuit 20, for example, a known circuit that amplifies a resistor terminal voltage due to a temperature change of a current flowing through a resistor connected in series with a diode and outputs the amplified voltage as a control bias voltage is used.

The selection circuit 19 receives the reference clock 2
6, a reset signal 25, a multiplied signal 27 which is a control signal for controlling the multiplied number of the PLL circuit, and a VCO output clock 31 and selected for the VCO 23 (SELECT).
The signal 30 is output.

FIG. 5 is a diagram showing a configuration of the selection (SELECT) circuit 19 in one embodiment of the present invention. Referring to FIG. 5, the selection circuit 19 sets a count number using the multiplied signal 27 and outputs the count number to the pulse counter (A) 33, and a reference clock (input clock) based on the set count number. And the output pulse of the VCO 23 is counted by using the pulse counter (A) 33 which outputs the pulse of the above to the pulse counter (B) 34 as a VCO pulse count signal and the VCO pulse count signal from the pulse counter (A) 33. A pulse counter (B) 34 and a pulse counter (B) 34
Is selected for the VCO 23 according to the count number (SEL
And a transistor select circuit 35 that outputs an ECT) signal 30.

The transistor select circuit 35 inputs the count value of the pulse counter (B) 34, decodes the count value, and outputs the select signal 30, and uses a well-known decoder logic such as a logic gate configuration or a table lookup system. Is used.

FIG. 6 shows a VCO according to an embodiment of the present invention.
FIG. 23 is a diagram illustrating an example of a configuration of a 23. Referring to FIG.
The VCO 23 includes a three-stage ring oscillator of an inverter (INV). Each inverter has a control bias voltage 29 from the charge pump 22, a control bias voltage 28 from the temperature detection circuit 20,
A selection signal (digital signal) from the selection circuit 19 is supplied.

FIG. 7 is a diagram showing a configuration of the inverter (INV) of VCO 23 shown in FIG. Referring to FIG. 7, the inverter (INV) is configured by connecting four columns of transistors arranged in vertical stages in 40 columns in parallel.

In this embodiment, forty columns of transistors
Transistors for phase correction control bias for 3 rows
Rows 39 and 17 are temperature correction control bias transformers.
Transistors 40 and 20 are connected to a full-on transistor 41.
Used. Tiger for phase correction control bias
The first column of transistor 39 has a source grounded and a gate
N-channel MOS transistor for inputting selection signal 30-N-1
TA NM1₁And N-channel MOS transistor NM1₁Drain of
To the source and input the inverter input signal to the gate
N-channel MOS transistor NM1_TwoAnd N-channel MO
S transistor NM1 _TwoConnect the drain to the drain of
P-channel MOS transistor that inputs the selection signal 30-P-1 to the port
Transistor PM1_TwoAnd the P-channel MOS transistor PM1_TwoSaw
Connect the drain to the gate and charge pump 29 to the gate.
These control bias voltage 29 is input and the source is
P-channel MOS transistor PM1 connected to power supply₁And
, Temperature correction control bias transistor 40
The first column has a source grounded and a gate with a select signal 30.
N-channel MOS transistor NM4 for inputting -N-4₁And N
Channel MOS transistor NM4₁Connect the source to the drain of
N channel with the inverter input signal input to the gate
Flannel MOS transistor NM4_TwoAnd N-channel MOS transistor
TA NM4_TwoConnect drain to drain and select gate
P-channel MOS transistor PM for inputting signal 30-P-4
4_TwoAnd the P-channel MOS transistor PM4_TwoSauce on the sauce
And the gate from the temperature detection circuit 20
Input the roll bias voltage 28 and connect the source to the power supply
P-channel MOS transistor PM4₁And full
The first column of the ON transistors 41 has a source grounded.
N channel for inputting the selection signal 30-N-20 to the gate
MOS transistor NM20 ₁And N-channel MOS transistor
TA NM20₁Connect the source to the drain of the
N-channel MOS transistor that receives the inverter input signal
NM20_TwoAnd N-channel MOS transistor NM20_TwoDray of
The drain is connected to the gate, and the selection signal 30-P-20 is connected to the gate.
P-channel MOS transistor PM20_TwoAnd P Cha
Flannel MOS transistor PM20_TwoConnect drain to source
Input the ground potential to the gate and connect the source to the power supply
P-channel MOS transistor PM20₁And three rows
Transistor 3 for phase correction control bias
Transistors for temperature correction control bias in rows 9 and 17
Driving of Full-On Transistors 41 in Stars 40 and 20
N-channel MOS transistor (NM1_Two~ NM42, ~ NM
202, the 20th column of the full-on transistor 41
Lanista NM40_Two) Gate is the input signal of the inverter
Are connected in common, and the drain is common as the inverter output
It is connected.

The operation of the embodiment of the present invention will be described.

The switching of the driving capability is performed only once at the time of circuit initialization (when the reset signal 25 is active). During the circuit operation, the output frequency is controlled only by the control bias.

Switching of the driving capability of the VCO 23 at the time of initialization is performed in accordance with the number of output pulses of the VCO counted in the same time as the preset reference clock count.

The operation of one embodiment of the present invention will be described in detail with reference to the flow charts of FIGS. 1, 2 and 3.
2 and 3 are flowcharts showing details of the processing flow of FIG.

As the VCO capability determination reference setting (step I in FIG. 1), a time for counting the output clock 31 of the VCO 23 is set.

First, the count number of the reference clock 26 in the pulse counter (A) 33 is set by the count number setting circuit 32 based on the multiplied signal 27 which is a control signal for setting the multiplied number (steps 1 and 2 in FIG. 2). 2).

The pulse counter (A) 33 reads the reference clock 26 according to the set count number.
Is counted (step 3 in FIG. 2).

For example, if the output frequency of the PLL circuit is 1 GHz
To set the initial value of the count number of the reference clock 26 to
Assuming 1000 times, the reference clock 26 is 1 [GHz]
In the case of, since the frequency is multiplied by 1, the pulse counter (A) 33
Is 1000 × 1/1 = 1000 times.

The cycle of the reference clock 26 is 1 [n
s], since the count number is 1000, 1 [ns] × 1000 = 1
[us] is the count time of the output signal of the VCO.

When the reference clock 26 has a frequency of 500 [MHz], the pulse counter (A) 33 counts 1000 because it is multiplied by 2 (the multiplied signal indicates 2 in FIG. 2).
× 1/2 = 500 times. Since the cycle of the reference clock 26 is 2 [ns] and the count number is 500, 2 [ns] × 500 = 1
[us] is the count time of the output signal of the VCO 23.

Thus, a fixed time is always set,
It is output to the pulse counter (B) 34 as a VCO pulse count signal (signal 37 in FIG. 4, 7 in FIG. 2) (step 4 in FIG. 2).

Next, when the reset signal 25 is input to the selection circuit 19, initialization of the circuit is started (FIG. 2).
Steps 5 and 6).

The pulse counter (B) 34 counts the output pulses 31 of the VCO 23 using the VCO pulse count signal (37) for a fixed time set by the pulse counter (A) 33 (step 8 in FIG. 3). ).

Then, a pulse counter (B) for a fixed time
The transistor select circuit 35 determines the count of 34 (step 9 in FIG. 3), and selects the number of drive transistors in the inverter forming the ring oscillator of the VCO 23 according to the count (step 1 in FIG. 3).
0).

The number of output pulse counts of the VCO 23,
The correspondence with the number of drive transistors in the inverter forming the ring oscillator of the VCO 23 is set in advance in the transistor select circuit 35 in accordance with the circuit characteristics, and the transistor select circuit 35 switches to the VCO 23 in accordance with the selected number of VCO drive transistors. Selection signal 3
0 is output (step 11 in FIG. 3).

In the VCO 23, the number of driving transistors is switched according to the selection signal 30 from the transistor selection circuit 35 (step 12 in FIG. 3). Note that V
The drive transistors included in the inverter that forms the ring oscillator of the CO 23 may be configured to be all set to the selected state at the time of circuit initialization, and the number of drive transistors may be switched in step 10.

In this embodiment, the selection signals 30-P-1,
30-P-4,30-P- 20 ... P -channel MOS transistor PM1 ₂ which is input to the guest terminal, PM4 _2, PM2
0 ₂ ... and, 30-N-1,30-N -4,30-N-20 ...
Switches on and off the N-channel MOS transistors NM1 ₂ , NM4 ₂ , NM20 ₂ ... Input to the gate terminal, thereby changing the number of drive transistors of the VCO 23.

When the driving transistor of the VCO 23 is switched, the initialization of the circuit is completed and the circuit operation starts (step 13 in FIG. 3).

During the circuit operation, the reference clock 26 and the output clock 31 of the VCO 23 divided by the frequency divider 24 are compared with the phase comparator 2 in the same manner as in the conventional PLL circuit.
1 (step 14 in FIG. 3), and if there is a phase difference (step 15 in FIG. 3), the VCO is adjusted according to the phase difference.
The frequency of the VCO 23 is changed by changing the phase correction control bias voltage 29 output to the VCO 23.

In one embodiment of the present invention, the driving transistor of the VCO is not switched during the circuit operation, and the phase correction control bias voltage 29 and the temperature correction control bias output from the phase comparator 22 and the temperature detection circuit 20, respectively. At 28, the output frequency of the VCO 23 is controlled.

FIG. 9 shows a characteristic graph of the phase control bias voltage 29 and the output frequency of the VCO 23 in one embodiment of the present invention. In FIG. 9, the number of drive transistors of the inverter forming the ring oscillator of the VCO is one.
The graph shows characteristics varied in a range from 0 to 18 stages.

In the example shown in FIG. 9, there is a frequency variation of 1 to 1.5 GHz due to the manufacturing process and temperature variation. To correct this variation, the phase correction control bias voltage 29 is set to 0 to 1 [V]. In the range of [].

As a comparative example, FIG. 10 shows a characteristic of a change in the output frequency of the VCO due to the phase correction control bias in the conventional PLL circuit. As can be seen from FIG. 10, since the variation is corrected only by the change of the phase correction control bias from 0 to 1 [V], the frequency sensitivity becomes extremely large. The slope of the characteristic graph of the VCO output frequency with respect to the phase correction control bias voltage corresponds to the sensitivity. In the example shown in FIG. 10, 200 to 1300 [MHz /
V].

On the other hand, in one embodiment of the present invention, the frequency sensitivity is 50 to 200 [MHz / V], and in one embodiment of the present invention, the frequency sensitivity is one-fourth of the conventional configuration. It is reduced to 1/6.

By the way, when the sensitivity is lowered, the process
Although it is impossible to correct the temperature variation, in one embodiment of the present invention, the variation is compensated by switching the number of driving transistors of the VCO.

The frequency sensitivity is adjusted by changing the ratio of the phase adjustment control bias transistor (39 in FIG. 7) when switching the VCO drive transistor.

A wide frequency band can be controlled by switching the driving transistors, and the frequency sensitivity can be adjusted by changing the ratio of the control bias transistors in all the driving transistors.

The switching of the driving capability of the VCO is performed only once at initialization. Frequency control during circuit operation is performed only by control bias.

As a result, the output frequency sensitivity to the control bias can be reduced while keeping the controllable frequency range wide, and the frequency can be controlled with high accuracy.

Switching of the VCO driving capability at the time of circuit initialization is performed by counting the output pulses of the VCO for a certain period of time, determining the driving capability, and performing the switching according to the capability. By setting the fixed time for counting the output pulses of the VCO from an externally applied reference clock and a multiplied signal, a fixed time can always be set irrespective of the manufacturing process and temperature variation in the circuit.

FIG. 8 shows a VC according to a second embodiment of the present invention.
FIG. 3 is a diagram illustrating a circuit configuration of an inverter included in an O ring oscillator. In the above embodiment, the N-channel drive type inverter 43 (FIG. 8B), which is advantageous for speeding up, is used. However, as shown in FIG. Selection signal 3 from selection circuit 19
It may be constituted by an inverter which can change the driving transistor by 0-N and 30-P. CMOS inverter 42
7, a transistor row for phase correction control bias, a transistor row for temperature correction control bias, and a transistor row for full ON are formed as shown in FIG. 7, and the inputs of the CMOS inverter 42 are commonly connected. , The output is connected in common and turned on by the selection signal 30.
It is controlled to be off, and the control bias voltages 29 and 28 from the charge pump 22 and the temperature detection circuit 20 are controlled.
Is used to control the load.

Further, in the above embodiment, the VCO 23 is constituted by a ring oscillator having three stages of inverters, and one inverter is constituted by 40 columns of transistors arranged in four stages and having two types of phase and temperature correction. Corresponding to the bias, the ratio of phase correction transistors is three, the temperature correction is seventeen, and the full-on transistor is twenty. The same effect can be obtained by changing the number of stages of inverters, the number of stages / rows of vertically stacked transistors, the type of control bias, and the ratio of the transistors.

[0063]

As described above, according to the present invention,
A wide range of frequency band can be controlled by switching the drive transistor of the VCO, and the frequency sensitivity can be controlled by changing the ratio of the control bias transistor among the plurality of drive transistors. With the wide frequency region, the output frequency sensitivity to the control bias is lowered, and the frequency can be controlled with high accuracy.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a control operation according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating details of a control operation according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating details of a control operation according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a PLL circuit according to one embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a selection circuit in one embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a VCO in one embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of an inverter according to one embodiment of the present invention.

FIG. 8 is a diagram showing another configuration of the inverter in one embodiment of the present invention.

FIG. 9 is a graph showing a characteristic graph of a VCO output frequency with respect to a phase correction control bias voltage in one embodiment of the present invention.

FIG. 10 is a diagram showing a characteristic graph of a VCO output frequency with respect to a phase correction control bias voltage of a conventional PLL circuit.

FIG. 11 is a block diagram showing a configuration of a conventional PLL circuit.

[Explanation of symbols]

 Reference Signs List 19 selection circuit 20 temperature detection circuit 21 phase comparison circuit 22 charge pump 23 VCO 24 frequency divider 25 reset signal 26 reference clock 27 multiplication signal 28 temperature correction control bias voltage 29 phase correction control bias voltage 30 selection signal 31 VCO output signal 32 count Number setting circuit 33 Pulse counter A 34 Pulse counter B 35 Transistor select circuit 37 VCO pulse count signal 39 Phase correction control bias transistor 40 Temperature correction control bias transistor 41 Full-on transistor

Claims (13)

(57) [Claims] 1. A phase comparison circuit, a charge pump, a voltage controlled oscillation circuit (referred to as "VCO"), a frequency dividing circuit, and a driving capability of the VCO are measured. A control method for a PLL circuit comprising: a selection unit that outputs a selection signal for switching a driving capability to the VCO, comprising: (a) setting a measurement standard for the capability of the VCO when the circuit is initialized; b) measuring the driving capability of the VCO; and (c) outputting a selection signal for switching the driving capability of the VCO to the VCO in accordance with the measurement result. In response to the selection signal, the driving capability is switched by selecting a driving transistor from a plurality of transistor arrays of an inverter constituting a ring oscillator. By setting a small ratio of the transistor array controlled by the control bias voltage supplied from the charge pump among the plurality of transistor arrays constituting the inverter, the frequency sensitivity to a change in the control bias voltage is reduced. A method for controlling a PLL circuit, comprising: 2. A predetermined pulse count time set by the selection means based on a reference clock input to the PLL circuit and a signal for controlling a multiplication factor of the PLL circuit when measuring the driving capability of the VCO. was used, the counts output pulses of the VCO in pulse count time, based on the regimen number result, PLL of claim 1, wherein said outputting a selection signal for switching the VCO drive capability, characterized in that Circuit control method. 3. During a circuit operation, a selection signal for switching the driving capability of the VCO is not output, and a phase difference between a reference clock input to the PLL circuit and a clock from the frequency dividing circuit is compared. Finely adjusting the oscillation frequency of the VCO with a control bias voltage output from the charge pump so that the phase difference becomes 0;
3. The control method for a PLL circuit according to claim 2, wherein: 4. The control method of a PLL circuit according to claim 3, wherein, during circuit operation, the oscillation frequency of said VCO is finely adjusted by a control bias voltage output from a temperature detecting means. 5. A phase comparison circuit, a charge pump, a VCO,
A PLL circuit comprising a loop constituted by a frequency divider and a frequency dividing circuit, wherein a selecting means for judging the driving capability of the VCO and outputting a selection signal for switching the driving capability of the VCO to the VCO according to the judgment result is provided. The VCO receives the selection signal, selects a driving transistor from among a plurality of transistor arrays of an inverter forming a ring oscillator, switches a driving capability, and switches a plurality of transistor rows forming the inverter. A PLL circuit wherein the frequency sensitivity to a change in the control bias voltage is reduced by setting a small ratio of a transistor array controlled by a control bias voltage supplied from the charge pump. 6. A phase comparison circuit, a charge pump, a VCO,
And a frequency dividing circuit, wherein the PLL circuit comprises a temperature detecting circuit for detecting an ambient temperature and supplying a control bias voltage for temperature correction to the VCO, and determining a driving capability of the VCO. And selecting means for outputting a selection signal for switching the driving capability of the VCO to the VCO according to the determination result. The VCO receives the selection signal, and includes a plurality of transistors of an inverter constituting a ring oscillator By selecting a driving transistor from among the columns, the driving capability is switched, and by setting a small percentage of the transistor column controlled by the control bias voltage among the plurality of transistor columns constituting the inverter, the charge pump and A control via supplied from the temperature detection circuit to the VCO PLL circuit, wherein a frequency sensitivity to changes in voltage was set to be lower. 7. The inverter includes a plurality of inverter transistors connected in parallel with their inputs connected in common and their outputs connected in common, and is turned on / off by the selection signal between the inverter transistor, a power supply, and ground. 7. The PLL circuit according to claim 5, further comprising a switching element, and an active load element biased by the control bias voltage with respect to the inverter transistor controlled by the control bias voltage. 8. A VCO output is counted based on a result of counting the pulse count time using a constant pulse count time determined from a reference clock input to the phase comparison circuit and a signal for setting and controlling a multiplication factor. 7. The PLL circuit according to claim 5, wherein a driving capability of the VCO is determined. 9. A method according to claim 9, wherein said selection means sets a count number using a multiplication signal for setting a multiplication number of said PLL circuit, and a reference clock input to said phase comparison circuit at said set count number. Count the pulses, VC
First counter means for outputting as an O-pulse count signal; and when a reset signal for circuit initialization is input, the VCO pulse count signal for a fixed time from the first counter means is used to output the VCO output pulse. Second counter means for starting counting; selector means for decoding a count number of the second counter means and outputting a selection signal to the VCO;
The PLL circuit according to any one of claims 5 to 7, further comprising: 10. The VCO includes a ring oscillator in which inverters are connected in an odd-numbered ring shape, wherein each of the inverters constituting the ring oscillator includes an inverter transistor array for a phase correction control bias, and a full-on inverter transistor. An inverter transistor for the phase correction control bias, the drive transistor including a P-type transistor having a gate input of the phase correction control bias voltage on the load side of the drive transistor, and being turned on / off by the selection signal. N-type and P-type transistors are connected in series to a ground side and a power supply side, respectively. The inverter transistor for full-on is configured such that the drive transistor has a gate connected to the ground potential at the load side. With a type transistor Both are configured by connecting N-type and P-type transistors which are turned on / off by the selection signal in series to the ground side and the power supply side, respectively. The gates of the drive transistors of the inverter transistors are connected in common and the signal input is performed. And the output nodes of the drive transistors of the inverter transistors are connected in common and connected to a signal output terminal. The number of the inverter transistor rows for the phase correction control bias is the full-on inverter transistor row. 6. The PLL circuit according to claim 5, wherein said number is smaller than said number. 11. The VCO includes a ring oscillator in which inverters are connected in an odd-numbered stage ring shape, and each of the inverters constituting the ring oscillator includes an inverter transistor array for a phase correction control bias, and a temperature correction control bias. And an inverter transistor array for full-on, wherein the inverter transistor for phase correction control bias is a P-type transistor having the gate input of the phase correction control bias voltage on the load side of the drive transistor. And an N-type transistor and a P-type transistor that are turned on / off by the selection signal are connected in series to a ground side and a power supply side, respectively. The inverter transistor for the temperature correction control bias includes a driving transistor. A transistor is provided with a P-type transistor having a control bias voltage for temperature correction as a gate input on the load side, and N-type and P-type transistors which are turned on / off by the selection signal are provided on the ground side and the power supply side. The full-on inverter transistor includes a P-type transistor having a gate input of a ground potential on the load side of the drive transistor, and is turned on / off by the selection signal. N-type and P-type transistors are connected in series to the ground side and the power supply side, respectively. The gates of the drive transistors of the inverter transistors are connected in common and connected to a signal input terminal. The output nodes of the driving transistors are connected in common and connected to the signal output terminal. 7. The method according to claim 6, wherein the number of the inverter transistor rows for the phase correction control bias is smaller than the number of the inverter transistor rows for the temperature correction control bias and the number of the inverter transistor rows for full ON. PLL circuit. 12. The PLL circuit according to claim 7, wherein a driving transistor of said inverter transistor is an N-type transistor. 13. The method according to claim 13, wherein said inverter transistor is a CMOS.
7. An inverter according to claim 7, wherein said inverter comprises an inverter.
12. The PLL circuit according to any one of 0 and 11.