JP3017103B2 - Memory refresh system and refresh circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory refresh system and a refresh circuit in a computer device.

[0002]

2. Description of the Related Art Conventionally, a computer device is provided with a device for refreshing a memory. As an example of such an apparatus, see, for example, Japanese Patent Application Laid-Open No. 2-1466.
59 and the like. In this device, in order to suppress a memory access from another information processing device during a refresh, the memory unit is provided with a refresh busy signal generating means for indicating that a refresh is being performed, and a refresh busy signal line is connected to another information processing device. Was distributed to the device. Another information processing apparatus inputs a signal for inhibiting memory access from the memory access inhibiting unit to the memory when the memory is busy with refresh.

[0003]

However, this type of refreshing device requires an extra dedicated control unit and dedicated distribution signal in addition to the memory unit. In order to notify the control unit, a refresh busy signal generating means must be provided in the memory unit, and a dedicated busy signal line must be distributed to another control unit.

In this type of device, as the number of memory units connected to the bus increases, the number of refresh requests output to the bus increases. As a result, the number of times that another control unit can access the memory unit is increased. And the plurality of memory units separately output refresh requests to the bus, resulting in a problem that the throughput of the bus deteriorates.

[0005] Further, in this type of apparatus, there is also a problem that the power of a unit which does not originally need to be backed up cannot be stopped because of a refresh instruction at the time of battery backup.

An object of the present invention is to perform a refresh operation of a plurality of memories connected to an occupied bus without using a dedicated refresh pizy signal generating means and a signal line.
Efficiently improving the bus throughput of the device, and at the same time, making it possible to retain data by energizing only the memory unit at the time of backup, etc., and trying to save power by stopping the power supply of other units Is to do.

[0007]

SUMMARY OF THE INVENTION A refresh system and a refresh circuit for a memory according to the present invention manage a refresh cycle counting means by which each memory unit can count refresh timing and a bus occupying a refresh request. Bus cycle counting means, refresh command control means for outputting a refresh command in synchronization with the counter,
A command internal path for receiving a signal from the refresh command control means, a command external path for receiving a command from this bus, and a selector means for switching between the two types of paths are provided. Switching is performed by a refresh request internal switching signal for switching to a path.

The present invention also provides a request arbitration unit for arbitrating a received request to control a command and giving an instruction to a memory control unit, and a refresh cycle counting unit for outputting a refresh cycle counter reset signal for resetting a refresh cycle counter. Is provided.

According to the present invention, each memory unit means comprises:
The refresh command control means outputs a refresh request based on the output from each internal refresh cycle counter means and the output from the bus cycle counting means. A request signal can also be output to the means.

The other memory unit means that did not output the refresh request can receive the refresh command from the command external path.
In addition, the request arbitration unit is configured to execute one request from either path.
If the refresh command is received even once, the refresh cycle counter of each unit is reset by the refresh cycle counter reset signal.

As a result, thereafter, all the memory units can refresh simultaneously, and the refresh occupying the occupied bus can be minimized. Also, during a backup or the like, the refresh command is accepted only through the command internal path, so that the contents of the memory can be kept assured even when the power supply other than the memory unit is stopped.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of a memory refresh system and a refresh circuit according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram illustrating the configuration of a refresh system according to an embodiment of the present invention.

In the refresh system shown in FIG. 1, a signal line 101 is an occupation type bus for exchanging requests, commands and addresses between units.
n is a memory unit having a storage element unit. A refresh control unit 3 for outputting a refresh command to the bus 101 is provided in each of the memory units 1-1 to 1-n.
And a memory control unit 4 and a memory element unit 5.

Reference numerals 2-1 to 2-m denote control units each including a command control unit 6 including a request arbitration unit 6-1 for issuing a read / write command to a memory via the bus 101. .

FIG. 2 is a diagram showing details of bus signals of the refresh device of the present embodiment.

In FIG. 2, request stage 101
In a, bits are assigned to each unit connected to the bus 101. Bus 101
Is constituted by repeating each of these stages as one cycle, and all the units connected to the main bus are synchronized with this cycle.

FIG. 3 is a block diagram mainly illustrating the main configuration of the refresh control unit 3 in the refresh system according to the present embodiment. In the circuit of FIG. 3, the request arbitration unit 3-1 and the refresh
Command controller 3-2 , refresh cycle counter 3-3, bus cycle counter 3-4, selector 3-5
And so on.

In the memory unit of FIG. 3, a refresh timing is detected by a refresh cycle counter 3-3 based on a refresh clock of the signal line 301. The bus cycle counter 3-4 manages the occupied bus 101 based on the bus clock of the signal line 302. The refresh command control unit 3-2 inputs a refresh timing output signal of the signal line 304, a bus request timing output signal of the signal line 305, and a backup signal of the signal line 306 .

The selector 3-5 switches between a command internal path of the signal line 308 and a command external path of the signal line 309. The request arbitration unit 3-1 determines that the signal line 307 receives the request received from the command path of the signal line 310 by a refresh request internal switching signal for switching the selector to the internal path at the time of the refresh request.
Arbitrate commands, etc. The refresh cycle counter 3-3 outputs a refresh cycle counter reset signal 311 for resetting when the command received on the signal line 310 is refresh.

The memory element section 4 including a DRAM is controlled by a memory control section 4 for controlling the memory element section.

FIG. 4 shows the details of the refresh command control unit.
Is a set signal, and is the logical product of the bus request timing output signal 305 and the output of the register 3-2-1 .

In FIG. 4, a refresh timing signal of a signal line 312, which is an output signal, is a register 3-2.
-1 of the reset signal, 3-2-2 is a command output unit for outputting a refresh request, a command, etc. 3-2
-4 is a backup signal of the signal line 306 and the signal line 313
The switching signal 307 is a logical sum output with the request timing signal.

In FIG. 5, reference numeral 101a denotes a request stage in which each unit outputs a request, and 101b denotes an arbitration stage in which a received request is arbitrated.
1-C is a command stage for outputting a command.
An address stage 1d outputs an address.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIGS. In the configuration of FIG. 1, the main bus 101 is composed of successive stages of bus stages 101a and 101d as shown in FIG. 5, and each unit connected to the bus 101 is a request stage 101a shown in FIG. As shown, the requests are simultaneously output to the allocated bits, and in the next arbitration stage 101b, each unit arbitrates the received request in the request arbitration unit.

At this time, the memory units 1-1 to 1--1
Each unit recognizes that the refresh request output by n is received with the highest priority, and that the next command stage 101c and address stage 101-d are occupied by refresh. The bus 101 of the occupation system is constituted by the continuation of this cycle. The bus cycle counter 3-4 manages the timing based on the detailed block diagram of the memory unit in FIG. 3, and the timing of the bus request stage 101-a is controlled via the bus request timing output path 305.
Output to 2.

The refresh cycle counter 3-3 includes:
The timing that requires refresh is counted based on the refresh clock 301, and when the refresh timing is reached, the refresh timing output path 30
4 outputs a track signal to the refresh command control unit 3-2. In the refresh command control unit 3-2, there is an output from the refresh timing output path 304,
When there is an output from the bus request timing output bus 305, a refresh request, a command,
The address is output to the bus 101, and during one cycle of the bus stages 101-a to 101-d, the refresh request internal switching path 307 is used.
The switching selector 3-5 switches the command internal path 308.

The output refresh request is sent to the unit which has output the command in the command internal path 3.
08, the other memory units that have not reached the refresh timing
The request is accepted from the path 309. The control units 2-1 to 2-m other than the memory do not operate in one cycle of the bus when the refresh request is output.

Further switching selector 3-5, usually have to choose commands external path 309, if the own unit is generated refresh requests only, it commands internal power
308 is selected. Upon receiving the request from the command path 310, the request arbitration unit 3-1 informs the bus 1 that the refresh request is processed with the highest priority.
Also, all of the memory units 1-1 to 1-n execute the refresh at the same time upon receiving the refresh command.
When each of the memory units 1-1 to 1-n executes refresh, the refresh cycle counter reset bus 31
1 issues a reset instruction to the refresh cycle counter 3-3.

Thereafter, the refresh of each memory unit is performed.
The refresh cycle counter 3-3 executes the refresh at the same timing, and the refresh of the plurality of memories can be completed in one bus cycle.
At the time of backup, the backup signal bus 306
By receiving a backup instruction from, all the memory units may be a switching selector 3-5 continues toward the preferential command internal path 308. Further, each memory unit receives and executes its own refresh request only from the command internal path 308 .

In the above embodiment, each of the memory units 1-1 to 1-n has a refresh command control unit based on the output from each of the internal refresh cycle counters and the output from the bus cycle counter.
3-2 can output a refresh request , output a refresh request to its own unit from the command internal path, and simultaneously output a request signal to the internal path .

The other memory units 1-1 to 1-n that have not output the refresh request can receive the refresh command from the command external path . When the request arbitration unit 3-1 receives the refresh command at least once from either path, the refresh cycle counter of each of the memory units 1-1 to 1-n is reset by the refresh cycle counter reset signal.

As a result, all memory units 1
-1 to 1-n can perform refresh at the same time and can minimize the refresh occupying the occupied bus. Also, during a backup or the like, the refresh command is accepted only through the command internal path, so that the contents of the memory can be kept assured even if the power supply other than the memory units 1-1 to 1-n is stopped. .

[0033]

According to the present invention described above, the refresh request is output to the bus in the same manner as other normal commands, and the refresh is processed in the same manner as the other normal commands. Dedicated signal lines and means for informing other control units that the unit is being refreshed can be dispensed with.

Further, according to the present invention, each of the plurality of memory units has a means capable of activating the refresh operation by itself, and even if either the own memory unit which has reached the refresh timing or another memory unit outputs a refresh request, the internal command of the command is output. Refresh can be accepted from a pass or an external pass. For this reason, in the present invention, if all the memory units are simultaneously refreshed and executed, and at least one refresh is executed after the start of the main bus, the refresh cycle counter of each memory unit is set to the request arbitration unit which receives the command. Thus, the reset can be performed through the refresh cycle counter reset signal. Therefore, according to the present invention, the refresh of a plurality of memory units connected to the bus in which the subsequent refresh timings of all the memory units are all at the same time can be completed at once, thereby minimizing performance degradation. Can be.

Further, in the present invention, each memory unit has a refresh cycle counter,
During backup, the switching signal is forcibly directed to the command internal path by the backup signal, so that even if the bus stops, each memory unit can continue refreshing independently, so the memory contents are saved at backup While the bus 101 can be stopped and the power supply to the control unit can be stopped, and the power supply to other than the memory unit can be stopped at the time of backup of the device, the effect of saving power can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an apparatus configuration of a memory refresh system and a refresh circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing bit assignment of a bus according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating details of a memory unit in FIG. 1;

FIG. 4 is a diagram illustrating details of a refresh command control unit in FIG. 1;

FIG. 5 is a diagram showing a bus cycle in one embodiment of the present invention.

[Explanation of symbols]

1-1 to 1-n memory unit 2-1 to 2-m control unit 3 refresh control unit 3-1 request arbitration unit 3-2 refresh command control unit 3-2-1 register 3-2-2 command output unit 3 -2-3 AND device 3-2-4 OR device 3-3 Refresh cycle counter 3-4 Bus cycle counter 3-5 Switching selector 4 Memory control unit 5 Memory device unit 101 Bus 101-a Request stage 101-b Arbitration stage 101-c Command stage 101-d Address stage

Claims (10)

(57) [Claims] 1. A memory element means for performing storage in an element unit;
A control means provided on a bus line for controlling storage of the memory element means, wherein the memory element means performs a memory refresh operation by a control signal from the control means; A memory control unit for controlling, a refresh control unit for outputting a refresh command, and a command control unit for outputting a command to the memory unit unit.When the memory unit unit performs refresh,
A refresh system for a memory, wherein the refresh control means outputs a refresh operation as a command on a bus line. A refresh cycle counting means for outputting a refresh timing in response to a clock signal at the time of refreshing the memory element means; a bus request timing output signal based on a bus clock;
And bus cycle counting means for outputting, on the basis of the bus request timing output signal, the a request signal for requesting the refresh of the memory element unit, a refresh command control for outputting a command for refreshing the memory device unit 2. A refresh system for a memory according to claim 1, comprising: means. 3. A memory device means for performing storage on a device-by-device basis.
A control means provided on a bus line for controlling storage of the memory element means, wherein the memory element means performs a memory refresh operation by a control signal from the control means; A memory control means for controlling; a refresh control means for outputting a refresh command; a plurality of memory unit means having the refresh control means; a command control means for outputting a command to the memory unit means; and a refresh of the memory element means. Refresh cycle counting means for outputting a refresh timing in response to a clock signal at the time, and a bus request timing output signal by a bus clock.
And a request signal for requesting a refresh of the memory element means and a refresh signal for refreshing the memory based on a signal from a bus request timing output signal which is an output signal of the bus cycle counting means. And a refresh command control means for outputting a command. 4. The refresh command control means
A command internal path unit for receiving a signal, and a request from the refresh command control unit.
4. The memory refresh system according to claim 3, further comprising: a command external path unit for accepting, said command internal path unit, and a switching selector for switching said command external path unit. 5. A memory refresh system according to claim 3, further comprising request arbitration means for processing an internal path switching signal at the time of said refresh request, a request signal received from a command path, and a command signal. . 6. When the refresh command is received, a counter reset signal in a refresh cycle for instructing reset is issued to the refresh cycle counting means, and the memory unit is refreshed once. Item 6. A refresh system for a memory according to item 3, 4 or 5. 7. A memory device for storing data in units of a device, and a control circuit provided on a bus line for controlling storage of the memory device, wherein the memory is refreshed by a control signal from the control circuit. In a refresh circuit of a memory that operates, a memory control circuit that controls the memory element; a refresh control circuit that outputs a refresh command; a plurality of memory unit circuits including the refresh control circuit; A command control circuit for outputting a command, a refresh cycle counting circuit for outputting a refresh timing in response to a clock signal at the time of refreshing the memory element, and a bus request timing output signal by a bus clock
Bus cycle counting means for outputting a request signal for requesting a refresh of the memory element in response to a count signal which is an output signal of a bus cycle counting circuit and a signal from a timing output signal for requesting a bus line; And a refresh command control circuit for outputting a command for refreshing the element. 8. A signal from a refresh command control means.
Command internal path for receiving the
8. The memory refresh circuit according to claim 7 , further comprising: a command external path to be attached; said command internal path; and a switching selector unit for switching between said command external paths. 9. A request arbitration circuit for performing a request arbitration process based on an internal path switching signal at the time of the refresh request, a request signal received from a command path, and a command signal. Memory refresh circuit. 10. An output circuit for outputting a counter set signal in a refresh cycle for instructing said refresh cycle counting means to reset when said refresh command is received, and for refreshing said memory unit once. 11. The circuit according to claim 7, 8, 9 or 10.
The refresh circuit of the memory according to claim 1.