JP3016379B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit suitable for an IDDQ test.

[0002]

2. Description of the Related Art In the case of a CMOS integrated circuit, current consumption in a non-operating state, that is, in a stationary state, is about several UA. However, when a specific node fails due to a manufacturing defect and is short-circuited to a power supply or a ground, a current flows. By utilizing this principle, the IDDQ test (qu
By using an iescent power supply current test, a defect of an integrated circuit can be eliminated in a short time.

In order to improve the defect removal rate by the IDDQ test, it is only necessary to prepare a test pattern in which all the nodes are "1" or "0". In practice, such a test pattern cannot be created. Because it ’s difficult
The test is performed with a changing ratio of the internal nodes, that is, a pattern with a high toggle rate.

ASIC using microcomputer
In the (Application Specific Integrated Circuit), the microcomputer is stopped and the power supply current is measured according to a program created by the user.

FIG. 5 is a diagram for explaining the prior art. Reference numeral 501 denotes a device under test, in which a microcomputer 502 and a user circuit 503 are integrated on the same chip, and are interconnected by an input signal 504 and an output signal 505. The address data bus 506 is connected to an external terminal 507 via a user circuit 503.
508 is a measuring device. By supplying an instruction code to the terminal 507 and inputting a control signal to the terminal 509, the measuring device 508 can control the device 501 to be measured. Reference numeral 511 denotes a clock output from the microcomputer 502. The user circuit 503 operates with the clock 511, and can stop the clock 511 by operating the clock control register 512.

FIG. 6 is a flowchart showing a processing flow when an IDDQ test is performed with the configuration of FIG. In step 601, the microcomputer 502 causes the user circuit 503 to transition to a state in which an IDDQ test is performed according to the instruction code given from the terminal 507. The part that cannot be controlled by the signal 505 is realized by directly operating the terminal 509 with a signal from the measuring device 508.

After the state transition of the user circuit 503 is completed, in order to stop the microcomputer 502 in a step, a flag for shifting to the stationary state is written in the internal register 512, and in a subsequent step 603, a stop instruction is executed. By doing so, the microcomputer 502 stops, and the output of the clock 511 stops, so that the operation of the user circuit 503 also stops, and as a result, the entire circuit under test 501 enters a stationary state.

[0008]

By the way, in performing the IDDQ test, a test pattern in which the internal connection points change as much as possible must be created in order to increase the defect detection rate. This is because the defect detection rate can be improved by measuring the quiescent current at a timing where there are many changes.

In the case of a normal CMOS logic, there is no steady-state current path, so that a quiescent current can be measured at any time except for a transient state such as a rise of a clock.

However, a microcomputer may include a dynamic circuit, a memory having a sense amplifier, or the like, and a current may flow only by stopping the clock. Therefore, the circuit cannot be brought into a stationary state unless a specific condition is satisfied.

In order to accurately measure the quiescent current, a series of sequences must be programmed and brought to a quiescent state.
There is a case where the internal state is not suitable for performing the DDQ test. That is, in order to perform an IDDQ test with a high detection rate in a circuit including a microcomputer, it is necessary to execute a program designed to transition the inside of the microcomputer to a state for the IDDQ test.

However, for a user who uses the microcomputer, it is practically impossible to create a program for setting an internal state suitable for performing the IDDQ test because the inside of the microcomputer is a black box.

Accordingly, the present invention has been made in view of the above problems, and has as its object to use a test routine to enable a microcomputer to perform an IDDQ test. To provide a semiconductor device that facilitates test pattern design for IDDQ test.

[0014]

In order to achieve the above object, the present invention provides a semiconductor integrated circuit including a microcomputer , wherein the microcomputer executes control of a quiescent power supply current test (hereinafter referred to as "IDDQ test"). Storage device that stores programs for
The microcomputer is stored in the storage device.
By executing the program, the semiconductor integrated circuit
Save the internal circuit terminal status that
The microcomputer and the internal circuit are in a stationary state.
And, performing IDDQ testing by measuring device is configured
Comprising Te, characterized in that.

[0015] The present invention preferably provides a semiconductor integrated circuit having a microcomputer and a user circuit.
The microcomputer performs a quiescent power supply current test (hereinafter referred to as a “ quiescent power supply current test”
A program for executing control of the “ IDDQ test ” by the CPU of the microcomputer is stored in advance, and at the time of the IDDQ test, the program stored in the storage means is executed, and under the program control, In order to operate the microcomputer without destroying the state of the user circuit, the values of the terminals of the user circuit are saved in a storage unit, and the microcomputer is operated independently of the value output by the user circuit. In order to stop the computer, an inhibit value is applied to the input of the microcomputer in place of the output of the user circuit, and the microcomputer is supplied with a quiescent power supply current measurement (hereinafter referred to as " quiescent power supply current measurement").
( Hereinafter referred to as “ IDDQ measurement ”) , the supply of the clock to the user circuit is stopped, and the IDDQ measurement is performed by the measuring device.

[0016]

Embodiments of the present invention will be described below. According to a preferred embodiment of the semiconductor device of the present invention, in a semiconductor integrated circuit including a microcomputer and a user circuit, a microcomputer (102 in FIG. 1) controls an IDDQ test by a CPU of the microcomputer. Storage means (116 in FIG. 1) storing a program to be executed, and selects either the output signal from the user circuit (103 in FIG. 1) or the output from the first latch circuit (109 in FIG. 1). A first selector (FIG. 1) for supplying the microcomputer
108) and the microcomputer (102 in FIG. 1)
Output signal and second latch circuit (112 in FIG. 1)
And a second selector (113 in FIG. 1) for selecting one of the outputs from the microcomputer and supplying the selected signal to the user circuit. The microcomputer controls the selection control signal (115 in FIG. 1) to the first and second selectors. ), And the microcomputer supplies a clock signal (119 in FIG. 1) to the user circuit.

In the IDDQ test, the user circuit is connected to the I
In order to make a transition to the DDQ measurement state, the microcomputer performs a program operation, executes a program (IDDQ routine) stored in the storage means (116 in FIG. 1),
In order to operate the microcomputer without destroying the state of the user circuit under program control, the value of the terminal of the user circuit is stored in the second latch circuit (112 in FIG. 1).
After writing to the first memory, the second selector (113 in FIG. 1) switches so that the second latch circuit is selected, and stops the microcomputer irrespective of the value output from the user circuit. After writing a value to be an inhibit to the latch circuit and switching the first selector to select the first latch circuit, the microcomputer is transited to the IDDQ measurement state, and then the supply of the clock to the user circuit is stopped. Then, the IDDQ measurement is performed by the measurement device.

The operation clock to the microcomputer may be supplied from the outside. In this case, the microcomputer notifies the external measuring device of the transition to the IDDQ measurement state, stops the supply of the clock from the outside, and performs the IDDQ measurement.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, in the present embodiment,
The device under test 101 is a microcomputer 102
And a user circuit 103, which is connected to the measuring device 104, which controls the terminals of the device under test 101. Measuring device 104 and device under test 10
1 is connected via a signal line 105.

The microcomputer 102 and the user circuit 103 are connected via a bus 106, and the selector 10
8 and the selector 113 include the microcomputer 1
02 is connected as a selection control signal. The signal lines of the bus 106 are connected to the latches 109 and 112.

The built-in R of the microcomputer 102
The OM 116 is connected to the control unit 117 via the internal command data bus 118 of the microcomputer 102. The user circuit 103 operates according to the output clock 119 from the microcomputer 102, and the output clock 119 is stopped by writing a value to the clock control register 120 according to an instruction from the microcomputer 102.

FIG. 2 is a flowchart showing a processing flow when an IDDQ test is performed in the configuration of the present embodiment shown in FIG. The operation of the IDDQ test of this embodiment will be described with reference to FIGS.

In step 201, the microcomputer 102 is programmed and operated to transition the user circuit 103 to the IDDQ measurement state. These processes are executed based on the data provided from the measurement device 104.

The instruction given from the measuring device 104 is given to the microcomputer 102 via the bus 106. During normal operation, the input to the microcomputer 102 is supplied from the output terminal 110 of the user circuit 103 to the selector 10.
8 is performed.

Similarly, during normal operation, the output from the microcomputer 102 is connected to the user circuit 103 via the selector 113.

In the following step 202, the internal ROM 11
The subroutine stored in 6 is called. The above is the contents programmed by the user, and the following steps are executed by the IDDQ routine stored in the built-in ROM 116.

The user circuit 10 set in step 201
In order to operate the microcomputer 102 without destroying the state 3, in step 203, the microcomputer 102
The value of the terminal 3 is written into the latch 112, and the selector control signal 115 is switched so that the latch 112 is selected.

In addition, in order to stop the microcomputer 102 irrespective of the value output from the user circuit 103, a value that becomes an inhibit (Inhibit) is written into the latch 109 via the data bus 106, and the selector 108 is turned on.
Is switched so that the latch 109 is selected.

In step 204, the internal ROM 11
The microcomputer 102 executes the IDDQ routine stored in No. 6 and causes the inside of the microcomputer 102 to transition to the IDDQ measurement state.

At step 205, the clock control register 1
By writing a flag to 20 and executing a stop command in step 206, the clock 119 output from the microcomputer 102 is stopped, and IDDQ measurement is performed.

FIG. 3 is a diagram showing the configuration of the second embodiment of the present invention. Referring to FIG. 3, the measuring device 301
Is a microcomputer 302 and a user circuit 303
And is connected to the measuring device 304, and the measuring device 3
04 controls the terminals of the measuring device 301. The measuring device 304 and the measuring device 301 are connected via a signal line 305.

The microcomputer 302 and the user circuit 303 are connected via a bus 306, and the selector 30
8 and the selector 313 include the microcomputer 3
02 is connected as a selection control signal.

A bus 306 is connected to the latches 309 and 312, and the built-in ROM 31 of the microcomputer 302 is connected to the bus 306.
6 is connected to the control unit 317 via the internal instruction data bus 318 of the microcomputer 302.

A clock 321 is output from the measuring device 304 and connected to the microcomputer 302. The microcomputer 302 outputs a signal 322 indicating that the IDDQ measurement state has been entered, and inputs the signal 322 to the measurement device 304.

FIG. 4 is a flowchart showing a processing flow of the IDDQ test in the second embodiment of the present invention shown in FIG. Referring to FIG. 3 and FIG.
The operation of the IDDQ test of the embodiment will be described below.

In step 401, the microcomputer 302 is programmed and operated to transition the user circuit 303 to the IDDQ measurement state. These processes are executed based on data provided from the measurement device 304.

The instruction given from the measuring device 304 is input via the bus 306 to the microcomputer 302 in the normal operation given to the microcomputer 302 from the output terminal 310 of the use circuit 303 through the selector 308.
Done through. Similarly, the microcomputer 302
Is output from the user circuit 303 via the selector 313.
Connected to.

In the following step 402, the internal ROM 3
Call the subroutine set to # 16. The above is the contents programmed by the user, and the following sequence is executed by the IDDQ routine stored in the built-in ROM 316.

The user circuit 30 set in step 401
In order to operate the microcomputer 302 without destroying the state of No. 3, in step 403, the microcomputer 302 sends the user circuit 30 via the bus 306.
The value of the terminal 3 is written into the latch 312, and the selector control signal 315 is switched so that the latch 312 is selected. Further, in order to stop the microcomputer 302 irrespective of the value output from the user circuit 303, a value to be an inhibit is written into the latch 309 via the data bus 306, and the selector 30 is controlled by the selection control signal 315.
8 is switched so that the latch 309 is selected.

In step 404, the internal ROM 316
Is executed, and the inside of the microcomputer 302 is shifted to the IDDQ measurement state.

At step 405, the microcomputer 3
02 outputs a signal 322 indicating the IDDQ measurement state.

In step 406, the measuring device 304 stops supplying the clock 321 and performs IDDQ measurement.

[0043]

As described above, according to the present invention,
This has the effect of facilitating the creation of a test pattern for the IDDQ test. The reason is that, in the present invention, by having the built-in ROM in which the IDDQ measurement routine is stored, the microcomputer can be placed in a state in which the IDDQ test can be performed. This is because it is only necessary to facilitate a program that calls a subroutine for measurement.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart for explaining a processing flow of the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a flowchart illustrating a processing flow according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional technique.

FIG. 6 is a flowchart for explaining a processing flow of the related art.

[Explanation of symbols]

101, 330, 501 Measuring device 102, 302, 502 Microcomputer 103, 303, 503 User circuit 104, 304, 504 Measuring device 105, 106, 118, 305, 306, 318, 5
05 Bus 107, 111, 115, 119, 307, 311, 3
15, 319, 321, 322 Signal line 108, 113, 308, 313 Selector 109, 112, 309, 312 Register 110, 114, 310, 314 Terminal 116, 316 Storage device 117, 317 Central processing unit

Claims (3)

(57) [Claims] 1. A semiconductor integrated circuit including a microcomputer, wherein the microcomputer includes a quiescent power supply current test (hereinafter, referred to as a static power supply current test).
A storage device storing a program for executing control of “ IDDQ test ”) , wherein the microcomputer is stored in the storage device.
By executing the program, the semiconductor integrated circuit
Evacuate the state of the internal circuit terminals required for the road,
Said microcomputer and said internal circuit and a stationary state <br/>, performing IDDQ testing by measuring device, and configuration
It is formed by a semiconductor integrated circuit, characterized in that. 2. A semiconductor integrated circuit comprising a microcomputer and a user circuit, wherein the microcomputer is a static power supply current test (hereinafter , referred to as a static power supply current test).
A program for executing a control of “ IDDQ test ” by the CPU of the microcomputer is stored in advance, and at the time of the IDDQ test, the program stored in the storage is executed. In order to operate the microcomputer without destroying the state of the user circuit, the values of the terminals of the user circuit are saved in a storage unit, and the microcomputer is operated independently of the value output by the user circuit. to stop the computer gives the inhibit value in place of the output of the user circuit to the input of the microcomputer, a stationary electrostatic the microcomputer
A semiconductor device, characterized in that after transition to a source current measurement (hereinafter referred to as " IDDQ measurement ") state , supply of a clock to the user circuit is stopped and IDDQ measurement is performed by a measurement device. 3. A semiconductor integrated circuit comprising a microcomputer and a user circuit, wherein the microcomputer is executed by a CPU of the microcomputer to control a quiescent power supply current test (hereinafter, referred to as an “IDDQ test”). A storage unit in which is stored in advance, a first selector that selects one of an output signal from the user circuit and an output from the first latch circuit and supplies the selected signal to the microcomputer, A second selector for selecting any one of an output signal and an output from a second latch circuit and supplying the selected signal to the user circuit, wherein the microcomputer selects a control signal for the first and second selectors. During the IDDQ test, the program stored in the storage means is executed. Under the program control, in order to operate the microcomputer without destroying the state of the user circuit, the value of the terminal of the user circuit is written into the second latch circuit, A second selector for switching the second latch circuit to be selected; and a first latch circuit for stopping the microcomputer regardless of a value output from the user circuit.
In after the write values to become inhibit the first selector is switched to the first latch circuit is selected, the microcomputer static supply current measurement (hereinafter referred to as "IDDQ measurement") to transition to the state, And a step of stopping supply of a clock to the user circuit and performing IDDQ measurement by a measuring device.