JP3016156B2 - Transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a processing device (processor) such as a computer or an NC device, and a separation type I / O installed at a place away from the processing device.
The present invention relates to a transmission control circuit and a transmission control system that control data transmission between O devices.

[Conventional technology]

2. Description of the Related Art Machine tools, FA devices, and the like are provided with a large number of solenoid valves, actuators such as motors, and sensors such as limit switches and proximity sensors on the machine side. These actuators and sensors are controlled by an NC device or a sequence controller (sequencer), but the NC device or sequencer is often housed in a control housing separated from the machine. An / O signal line is routed between the machine and the control enclosure.

However, as the number of I / O signal points increases, the number of wirings increases, and the space occupied by the wirings, wiring processing, and the like have become problems. On the other hand, due to the development of electronic components, the processors have become smaller and higher in performance, and the space for connecting I / O signal lines has become smaller, and it has become a path for selecting a processor installation position.

Therefore, the processor is separated from the I / O device and servo device, and in some cases, the NC device and the sequencer, and the former (processor) is the operating device (switch, keyboard, CRT, etc.)
It is installed in a position considering the convenience of the operator,
The latter (up to I / O devices and servo devices, and in some cases up to NC devices and sequencers) have come to be installed at reasonable positions taking into account wiring and mechanical structure. These are connected by an electrical or optical communication path.

[Problems to be solved by the invention]

As the above communication path, in order to reduce the cloth dose,
In many cases, a serial transmission line is used.
For example, a transmission system conforming to the RS-232-C standard is used. In this case, since various serial transmission control ICs are commercially available and a standard circuit configuration is established, hardware design is relatively easy. However, the I / O device must include a microprocessor, and both the processor and the I / O device require complicated software for communication processing. A particular problem arises when one side of the transmission (eg, a processor) attempts to reference (capture) signal data representing an event (eg, an input signal such as a sensor signal) that has occurred on the other side. in this case,
The processor first sends a signal indicating the content of the request, for example, the address of the data to be referred to, to the I / O device side, and the I / O device analyzes the sent signal and sends back necessary signal data as an answer . On the other hand, the processor continues to wait for an answer, that is, a return of data. Therefore, a complicated program is required and the data processing performance of the processor is reduced.
In addition, there is a problem that the transmission bit rate must be increased with respect to the capacity of the transmission line, that is, the required data amount, to cope with the transmission delay.

An object of the present invention is to provide a communication between a separated I / O device and a processor.
Even when the processor tries to refer to the input signal without using complicated communication software, the connection is made by the serial transmission circuit without reducing the processing capability of the processor.

[Means for solving the problem]

The above object is achieved by a transmission apparatus including a transmission path for transmitting serial signals in two directions and a pair of transmission control circuits connected to the transmission path for transmitting and receiving data. On the side, a memory for storing the transmission signal and a parallel-to-parallel conversion circuit that extracts the transmission signal stored in the memory in a predetermined order, converts it into a serial electric signal, and sends it out as a data block having a fixed data length. A serial-parallel conversion circuit for parallelizing the received data blocks and a memory for storing the output of the serial-parallel conversion circuit in a predetermined order on the receiving side of each transmission control circuit; Transmits a signal specifying the number of data blocks to be transmitted by one of them to the other transmission control circuit, and then starts transmitting the data block converted to the serial electric signal. Then, the other transmission control circuit converts the received data block into a parallel-to-parallel format and stores the data block in the memory storing the reception signal in the predetermined order, and the transmission signal stored in the memory storing the transmission signal. Is taken out in the predetermined order and subjected to the parallel-to-parallel conversion, and in accordance with the transmission of each data block from the one transmission control circuit to the other transmission control circuit, the parallel-to-parallel conversion is performed to the one transmission control circuit. This is achieved by sending data blocks.

Each transmission control circuit takes out the transmission signal from the memory in which the transmission signal is stored, performs a transmission operation consisting of parallel conversion and transmission in the order of the address of the memory in which the transmission signal is stored, and executes the transmission of the received data block. Performs an update operation of storing the output of the serial-parallel conversion and the serial-parallel conversion circuit in the address order in the memory, and when the transmission of the specified number of data blocks is completed, returns to the first address of the memory storing the transmission signal. Preferably, the transmitting operation is repeated, and the updating operation is repeated by returning to the first address of the memory that stores the output of the serial-parallel conversion circuit in address order.

[Action]

In data transmission, in the transmission section, data in the transmission signal storage section of the memory is taken out in address order, converted into a serial electric signal, and transmitted. When the data at the set final address has been transmitted, the operation automatically returns to the first address and repeats the data transmission. On the other hand, in the receiving unit, the serial electric signal received by the receiving end is converted into a parallel signal, and stored in the received signal storage unit of the memory in order of address. When the data is stored up to the set final address, the process automatically returns to the first address and the reception and the data storage are repeated.

The address width from the “first address” to the “set last address” is the same for transmission and reception. By the initial synchronization operation, transmission and reception of the first address are performed almost simultaneously.

〔Example〕

1 and 2 show an embodiment of the present invention. In FIG. 1, a processor 4 and a separation type I / O device 5A are connected by a data transmission line 3, and the separation type I / O device 5A
It is connected to the. In the present embodiment, the data transmission path 3 transmits an electric signal, but may transmit an optical signal, for example, an optical fiber. Processor 4
Is an NC device mainly composed of a central processing unit (CPU) 7A, and may be a sequence controller (sequencer) or the like. The CPU 7A and the data transmission path 3 are connected via the processor-side transmission control circuit 1.

The separation type I / O device 5A is a controlled object (generally a machine tool,
An interface device that connects the machine 6 such as an FA device) to the data transmission line 3, and an output circuit 8, an input circuit 9, and an I / O device-side transmission control circuit that connects the input / output circuits 8, 9 and the data transmission line 3. 2A. One of its functions is
That is, the output circuit 8 is turned on / off by data transmitted from the processor 4 via the data transmission path 3. By this ON / OFF, the actuator such as the valve / motor of the machine to be controlled 6 is controlled or the lamp is blinked to indicate the state. Another of the functions is to transmit a sensor signal of a limit switch, a proximity sensor, or the like, or switch information of a manual switch, which is input through the input circuit 9, to the processor 4 through the data transmission path 3. .

When the controlled object 6 includes a servo device that drives the motor to control the speed and position of the machine, the signals output via the output circuit 8 include a position command signal, a speed command signal, and a motor current command. There are signals, and the signals input through the input circuit 9 include sensor signals such as a position sensor, a speed sensor, and a current sensor.

If the output circuit 8 includes a digital-analog conversion circuit, the split-type I / O device 5A can output analog signals. If the input circuit 9 includes an analog-digital conversion circuit, analog signals can be input. It is.

The I / O device side transmission control circuit 2A outputs the data transmitted through the data transmission line 3 to the output circuit 8, while transmitting the data obtained through the input circuit 9 to the processor 4 through the data transmission line 3. Circuit.

FIG. 3 shows the concept of a signal passing through the data transmission line 3, and FIG. 4 shows a configuration example of one block of the signal.
Further, in the following description, “0” indicates that there is no signal.
The level is set to “1” when there is a signal. The left side of the figure is a preceding event, and the right side is a subsequent event. In FIG. 4, the header H indicates the head of one block, and is set to the “1” level. The request bit R, which is normally at “0” level,
This is a bit for synchronization with the I / O device side transmission control circuit 2A. DATA in the third column is data of a fixed length such as 8 bits and 16 bits.
The end is a parity bit P, which has a fixed length as a whole block.

These data blocks are sequentially transmitted on the data transmission path 3 as shown in FIG. FIG. 3 (a) shows a signal transmitted from the processor to the separation type I / O device, and FIG. 3 (b) shows a signal transmitted from the separation type I / O device to the processor.

Hereinafter, a data transmission method in the device having the above configuration will be described. After the power is turned on, the processor-side transmission control circuit 1 instructs the processor-side transmission control circuit 1 to signal the start of transmission by "1" for R and the number of words to be transmitted to DATA (hereinafter, imax).
And send the block with. After the transmission of the first block, the block of word 0 is transmitted after a pause period of several clocks designed in advance, and thereafter, the block is transmitted in order of word 1, word 2, and so on. When the transmission is completed up to the word imax, the process returns to the word 0, and the transmission is repeated indefinitely as the word 1, the word 2, and so on. In the transmission of word 0, word 1, word 2... Word imax, R is set to the "0" level. The transmission example in FIG. 3 is a case where imax is set to 10. At this time, the transmission control circuit 1 on the processor side transmits the transmission control circuit 2 on the I / O device side.
The data of word 0 to word imax sent to A need not necessarily be a control signal or the like having a specific meaning.

On the other hand, the I / O device side transmission control circuit 2A receives the first block in which R is at the “1” level, and starts operating. The received imax value is stored in its own register.
After completion of the reception of the block having the “1” level, a block of word 0 taken out from the input circuit 9 is transmitted to the processor-side transmission control circuit 1 after a pause of several clocks. 2 and so on. When the transmission is completed up to the word imax, the process returns to the word 0, and the transmission is repeated indefinitely as the word 1, the word 2, and so on. The processor-side transmission control circuit 1 ignores the value of the R bit of the received data block and stores the received data at a predetermined address in the internal memory 11 in the order of reception. Thus, R
By using bits, data could be transmitted without transmitting the address of bidirectional transmission data each time.
If the transmitted block is word 0, it is clear that the simultaneously received block is word 0. In the idle period, the number of clocks required for the determination of the R bit and the P bit, preparation for transmission, and the like are set at the time of circuit design.

The transmission and reception data is extracted or stored from the memory 11 in the processor-side transmission control circuit 1,
In the I / O device-side transmission control circuit 2A, an address signal is output from the I / O device-side transmission control circuit 2A to the address line corresponding to the word i. It is input to the transmission control circuit 2A on the side, or output from the transmission control circuit 2A on the I / O device side to the output circuit 8.

FIG. 2 shows a second embodiment of the present invention. This embodiment is different from the first embodiment in that the I / O device side transmission control circuit 2
B includes a memory 11 similarly to the processor-side transmission control circuit 1, and further includes an input circuit 9, an output circuit 8, and an I / O
The point is that a CPU 7B is provided so as to be connected to the device-side transmission control circuit 2B. In the present embodiment, transmission and reception data are taken out of the memory 11 or stored in both the processor-side transmission control circuit 1 and the I / O device-side transmission control circuit 2B. In the separation type I / O device 5B, the signal input to the input circuit 9 is stored in the memory 11 of the I / O device side transmission control circuit 2B by the CPU 7B, and the memory 11 of the processor side transmission control circuit 1 is processed according to the above-described procedure. Are sequentially transmitted. The signal output to the controlled object 6 is transferred from the memory 11 of the I / O device side transmission control circuit 2B to the output circuit 8 by the CPU 7B. That is, the present embodiment is different from the first embodiment in that the portion for holding data has two stages of the input / output circuits 8, 9 and the memory 11.

According to this embodiment, the memory is built in the transmission control circuit, and the memory in the transmission control circuit on both the upper (processor) side and the lower (I / O device) side has some time delay, Data transfer is automatically performed as if the same data is stored from outside the control circuit, eliminating the burden on the CPU described above and only writing data to the memory of the transmission control circuit. The necessary data can be obtained simply by reading the data from the memory at the same time as the data is transferred. According to this method, the transmission of the address becomes unnecessary, and the ratio of the meaningful data transmitted to the transmission bit rate can be improved. In addition, since data transmission is performed autonomously and cyclically, the load on the external circuit due to data transmission is reduced, and there is no need to design programs or design circuits with awareness of data transmission, Simplification of programs and external circuits has become possible.

At a certain point during transmission, when it is desired to change the range of data to be repeatedly updated, or when a specific data is urgently required, etc., the request bit R is set to "1" by a command from the CPU 7A, and a new data is stored in DATA. A block carrying the value of imax can be transmitted. I / O device side transmission control circuit 2A
Alternatively, 2B determines that the value of imax has been updated because R is "1", stores the new imax value in its own register, and sets the next block to be transmitted to the word 0.
, And thereafter, blocks of word 1, word 2,... Are sequentially transmitted. After transmitting the block in which R is set to "1", the processor-side transmission control circuit 1 also returns R to "0" and resumes transmission / reception of word 0. Thus, for example, when the time when a large amount of data is required, such as when the apparatus is started, ends, and when the required data amount is reduced by entering the steady operation, the number of data to be updated is reduced by reducing the imax value, and Performance (responsiveness) can be improved. In addition, when the data of words 0 to imax are arranged in the order of higher importance and smaller numbers, and only the important data is to be monitored in real time, imax is limited to the range including the important data. Even immediately after the transmission of the data, it is possible to promptly retransmit the data.

FIG. 5 shows an example of a block diagram of the processor-side transmission control circuit 1. This is common to the I / O device side transmission control circuit 2B. The illustrated processor-side transmission control circuit 1 includes a randomly accessible memory 11 connected to a data input / output terminal 25 via a memory interface circuit 16;
Another memory interface circuit 17 connected to 11
A synchronization control circuit 19 connected to the memory interface circuit 17; a clock input terminal 24 connected to the synchronization control circuit 19 via a reception control circuit 15;
A synchronous clock output terminal 22 connected to the transmission control circuit 13 via a transmission control circuit 13; a data reception terminal 23 connected to the reception control circuit 15 via a serial / parallel conversion circuit 14;
13 includes a data transmission output terminal 21 connected via a parallel / parallel conversion circuit 12 and an arbitration circuit 18 connected to the memory interface circuits 16 and 17. The memory interface circuit 17 is also connected to the serial / parallel conversion circuit 12 and the serial / parallel conversion circuit 14. Further, the memory 11 includes:
It is divided into a transmission signal storage section 11A and a reception signal storage section 11B.

The operation of the transmission control device having the above configuration will be described below. Data input from the data input / output terminal 25 is transmitted to the transmission signal storage unit 11 of the memory 11 through the memory interface circuit 16.
Written to A. The data written in the transmission signal storage unit 11A is sent to the parallel / parallel conversion circuit 12 via the memory interface circuit 17, converted into a serial signal, and transmitted from the data transmission output terminal 21. This signal is synchronized with the transmission clock output from the synchronization clock output terminal 22.

The serial signal input to the data receiving terminal 23 is converted into a parallel signal by the serial / parallel conversion circuit 14, and is written to the reception signal storage unit 11B of the memory 11 via the memory interface circuit 17. When a read command is input to the data input / output terminal 25, the data written to the received signal storage unit 11B is transmitted to the data input / output terminal 25 via the memory interface circuit 16.
Is output to When both of the memory interface circuits 16 and 17 try to access the memory 11 at the same time, the arbitration circuit 18 works to access the memory with the higher priority first.

The serial signal input to the data receiving terminal 23 is synchronized with the clock signal input to the clock input terminal 24,
By using this clock signal, it is correctly converted to a parallel signal. It is also possible to configure an asynchronous transmission control circuit using an internal clock that is sufficiently high with respect to the bit rate of the serial signal of the data transmission output terminal 21 and the data reception terminal 23.

However, the frequency of the clock output from the synchronous clock output terminal 22 and the frequency of the clock input to the clock input terminal 24 must be the same or similar.

Next, data and addresses of the memory 11 will be described. The memory 11 will be described as a 32-word configuration having addresses 0 to 31 (decimal numbers, hereinafter all represented in decimal numbers). The addresses of the transmission signal storage unit 11A are 0 to 15, and the addresses of the reception signal storage unit 11B are 16 to 31. By the initial synchronization by the synchronization control circuit 19, while the data written to the address 0 is being transmitted, the data received from the data receiving terminal 23 at the same time is written to the address 16 after the parallel conversion. Next, the data at the address 1 is transmitted, and the data received at the same time is written to the address 17. Next, the addresses are incremented so that addresses 2 and 18 are pairs of transmission and reception. When the data transmission / reception of the preset final address (for example, if imax is set to 10, the pair of addresses 9 and 25 becomes the final address) is completed, the data returns to the pair of addresses 0 and 16 and the data is transmitted again. And continue receiving.

FIG. 6 is a block diagram showing an embodiment of the configuration of the I / O device-side transmission control circuit 2A of FIG. 1, and is different from the example shown in FIG. There is no arbitration circuit 18 and it is connected to the memory interface circuit 17 to connect to the reception address counter 27 and the transmission address counter 28
Is provided. The transmission control circuit outputs the value of the transmission address counter 28 and the read command from the input / output terminal 25, receives transmission data from a register outside the transmission control circuit, and transmits the received transmission data to the synchronization control circuit 19, the transmission control circuit. 13, Data transmission output terminal 2 via parallel-to-parallel conversion circuit 12
Output from 1. When the received data is input via the data receiving terminal 23, the value of the receiving address counter 27 and the write command are output from the input / output terminal 25, and the received data is stored in a register outside the transmission control circuit. Each address counter is incremented each time its value is used once, and the value of the address counter incorporated in the transmission control circuit paired with the transmission control circuit also counts up almost in synchronization.

FIG. 7 shows a connection state between the transmission control circuit 1 and the external registers 29 and 30 shown in FIG. According to the present embodiment, when transmitting and receiving data from a register such as a flip-flop, the transmitting and receiving data is transmitted and received without using a controller for communication control, so that there is no redundancy in terms of economy and function. There is an effect that transmission control can be performed.

〔The invention's effect〕

According to the present invention, data in a predetermined range at the lower end of the transmission path is repeatedly transmitted in the order determined in the memory at the upper end of the transmission path, and the memory at the upper end of the transmission path is constantly updated with the latest data. Therefore, there is no need to add an address for each data and transmit the data, and the number of transmission bits is reduced, and the transmission speed is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a first embodiment of the present invention, FIG. 2 is a block diagram showing a second embodiment of the present invention, and FIG. 3 explains an order of data to be transmitted. FIG. 4 is a conceptual diagram showing a configuration example of data to be transmitted,
FIG. 5 is a block diagram showing an embodiment of the transmission control circuit of the present invention, FIG. 6 is a block diagram showing another embodiment of the transmission control circuit of the present invention, and FIG. 7 is an embodiment shown in FIG. FIG. 3 is a block diagram showing a connection state between the external register and the external register. 1 ... Processor side transmission control circuit, 2A, 2B ... I / O device side transmission control circuit, 3 ... Transmission path, 4 ... Control device, 5A, 5B
... I / O device, 6 ... controlled object, 7A, 7B ... CPU, 8 ... output circuit, 9 ... input circuit, 11 ... memory, 12 ... parallel-to-linear conversion circuit, 13 ... transmission Control circuit, 14 …… Series-conversion circuit, 15
...... Reception control circuit, 16, 17 ... Memory interface circuit, 18 ... Arbitration circuit, 19 ... Synchronization control circuit, 21 ... Data transmission output terminal, 22 ... Synchronous clock output terminal, 23 ...
Data transmission terminal, 24 clock input terminal, 25 data input / output terminal, 27 reception address counter, 28
Transmission address counters, 29, 30 ... external registers.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 29/02 G06F 13/00

Claims (2)

(57) [Claims] 1. A transmission apparatus comprising: a transmission path for transmitting a serial signal bidirectionally; and a pair of transmission control circuits connected to the transmission path for transmitting and receiving data. On the side, a memory for storing the transmission signal and a parallel-to-parallel conversion circuit that extracts the transmission signal stored in the memory in a predetermined order, converts it into a serial electric signal, and sends it out as a data block having a fixed data length. Provided, on the receiving side of each transmission control circuit, a serial-parallel conversion circuit for parallelizing the received data blocks and a memory for storing the output of the serial-parallel conversion circuit in a predetermined order,
The pair of transmission control circuits, when starting transmission of the data block converted to the serial electric signal after transmitting a signal defining the number of data blocks transmitted by either one to the other transmission control circuit, the other The transmission control circuit of
The received data block is subjected to serial-parallel conversion and stored in the memory for storing the reception signal in the predetermined order, and the transmission signals stored in the memory for storing the transmission signal are extracted and rearranged in the predetermined order. Converting, and sending the parallel-converted data block to the one transmission control circuit in accordance with sending each data block from the one transmission control circuit to the other transmission control circuit. A transmission device characterized by the above-mentioned. 2. The transmission apparatus according to claim 1, wherein each transmission control circuit stores a transmission operation including fetching a transmission signal from a memory in which the transmission signal is stored, parallel-conversion, and transmission. Performed in the order of the addresses of the memory, and performed an update operation of storing the output of the serial-parallel conversion and the serial-parallel conversion circuit of the received data block in the memory in the address order, and when the transmission of the specified number of data blocks is completed, The transmission operation is repeated by returning to the first address of the memory storing the transmission signal, and the updating operation is repeated by returning to the first address of the memory storing the output of the serial-parallel conversion circuit in address order. A transmission device characterized by the above-mentioned.