JP3014786U - Intra-station line terminal tester - Google Patents

Abstract

(57) [Summary] [Purpose] By displaying the operating status of each data line, simplifying the operation points and display section and displaying the lamps along the flow of data, it is possible to easily identify the failure point. To [Structure] A waveform conversion circuit 1 for adjusting a clock timing and converting it into a unipolar signal, a shift register circuit 2 for temporarily storing a pulse for one period, and a time-synchronization pulse which coincides with a predetermined pattern. A frame synchronization detection circuit 3 for outputting synchronization information, a multi-frame selection circuit 4 for extracting octet information selected by a switch, an octet holding circuit 5 for holding information in units of octets until a synchronization pulse of the frame synchronization detection circuit arrives, A display circuit 6 is provided for displaying information necessary for fault determination based on the output of the frame synchronization detection circuit and the output of the octet holding circuit, and a speaker for producing a low frequency sound for confirming the line state is further provided.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a tester for an intra-station line terminating device for connecting to a line terminating device of a multiplex radio station, which is a constituent element of a radio multiplex transmission line, and for easily determining the quality of a data line and a fault location.

[0002]

[Prior art]

 In the wireless multiplex transmission line, the change from the frequency division modulation system to the pulse code modulation (hereinafter referred to as PCM) system is rapidly progressing in recent years. In this PCM system, transmission efficiency is improved by multiplexing data for up to 20 lines in one telephone conversion channel. FIG. 2 shows a configuration example of such a transmission line. The lines accommodated in the transmission line in Fig. 2 include operation management information, immediate processing data, batch processing data, image information, facsimile information, etc. The maintenance staff conducted a separate test for each related device to determine the faulty section. However, the data multiplexer does not have an operation status display for each data line. Therefore, conventionally, in order to determine the quality of this type of data line and the location of a failure, for example, in order to check the operation of one line, operation was stopped with other 19 lines in the same group, and a commercially available general-purpose measuring instrument was used. It was

[0003]

[Problems to be solved by the device]

 The above general-purpose measuring instrument is expensive and difficult to realize even if it is desired to place it in all the necessary places. Also, if people carry it with them each time, there are many problems in terms of time required and transportation method. Furthermore, as mentioned above, in the event of a failure, it is necessary to stop the operation of many lines that are not directly related to each other for the isolation test. Since the measuring instrument used was multi-functional, the operation was complicated and there were drawbacks such as it took too long to search for a fault.

The object of the present invention is to solve such problems, to display the operating state of each data line, to simplify the operation part and the display part, and to display the lamp along the data flow. The purpose is to provide an inexpensive and easy-to-use tester for intra-station line termination equipment that can easily identify a fault location.

[0005]

[Means for Solving the Problems]

 In order to achieve the above-mentioned object, the tester for the line terminating equipment of the present invention inputs the data and clock composed of bipolar signals and supplies the data of the non-zero return signal without error to the next circuit. The waveform conversion circuit 1 that adjusts the clock timing so that the clock rises in the center of the signal and converts it to a unipolar signal, and the data generated by the waveform conversion circuit 1 are input and that data is input to the clock. A frame register composed of a combination of a shift register circuit 2 that can shift each rising edge and temporarily store a pulse for one cycle, and a frame sync bit from the shift register circuit 2 and an AND circuit. A frame that outputs a sync pulse and sync information when the pattern detection circuit verifies and matches a predetermined pattern. From the multi-frame selection circuit 4 and the multi-frame selection circuit 4, which is composed of a phase detection circuit 3, a rotary switch and a shift register, and which extracts the required octet information from the shift register circuit 2 by the rotary switch. Based on the octet holding circuit 5 that holds the input information in units of octets until the synchronization pulse from the frame synchronization detection circuit arrives, and the output of the frame synchronization detection circuit 3 and the output of the octet holding circuit 5. The configuration is provided with a display circuit 6 that displays items and information necessary for determining the cause of failure. Further, the speaker 62 is connected to the octet holding circuit 5 and outputs a low frequency sound for confirming the line status at the device connection point, and a terminal for external connection of the waveform observing device.

[0006]

【Example】

 Next, the present invention will be described in detail with reference to the drawings. First, the operating principle of this embodiment will be described. FIG. 2 is a system system diagram showing a configuration example of a wireless multiplex transmission line to be used by the tester of this embodiment. In FIG. 2, 10 and 20 are carrier terminal devices connected by the same microwave multiplex transmission line 30. Reference numeral 11 denotes an intra-station line terminating device connected to the carrier terminal device 10. Reference numeral 12 is a data line terminating device connected to the intra-station line terminating device 11. 13a ... 13x are terminal devices connected to the data line terminating device 12. Reference numeral 14 is a connection point of this embodiment on the side of the intra-station line terminating device 11. Reference numeral 21 denotes an intra-station line terminating device connected to the carrier terminal device 20. Reference numeral 22 is a data line terminating device connected to the intra-station line terminating device 21. 23a ... 23x are terminal devices connected to the data line terminating device 22. Reference numeral 24 is a connection point of this embodiment on the side of the intra-station line termination device 21.

FIG. 3 is an explanatory diagram showing a pulse configuration in the intra-station line terminating device 11 (21). 64 kbps data of the 0th-order group of PCM (at points 14 or 24) connected to the carrier terminal apparatus 10 (20) of the intra-station line terminator 11 (21) has 1 octet (8 bits) pulse of 20 It adopts a method of repeatedly transmitting every time. A set of octets of 1 to 20 is called a multiframe, and the combination of the frames is changed and transmitted according to the bearer speed input to the intra-station line terminating device 11 (21). The line number of the bearer signal corresponds to the multiframe. The correspondence between the multiframe number and the multiplexed line number is shown in the explanatory diagram of FIG.

According to the principle of the present embodiment, when the transmission of 20 octets is completed at the 64 Kbps point of the 0th order group of PCM and the X-50 pattern of the frame bit is detected, the synchronization is established. However, when the bearer signal is 64 Kbps and the frame pattern is repeated and 0 is set, the 8K clock superimposed on the 64K clock is synchronized with the frame bit for synchronization. From this point on, the bit status in octet units is retained and displayed until the next synchronization is achieved. The octet status items such as DNR and UNR can also be known from this octet-based information.

FIG. 1 is a circuit system diagram showing a configuration of an embodiment of the present invention. In FIG. 1, 1 is a waveform conversion circuit, 2 is a shift register circuit, 3 is a frame synchronization detection circuit, 4 is a multi-frame selection circuit, 5 is an octet holding circuit, and 6 is a display circuit. The waveform conversion circuit 1 inputs data of 64 Kbps which is a bipolar signal (bipolar) and a clock of 64 Kbps, and converts it into a unipolar signal (unipolar). However, the data is a high impedance input. In order to supply error-free data to the next circuit, the NRZ code is created by adjusting the clock timing so that the clock rises at the center of the data.

The shift register circuit 2 is a circuit for obtaining bit information when a pulse for one cycle is stored in this shift register, and 8 bit shift registers are connected in series in 20 stages. Here, the input data created by the waveform conversion circuit 1 is shifted at each rising edge of the clock. As shown in FIG. 3, the pulse configuration of the intra-station line terminator is 1 octet 8 bits and the number of frames is 20, so a 160-bit (8 × 20) pulse is temporarily transferred to the shift register circuit 2 in one cycle. Can be memorized.

The frame synchronization detection circuit 3 is composed of a combination of AND circuits, and takes out 20 frames of the frame synchronization bit, which is the first bit of one octet, from the shift register circuit 2 and compares it with the reference pattern. When it matches “A1101001000010101110”, the sync pulse and the sync information are output. However, if the bearer signal is 64 Kbps and the frame synchronization pattern is repeatedly set to 0, the 8K clock superimposed on the 64K clock is taken out by the 8K extraction circuit, and the clock is used for synchronization. The sync pulse generated here is used as a timing pulse for frame No selection of the multi-frame selection circuit and a display update pulse of the octet holding circuit.

The multi-frame selection circuit 4 is composed of a rotary switch and one 8-bit shift register, and each register (20 pieces) of the shift register circuit 2 has fixed information in units of octets when synchronized. Since it remains as it is, the same octet information as the shift register selected by the multi-frame No select (rotary switch) is taken out by this circuit. The octet holding circuit 5 is a circuit for holding until the 8-bit information in octet units from the multi-frame selection circuit 4 arrives.

The display circuit 6 displays various lamps based on the octet information of the octet holding circuit 5 and the synchronization information of the frame synchronization detection circuit 3. The lamps and other elements of the display section are all arranged centrally on the front surface of this embodiment. FIG. 5 is a front view showing the outer appearance of this embodiment. In FIG. 5, 30 is a power switch and 31 is a power indicator lamp. Reference numeral 32 is a data pulse input display lamp, and 33 is a clock pulse display lamp. Reference numeral 34 is a frame synchronization normal display lamp, 35 is a frame synchronization abnormal display lamp, 36 is a SEND information display lamp, 37 is a multiplex transmission line failure, game data transmission disconnection display lamp, and 38 is a bit error rate defective display lamp.

Reference numeral 39 is a multi-frame number selection switch. Reference numerals 40 to 47 are 8-bit display lamps of F to S. Reference numeral 50 is a terminal device operating indicator lamp, 51 is an operation stop or test indicator lamp, 52 is a data line terminal device failure indicator lamp, and 53 is a terminal device failure indicator lamp. Reference numeral 60 is a bit selection switch. 61 is a knob for adjusting the volume of the low frequency sound of the bit selected by the bit selection switch 60. Reference numeral 62 is a speaker that generates the low frequency sound.

The lighting operation of each display lamp will be described below. The power supply indicator lamp 31 lights up when the power switch 30 is turned on. The DATA IN and CLK IN lamps 32 and 33 are turned on when there is an input pulse from the waveform conversion circuit 1. The SYNC OK lamp 34 continues to be lit while the synchronization is normal after receiving the sync pulse from the frame sync detection circuit 3 and passing through the holding circuit having a time constant slightly longer than the cycle of the sync pulse.

The REC lamp 35 is lit according to the frame synchronization abnormality information from the frame synchronization detection circuit 3, and is therefore lit when the 64K input data is interrupted or the synchronization is abnormal, but the lighting is prohibited during the AIS reception. The SEND lamp 36 lights up according to the SEND information from the partner station (when the 160-bit head bit is 0). The SEND information from the shift register is taken out and turned on by synchronizing the timing with a synchronizing pulse. However, when the frame synchronization pattern is set to 0 repeatedly, the SEND information cannot be transmitted, so the lighting is prohibited.

The AIS lamp 37 is lit when the 64K input data are all 1. It is lit by ANDing the output of the waveform conversion circuit 1 and the frame synchronization abnormality from the frame synchronization detection circuit 3. The ERR lamp 38 monitors the missing bits of the frame sync pulse as an error monitor, and lights it at a bit error rate of about 1 × 10 ⁻⁴ . The F, D1 to D6, and S lamps display the 8 bits from F to S output from the octet holding circuit 5. The OPE lamp 50 lights up when the S bit is 1.

The TEST lamp 51 lights up when the S bit is 0. However, lighting is prohibited during DNR and UNR reception. The DNR lamp 52 is turned on when the detection circuit formed by the combination of the AND circuits collates it and the patterns D1 to S match "0000000". The UNR lamp 53 is turned on when the pattern of D1 to S is matched with “0010100” in the detection circuit configured by the combination of AND circuits.

Next, a usage example of this embodiment will be described. If there is a report that there is a failure in the line that goes through the intra-office line terminating device (hereinafter referred to as OCE), check the line usage classification, and the No. of the OCE rack that accommodates this line, the channel No. Check No and immediately check if the alarm for the OCE alone is issued. Next, in order to confirm the input / output status of 64K data of OCE, a clock cable and a measurement cable are connected to OCE as shown in FIG. 6 (an explanatory view showing a usage example of this embodiment). At this time, connect the clock cable to the clock output of the OCE alarm board, and connect the measurement cable to the 64K data input / output of OCE. This connection point corresponds to 14 or 24 in FIG. In FIG. 6, D on the upper side is a use example of the present embodiment when a DNR alarm is issued, and U on the lower side is a use example of the present embodiment when a UNR alarm is issued. Further, the carrying end is a carrier terminal device, OCE is an in-office line terminating device, DSE is a data line terminating device, and DTE is a data terminal device.

Then, it is confirmed whether 64K data and a clock pass. In this case, if normal, the DATA and CLK lamps (32, 33) are turned on. Next, it is confirmed whether the input / output 64K data is normal. If it is normal, the SYNC OK lamp (34) lights up. However, if any of the REC (35), SEND (36), AIS (37), and ERR (38) lamps are lit, there is an error in the 0th-order group 64K data system of the OCE and carrier terminal equipment. It is judged that there is. Further, the switch (39) for selecting the multi-frame No. of this embodiment is switched to the frame No. of the line to be confirmed. However, if the transmission rate for one channel is 64K, this operation is not necessary.

In this way, as shown in FIG. 6, the faulty section is determined by the DNR and UNR. The operational status of the line can be confirmed from the lighting status of the OPE (50), TEST (51), and OCTET (40 to 47) lamps. Also, since the line can be monitored by the sound from the speaker (62), it is possible to check at a distant place, and the maintenance staff is busy on the phone or other work. It is possible to grasp the situation. The display items and display contents of the display circuit 6 are summarized in Table 1 below.

[0022]

[Table 1]

[0023]

[Effect of device]

 As described in detail above, the present invention displays the operating status of each data line, simplifies the operation part and the display part, and displays the lamp along the flow of data, so that the failure part can be easily specified. The advantage is that an inexpensive and easy-to-use tester for intra-station line termination equipment can be obtained. Furthermore, by enabling the line to be monitored by the speaker, the effect of being able to check at a remote place is added.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a system system diagram showing a configuration example of a wireless multiplex transmission line used in this embodiment.

FIG. 3 is an explanatory diagram showing a pulse configuration in an intra-station line termination device.

FIG. 4 is an explanatory diagram showing an example of correspondence between multiframe numbers and multiplexed line numbers.

FIG. 5 is a front view showing the appearance of the present embodiment.

FIG. 6 is an explanatory diagram showing a usage example of the present embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 waveform conversion circuit 2 shift register circuit 3 frame synchronization detection circuit 4 multi-frame selection circuit 5 octet holding circuit 6 display circuit 10, 20 carrier terminal station device 11, 21 intra-station line termination device 12, 22 data line termination device 13a, 13x, 23a, 23x Terminal device 14, 24 This embodiment connection point 31, 32, 33, 34, 35, 36, 37, 38, 4
0,41,42,43,44,45,46,47 Indicator lamp

Claims (2)

[Scope of utility model registration request] 1. A clock timing is adjusted so that a clock and a clock rise in the center of the data in order to input a data and a clock composed of a bipolar signal and to supply the error-free non-zero return signal data to the next circuit. Then, a waveform conversion circuit for converting into a unipolar signal and data generated by the waveform conversion circuit are input, and the data can be shifted at each rising edge of the clock to temporarily store a pulse for one period. The shift register circuit and the frame synchronization bit are taken out from the shift register circuit, collated by a frame synchronization pattern detection circuit configured by a combination of AND circuits, and if they match a predetermined pattern, a synchronization pulse and synchronization information are output. It is composed of a frame synchronization detection circuit, a rotary switch and a shift register. A multi-frame selection circuit that extracts the required octet information from the shift register circuit by the rotary switch, and information in units of octets input from the multi-frame selection circuit until the synchronization pulse from the frame synchronization detection circuit comes. Octet holding circuit for holding for a period of time, and a display circuit for displaying items and information necessary for fault cause determination based on the output of the frame synchronization detection circuit and the output of the octet holding circuit For tester. 2. The intra-station line terminating device according to claim 1, further comprising: a speaker connected to the octet holding circuit and emitting a low-frequency sound for confirming a line state at a device connection point, and a terminal for externally connecting the waveform observing device. For tester.