JP3136222B2 - Voice communication device using ISDN - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voice communication method using ISDN (Integrated Services Digital Communication Network) for communicating voice data of high sound quality using ISDN, and an apparatus therefor.

[0002]

2. Description of the Related Art The prior art is disclosed in Japanese Patent Laid-Open No. 2-7752.
This is disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2000-95 "Compound terminal device for ISDN".
A conventional technique will be described with reference to FIG.

[0003] The ISDN 101 is an ISDN composite terminal 10.
2 is an exchange network for exchanging information between the ISDN 2 and the ISDN composite terminal 103. In the ISDN composite terminal 103, the layer 1 interface 131 matches electrical and physical conditions for connecting the terminal to the switching network. That is, connection conditions in the seven physical layers of the open system interconnection (OSI) are prepared. The Bch synchronization data generator 137 generates B channel synchronization data to be transmitted to synchronize the data strings of the B1 channel and the B2 channel. The Bch transmission unit 133 transmits the B channel data and the B channel synchronization data obtained from the Bch synchronization data generation unit to the other communication terminal via the layer 1 interface 131. Bch data receiving unit 134
Receives the B channel data transmitted from the composite terminal 102 via the layer 1 interface 131.
The synchronization algorithm storage unit 138 stores a synchronization algorithm for correcting the data strings so as to synchronize the data strings of the B1 and B2 channels.

Next, the operation of the above conventional configuration will be described. First, a transmission data sequence is transmitted from the Bch data transmission unit (not shown) of the ISDN composite terminal 102 via the ISDN 101. The ISDN composite terminal 103 checks the order of the data string received via the layer 1 interface 131, and corrects the data string for synchronizing the data strings of the next B1 channel and B2 channel. Specifically, the correction data is obtained by delaying each data of the B2 channel received by the Bch data synchronization unit 135 by n data. In order to perform this data string correction, a synchronization algorithm is stored in the synchronization algorithm storage unit 138, and the Bch data synchronization unit 135 is stored.
Then, using the synchronization algorithm, the data strings of the subsequent B1 channel and B2 channel are synchronized.

As described above, there is a method of synchronizing two B channels and transmitting one piece of information using two B channels.

On the other hand, audio information which is an analog signal is
Although the technique of transmitting using one B channel of the DN is well known, the bandwidth of the audio signal is limited to 0.3 to 3.4 kHz, and the audio quality is not good.

To solve this, as described above,
There has been proposed a method of transmitting voice information of high sound quality by synchronizing two B channels and transmitting voice information (with two B channels) at an increased bearer communication speed.

[0008]

However, in the above prior art, since the specifications (transmission band, stereo / monaural, etc.) of the audio information to be transmitted are fixedly determined, the entire apparatus is changed according to the purpose of use. There was a problem that had to be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a voice communication method using an ISDN for freely selecting high-quality voice information of a specification according to a specification purpose by using one or a plurality of B channels, and a voice communication method using the same. It is to provide a device.

[0010]

SUMMARY OF THE INVENTION A voice communication apparatus using an ISDN according to the present invention is a communication terminal apparatus which performs digital signal communication at a desired bearer communication speed using at least one communication channel via the ISDN. Connect and analog
A voice communication device that transmits voice signals via ISDN.
From the communication terminal device according to the digital communication speed.
Receiving means for receiving a timing signal
A / D converter for converting analog signals to digital audio signals
Conversion means, and a digital audio signal from the A / D conversion means.
Compression means for compressing the
Expansion means for expanding the digital audio signal
Digital audio signal from analog means to analog audio signal
Indicates D / A conversion means for conversion and monaural / stereo
Setting means for setting the format of the audio signal;
From the received timing signal and the setting means
The A / D conversion means and the compression means based on the
Operation clock of the D / A conversion means and the decompression means
Means for creating and supplying clocks
Characterized by comprising.

Further, the voice communication apparatus using ISDN of the present invention includes a first communication terminal apparatus for communicating digital signals at a desired bearer communication rate using at least one communication channel via ISDN . 2 communication terminals
A voice communication device connected to each other and transmitting an analog voice signal via ISDN, wherein the voice communication device on the transmitting side is provided.
Is the digital communication speed from the first communication terminal.
Receiving means for receiving a timing signal according to
And the format of the audio signal indicating monaural / stereo
First setting means for digitizing the input analog signal.
A / D conversion means for converting the signal into a digital audio signal;
Compression means for compressing the digital audio signal from the conversion means
And a timing signal received by the first receiving means.
And the format read from the first setting means,
An operation clock for the A / D conversion means and the compression means is generated.
And a first timing clock generating means for generating and supplying a second communication terminal to the voice communication device on the receiving side.
Timing according to the digital communication speed from the device
Second receiving means for receiving the signal, and the transmitted audio signal
A second setting means for setting the format, and receiving from the ISDN
Expanding means for expanding a compressed digital audio signal
And a digital audio signal from the decompression means.
D / A conversion means for converting into an audio signal, and the second reception
The timing signal received by the means and the second setting means.
The D / A conversion means based on the format read from the column
And an operation clock for generating and supplying the operation clock of the decompression means.
And timing clock generating means .

[0012]

According to the voice communication method and apparatus using the ISDN of the present invention having the above-described structure, voice transmission using the single or a plurality of B channels according to the specification according to the purpose of use is performed by the IS.
This can be performed using DN. Therefore, in a radio station or the like that provides various programs such as a sports broadcast and a concert broadcast, the audio signal can be relayed by using the ISDN according to the specifications to be relayed.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a configuration of a system for simultaneously using the B1 channel and the B2 channel as a transmission / reception transmission line of the ISDN basic interface, dividing audio information into a plurality of division data at a communication speed of 128 kbps, and transmitting the divided data. FIG. In FIG. 1, reference numeral 201 denotes one ISDN terminal device (hereinafter, simply referred to as a terminal);
202 is the other terminal. In the terminal 201, 23
Is a microphone for inputting audio signals, 22 is a speaker for outputting audio information from the terminal 202, 1 is a microphone 23, an audio information amplifier (hereinafter simply referred to as an amplifier) connecting the speaker 22, and 2 is an amplifier 1 A / D-converts and encodes audio information obtained from the microphone 23 and decodes the audio information from the terminal 202 and D / A-converts it, and 3 denotes an audio codec 2 And a divided transmitting means for dividing the audio information and transmitting the divided data to the other terminal, and a divided receiving means for receiving the divided data transmitted from the other terminal 202. This is a terminal adapter for connecting the B1 channel and the B2 channel to the other party via the signal line 11 and the ISDN.

Reference numeral 13 denotes an ISDN for connecting the terminal 201 and the terminal 202. In the terminal 202, 6 includes an input signal line 5 and an output signal line 10, and includes a division transmission unit and a division reception unit.
A terminal adapter 7 for connecting to the other party via the SDN 13 decodes the audio information from the terminal 201 via the ISDN 13, performs D / A conversion on the audio information, and converts the audio information to be transmitted to the terminal 201 into an A / D converter. An audio codec device for performing the / D conversion and encoding the same, 8 is a broadcast facility such as a radio station, and 9 is an antenna provided in the broadcast facility 8.

Next, the communication operation of the configuration shown in FIG. 1 will be described, for example, with the terminal 201 as the transmitting side and the terminal 202 as the receiving side.

FIG. 2 shows a synchronization sequence as a call connection procedure after a call is set up. The synchronization sequence includes two sequences, a synchronization establishment sequence and a synchronization confirmation sequence. First, the synchronization establishment sequence process and the synchronization confirmation sequence process executed by the terminal adapter 3 on the transmitting side will be described with reference to the flowcharts shown in FIGS.

In the originating-side synchronization establishment sequence processing shown in FIGS. 3 and 4, after completing the originating connection, the terminal adapter 3 activates an overall timer for monitoring the completion of the synchronization sequence (step S1), and all data bits are set. The synchronization pattern 1 of "0" is transmitted to the B1 channel (step S2). Thereafter, the reception of the synchronization pattern 1 in the B1 channel is waited (step S3), and if received, the synchronization pattern 1 is transmitted to the B2 channel (step S4). After that, it waits for reception of the synchronization pattern 1 on the B2 channel (step S5), and if received, sends out the synchronization pattern 2 in which all data bits are "1" to the B1 channel and the B2 channel (step S6). Then B
It waits for the reception of the synchronization pattern 2 on the 1 channel and the B2 channel (steps S7 and S8), and if it is received, the synchronization pattern 3 in which all data bits are “0”.
Is transmitted to the B1 channel and the B2 channel (step S9). That is, by transmitting the synchronization pattern 2 in which the data bits are all "1" and between the synchronization patterns 1 and 3 in which the data bits are all "0", the receiving side clearly defines the synchronization patterns 1, 2, and 3. Can be distinguished. After that, the reception of the synchronization pattern 3 on the B1 channel and the B2 channel is waited (step S10). If the synchronization pattern 3 is received, the synchronization establishment sequence process is terminated and the process proceeds to the synchronization confirmation sequence (step S11).

Steps S12 to S1
In 6, when waiting for the reception of the synchronization patterns 1, 2, and 3, an overall timeout occurs, a call disconnection process is performed (step S17).

In the originating-side synchronization confirmation sequence processing shown in FIG. 5, the terminal adapter 3
Byte synchronization confirmation data is transmitted (step S18),
A reception waiting timer is started (step S19). Then, it is monitored whether a timeout has occurred (step S20),
If it is not a timeout, it is determined whether or not a synchronization failure notification in which all eight bytes are “55” as shown in FIG. 11 has been received (step S21). If the synchronization failure notification has not been received, it is determined whether or not data that does not match the synchronization confirmation data transmitted in step S18 has been received (step S22). If the unmatched data has not been received, it waits for the received synchronization confirmation data (step S).
23) Steps S20 to S until reception is completed
Perform each of the 23 steps. If received, synchronization confirmation data is sent (step S24). Next, a communication enable signal is sent to the voice codec 2 (step S25), and the process then proceeds to a communication processing routine (step S26).

In step S21, when the synchronization failure notification shown in FIG. 11 is received, or in step S22
For example, when data including an error as shown in FIG. 10 is received, the process returns to the synchronization establishment sequence process (step S27). If a timeout has occurred in step S20, a call disconnection process is performed (step S28).

Next, the synchronization establishment sequence processing and the synchronization confirmation sequence processing executed by the terminal adapter 6 on the receiving side will be described with reference to flowcharts shown in FIGS.

In the terminating-side synchronization establishment sequence processing shown in FIGS. 6 and 7, after the termination connection is completed, the terminal adapter 6 starts an overall timer for monitoring the completion of the synchronization sequence (step S29), and uses the B1 channel or the B2 channel. It waits for reception of synchronization pattern 1 (step S30 or step S31). Step S
In step 30, when the synchronization pattern 1 is received on the B1 channel, the synchronization pattern 1 is transmitted to the B1 channel (step S32), and it is determined whether the synchronization pattern 1 is received on the B2 channel (step S33). In this case, the synchronization pattern 1 is transmitted to the B2 channel (step S34). On the other hand, when the synchronization pattern 1 is received on the B2 channel in step S31, the synchronization pattern 1 is transmitted to the B2 channel (step S35), and it is determined whether the synchronization pattern 1 is received on the B1 channel (step S36). If it has been received, the synchronization pattern 1 is transmitted to the B1 channel (step S37).

Thereafter, it is determined whether or not the synchronization pattern 2 has been received on the B1 channel (step S38). If it has been received, it is determined whether or not the synchronization pattern 2 has been received on the B2 channel (step S39). Sends the synchronization pattern 2 to the B1 channel and the B2 channel (step S40). Thereafter, the partner reception guarantee timer is started (step S41). When it is determined that the reception guarantee timer has timed out (step S42), the synchronization pattern 3 is transmitted to the B1 channel and the B2 channel (step S43). This partner reception guarantee timer is
This is a timer set to the time until the synchronization pattern 2 transmitted from the receiving side is securely received by the transmitting side. afterwards,
It is determined whether or not the synchronization pattern 3 has been received on the B1 channel and the B2 channel (step S44), and the process proceeds to a receiving-side synchronization confirmation sequence process (step S45).

Steps S46 to S5
In step 1, when a timeout of the reception waiting timer occurs, the process proceeds to a call disconnection process (step S5).
2).

In the receiving side synchronization confirmation sequence processing shown in FIG. 8, the terminal adapter 6 starts a reception waiting timer (step S53), determines whether or not a timeout has occurred (step S54).
It is determined whether or not the synchronization confirmation data that does not match the predetermined data pattern as shown in (1) is received (step S55). If the mismatching data is not received, the reception of the matching synchronization confirmation data is waited. (Step S56) Steps S54 to S56 are executed until the data is received. Figure 9 if received
Is transmitted (step S57).
Thereafter, the reception waiting timer is started (step S5).
8), it is determined whether or not a timeout has occurred (step S5)
9) If not a timeout, it is determined whether a synchronization failure notification as shown in FIG. 11 has been received (step S6).
0) If no synchronization failure notification has been received, reception of synchronization confirmation data is waited for (step S61), and steps S59 to S61 are executed until reception. If it has been received, a communicable display signal is sent to the voice codec device 7 (step S62), and the process proceeds to a communication processing routine (step S63).

In step S55, when the synchronization confirmation data that does not match is received, a synchronization failure notification is transmitted (step S64), and the process proceeds to a synchronization establishment sequence process (step S65). Also, in step S60, when the synchronization failure notification is received, the process proceeds to the synchronization establishment sequence process (step S66). Step S
If a timeout has occurred in 54 and step 59, the process proceeds to a call disconnection process (steps S67 and S68).

Next, the operation of the terminal adapter will be described with reference to the block diagram shown in FIG. In FIG. 12, the same reference numerals shown in circles indicate the same signal lines.

First, an outgoing / incoming call connection method will be described. The outgoing call is activated from the voice codec device to the control circuit 445 via the signal line 401, and the incoming call is activated from the ISDN interface circuit 403 to the control circuit 445 via the signal line 443.

The control circuit 445 receives the signal via the signal line 443,
Signal line 40 from ISDN interface circuit 403
The transmission / reception connection with the ISDN 13 is performed using the D channel via the 4,422. After the connection is completed, the terminal adapter executes a synchronization establishment sequence process. Control circuit 4
45 is a synchronous pattern sending circuit 402 via a signal line 411
And instruct the logical level of the signal line 442 to be transmitted to the B1 channel and the logical level of the signal line 444 to be transmitted to the B2 channel. On the other hand, the ISDN interface circuit 403 transmits a B1 channel and B2 channel transmission timing signal as shown in FIG. The synchronous pattern sending circuit 402 detects the sending timing signal and changes the logical level of the signal lines 444 and 442 to the signal line 430, the switching circuit 406, and the signal line 40.
7. Send it to the terminal adapter on the other side via ISDN13. That is, in this state, in the switching circuit 406, the signal line 407 is connected to the signal line 430.

When transmitting the synchronization pattern 1 to the B1 channel, the control circuit 445 sets the signal line 444 to the logical level “0” and sets the signal line 442 to the logical level “1”. When transmitting the synchronization pattern 1 to the B2 channel, the signal line 444 is set to the logical level “1” and the signal line 442 is set to the logical level “0”. Subsequently, the synchronization pattern sending circuit 402 sets the data bits of the B1 channel 8 bits and the B2 channel 8 bits shown in FIG.
The signal line 430, the switching circuit 406, the signal line 40
7. Send it to the terminal adapter on the other side via ISDN13. When transmitting the synchronization pattern 2 to the B1 channel and the B2 channel, the signal lines 444 and 442 are both set to the logical level “1”. Subsequently, the synchronization pattern sending circuit 402 sends the B1 channel 8 bits shown in FIG.
The data bits of the 8 bits of the B2 channel are all set to “1” and transmitted to the partner terminal adapter on the same route as the synchronization pattern 1. When transmitting the synchronization pattern 3 to the B1 channel and the B2 channel, the synchronization pattern transmission circuit 402 is activated via the signal line 447. The synchronization pattern sending circuit 402 sets all the data bits of the B1 channel 8 bits and the B2 channel 8 bits shown in FIG. 13 to “0” and sends them to the partner terminal adapter on the same route as the synchronization patterns 1 and 2.

After transmitting the synchronous pattern 3, the synchronous pattern transmitting circuit 402 switches the switching circuit 406 via the signal line 420.
Is given a switching instruction. The switching circuit 406 switches the connection of the signal line 407 from the signal line 430 to the signal line 434 according to the switching instruction.
Switch to That is, the switching circuit 41 is connected to the signal line 407.
3 will be supplied.

Next, a method for detecting the synchronization patterns 1 and 2 will be described. Synchronization patterns 1 and 2 transmitted from the other terminal adapter are ISDN 13, signal line 4
22, a control circuit 445, a B1 channel synchronization pattern 3 detection circuit 414, and a B2 channel synchronization pattern 3 via the ISDN interface circuit 403 and the signal line 408.
The signal is input to the detection circuit 415. The control circuit 445 detects the synchronization patterns 1 and 2 from the signal line 408 based on the transmission timing signal obtained from the signal line 424. The B1 channel synchronization pattern 3 detection circuit 414 and the B2 channel synchronization pattern 3 detection circuit 415 start receiving by a start signal given from the control circuit 445 via the signal line 447, and when the synchronization pattern 3 is received, the signal line 439 and the The data storage input / output control circuit 416 is notified via 440. When the data accumulation input / output control circuit 416 receives the synchronization pattern 3 detection notification from both the B1 channel synchronization pattern 3 detection circuit 414 and the B2 channel synchronization pattern 3 detection circuit 415, the control circuit 4 via the signal line 410.
Notify 45. Thus, the synchronization establishment sequence processing ends.

After the completion of the synchronization establishment sequence processing, the synchronization confirmation data and the audio data in the subsequent communication processing routine are transmitted after being divided into two channel data of the B1 channel and the B2 channel, and are combined into one channel data after reception. Will be done. At the time of transmission from the terminal adapter on the transmitting side, the amount of delay in the ISDN 13 is often different even if the two channel data are in a predetermined order. In that case, a reception delay difference occurs in the terminal adapter on the receiving side, and it becomes impossible to obtain normal combined channel data. Therefore, in the present embodiment, a method of absorbing the reception delay difference between B1 channel data and B2 channel data and establishing data synchronization is used. Hereinafter, this method will be described.

FIG. 14 shows a case where there is no difference in reception delay between the B1 channel data and the B2 channel data. The data storage input / output control circuit 416 determines from the control circuit 445 via the signal line 405 which B channel of the other party, that is, the transmitting terminal adapter, is connected to this side, that is, the receiving terminal adapter. Be instructed. The transmitting terminal adapter transmits the head of the synchronization confirmation data after transmitting the synchronization pattern 3. The data accumulation input / output control circuit 416 receives the detection signal of the synchronization pattern 3 from the B1 channel synchronization pattern 3 detection circuit 414 via the signal line 439, and in the next cycle, outputs the signal from the B2 channel synchronization pattern 3 detection circuit 415. , A detection signal of the synchronization pattern 3 is given via a signal line 440. Therefore, the data storage input / output control circuit 416
Can detect that there is no difference in reception delay between the B1 channel data and the B2 channel data. In this case, without activating the B-channel data storage circuit 412, a signal of the logical level “0” is transmitted via the signal line 428 from the end of the reception of the synchronization pattern 3 of the two channels.
The data storage input / output control circuit 416 supplies the data to the switching circuit 417. As a result, in the switching circuit 417, the output signal line 427 is connected to the input signal line 408. Therefore, the combined channel data D1, D2, D3,... As shown in FIG.

FIG. 15 shows a case where the B2 channel data is received later than the B1 channel data. In this case, the data storage input / output control circuit 416
A detection signal of the synchronization pattern 3 is given from the one-channel synchronization pattern 3 detection circuit 414, and in the next cycle, B2
No detection signal of the synchronization pattern 3 is given from the channel synchronization pattern 3 detection circuit 415. Therefore, the data storage input / output control circuit 416 can detect that the B2 channel data is behind the B1 channel data. Then, by giving the logical level “1” to the B channel data storage circuit 412 via the signal line 418, the data D1, D3,... After receiving the synchronization pattern 3 of the B1 channel are stored. Thereafter, when a detection signal of the synchronization pattern 3 is provided from the B2 channel synchronization pattern 3 detection circuit 415 via the signal line 440, the logic level “1” is provided to the B channel data storage circuit 412 via the signal line 409. , The accumulated B1
The channel data is sequentially output to the signal line 429. The logic level of the signal line 428 is
When the B1 channel data is output from “2”, it becomes “1”, and the output signal line 427 of the switching circuit 417 is connected to the input signal line 429. On the other hand, when the B2 channel data D2, D4,... Are received on the signal line 408, it becomes “0”, and the output signal line 427 of the switching circuit 417 is connected to the input signal line 408. Thus, the switching circuit 417
Outputs the combined channel data D1, D2, D3,... Shown in FIG. 15 to the signal line 427 while switching the connection according to the logic level given via the signal line 428.

FIG. 16 shows a case where the B1 channel data is received later than the B2 channel data. In this case, the data storage input / output control circuit 416
A detection signal of the synchronization pattern 3 is given from the two-channel synchronization pattern 3 detection circuit 415, and in the next cycle, B1
The synchronization pattern 3 detection signal is not supplied from the channel synchronization pattern 3 detection circuit 414. Therefore, the data storage input / output control circuit 416 can detect that the B1 channel data is behind the B2 channel data. Then, the logic level “1” is output via the signal line 418.
Is given to the B-channel data storage circuit 412, so that the data D after receiving the synchronization pattern 3 of the B2 channel
2, D4,... Are accumulated. Thereafter, when a detection signal of the synchronization pattern 3 is given from the B1 channel synchronization pattern 3 detection circuit 414 via the signal line 439, the signal line 41
The data is accumulated by giving a logic level “1” to the B-channel data accumulation circuit 412 via the line 8. Signal line 4
The logic level of the B channel data storage circuit 412
Becomes "1" when the B2 channel data is output from, and the output signal line 427 of the switching circuit 417 is connected to the input signal line 429. On the other hand, when the B1 channel data D1, D3,... Are received on the signal line 408, it becomes “0”, and the output signal line 427 of the switching circuit 417 is connected to the input signal line 408. Thus, the switching circuit 417
Outputs the combined channel data D1, D2, D3,... Shown in FIG. 16 to the signal line 427 while switching the connection according to the logic level given via the signal line 428.

Next, the operation of the synchronization confirmation sequence will be described. The control circuit 445 includes the data storage input / output circuit 4
16 recognizes the detection of the synchronization pattern 3 via the signal line 410, and sends the signal to the synchronization confirmation data transmission circuit 423 to the signal line 43.
8, the synchronization confirmation data shown in FIG. 9 or the synchronization failure notification shown in FIG. 11 is output. The synchronization confirmation data transmission circuit 423 includes a signal line 433, a switching circuit 413, and a signal line 43.
4, switching circuit 406, signal line 407, ISDN interface circuit 403 and signal line 404,
After passing through N13, synchronization confirmation data or synchronization failure notification is sent to the partner terminal adapter. The synchronization confirmation data and the synchronization failure notification from the partner terminal adapter are synchronized in the B channel data storage circuit 412 via the signal line 422, the ISDN interface circuit 403, and the signal line 408. The synchronized reception data is supplied to the switching circuit 417, the signal line 427, the switching circuit 43.
1 and the synchronization confirmation data receiving circuit 4 via the signal line 436.
32 and a control circuit 445 via a signal line 446.
Sent to The control circuit 445 identifies the synchronization confirmation data, the synchronization confirmation data mismatch or the synchronization failure notification based on the received data.

After the completion of the synchronization confirmation sequence, the control circuit 44
Reference numeral 5 denotes a switching signal for connecting the signal line 434 and the signal line 421 in the switching circuit 413 and a switching signal for connecting the signal line 427 and the signal line 437 in the switching circuit 431 via a signal line 419. Also, a signal indicating that communication is possible is transmitted to the voice codec device 425. As a result, the audio data output from the audio codec device 425 is
1, switching circuit 413, signal line 434, switching circuit 406,
Signal line 407, ISDN interface circuit 403,
The signal is transmitted to the partner terminal adapter via the signal line 404 and the ISDN 13. The audio data transmitted from the terminal adapter on the other end is connected to the signal line 422, I
SDN interface circuit 403, signal line 408, B
Channel data storage circuit 412, signal line 429, switching circuit 417, signal line 427, switching circuit 431, and signal line 4
37, it is supplied to the voice codec device 425. As described above, by using both the B1 channel and the B2 channel and realizing synchronization of the two channel data by the optimal algorithm, the transmission speed of each channel is substantially 64 kbps. With a transmission rate of 128 kbps, twice that of
Communication between voice codec devices becomes possible.

Next, an embodiment of a method for confirming (testing) whether the synchronization between the B1 channel and the B2 channel is ensured will be described.

FIG. 17 is a diagram showing another configuration of a system for simultaneously using the B1 channel and the B2 channel as a transmission / reception path of the ISDN basic interface and dividing and transferring data at a communication speed of 128 Kbps. FIG. 17 is different from FIG. 1 in that a data communication terminal 14 which is an ISDN terminal device is connected to one terminal adapter 3 and data communication is similarly performed to the other terminal adapter. Terminal 15 is connected. And, by this configuration, 1
Data communication is performed at a communication speed of 28 Kbps (64 Kbps + 64 Kbps).

Next, the communication operation of the second embodiment having the configuration shown in FIG. 17 will be described, for example, with the terminal 201 as the transmitting side and the terminal 202 as the receiving side.

FIG. 17 shows a synchronization sequence which is a call connection procedure of the second embodiment after the call setup. The synchronization sequence includes two sequences, a synchronization establishment sequence and a synchronization confirmation sequence. First, a synchronization sequence executed by the terminal adapter 3 on the transmitting side will be described. Note that the synchronization establishment sequence is the same as the flowcharts shown in FIGS. 3 and 4 and has been described above, and thus description thereof will be omitted.

FIG. 18 is a flowchart showing the synchronization confirmation sequence processing of the originating terminal adapter 3 according to the synchronization sequence shown in FIG. Hereinafter, the calling-side synchronization confirmation sequence processing of the terminal adapter 3 will be described with reference to FIG.

In the originating-side synchronization confirmation sequence processing shown in FIG. 18, the terminal adapter 3 sends out 8-byte synchronization confirmation data as shown in FIG. 9 (step S10).
1), start a reception waiting timer (step S10)
2). Next, it is monitored whether or not a timeout has occurred (step S103), and if not, it is determined whether or not a synchronization failure notification in which all eight bytes are "55" as shown in FIG. 11 has been received (step S104). If the synchronization failure notification has not been received, it is determined whether or not data that does not match the synchronization confirmation data transmitted in step S101 has been received (step S105). If no unmatched data has been received, it waits for reception of matched synchronization confirmation data (step S106), and waits until step S106 is received.
Steps 103 to S106 are executed. If received, it is determined whether or not to perform failure detection (step S107). If failure detection is not performed, synchronization confirmation data is sent (step S108). Next, a communication enable display signal is transmitted to the data communication terminal (step S109), and thereafter, the process proceeds to a communication processing routine (step S110).

On the other hand, if it is determined in step S107 that failure detection is to be performed, synchronization confirmation data and a loop creation command are transmitted (step S111), and steps S103 to S107 and step S111 are performed until a loop request confirmation signal is received. And step S1
Step 12 is executed. If received, the data communication terminal 14
(Step S113), and then proceeds to a test processing routine (step S11).
4).

In step S104, when the synchronization failure notification shown in FIG. 11 is received, or in step S1
For example, when data including an error as shown in FIG. 10 is received in 05, the process returns to the synchronization establishment sequence process (step S116). Step S10
If a timeout occurs in step 3, call disconnection processing is performed (step S115).

Next, a synchronization sequence executed by the terminal adapter 6 on the receiving side will be described. Note that the synchronization establishment sequence is the same as the flowcharts shown in FIGS. 6 and 7 and has been described above, and thus description thereof will be omitted.

FIG. 19 is a flowchart showing the synchronization confirmation sequence processing of the terminating terminal adapter 6 according to the synchronization sequence shown in FIG. Hereinafter, the receiving side synchronization confirmation sequence processing of the terminal adapter 6 will be described with reference to FIG.

In the receiving-side synchronization confirmation sequence processing shown in FIG. 19, the terminal adapter 6 starts a reception waiting timer (step S120), determines whether or not a timeout has occurred (step S121). It is determined whether or not synchronization confirmation data that does not match a predetermined data pattern is received (step S122). If no synchronization confirmation data has been received, reception of the matching synchronization confirmation data is waited for (step S123). ), Until it is received, step S121
To execute each step of step S123. If received, the synchronization confirmation data shown in FIG. 9 is transmitted (step S124). Thereafter, a reception waiting timer is started (step S125), and it is determined whether or not a timeout has occurred (step S126).
It is determined whether or not a synchronization failure notification as shown in FIG. 1 has been received (step S127). If no synchronization failure notification has been received, reception of synchronization confirmation data is waited for (step S1).
28), execute each step of step S126 to step S128 until receiving. If received, it is determined whether a loop creation command has been received. If not received, a communication enable signal is sent to the data communication terminal (step S130), and the process proceeds to the communication processing routine (step S131). On the other hand, when the loop creation command is received in step S129, a loop request confirmation signal is sent to the transmitting side (step S132), and the receiving side line and the transmitting side line are connected to form a data return loop (step S133). .

If it is determined in step S122 that the synchronization confirmation data does not match, a synchronization failure notification is sent (step S135), and the process proceeds to a synchronization establishment sequence process (step S136). Also, in step S127, when the synchronization failure notification is received, the process proceeds to the synchronization establishment sequence process (step S138). If a timeout has occurred in steps S121 and 126, the process proceeds to the call disconnection process (steps S134 and S137).

Next, the operation of the terminal adapter according to the second embodiment will be described with reference to the block diagram shown in FIG. In FIG. 21, the same reference numerals as those shown in FIG. 12 indicate blocks and signal lines having the same functions. In addition, the operation of the synchronization establishment sequence is the same as that described with reference to FIG.

The operation of the terminal adapter synchronization confirmation sequence will be described below. The control circuit 445 recognizes the detection of the synchronization pattern 3 from the data storage input / output circuit 416 via the signal line 410, and outputs synchronization confirmation data or synchronization confirmation data and a loop creation command transmission circuit 423.
'Via the signal line 438, outputs the synchronization confirmation data shown in FIG. 9, the synchronization failure notification shown in FIG. 11, or the loop creation command shown in FIG. Synchronization confirmation data or synchronization confirmation data and loop creation command sending circuit 423 '
The signal line 433, the switching circuit 413, the signal line 434, the switching circuit 406, the signal line 407, the ISDN interface circuit 403, and the signal line 404
After that, the synchronization confirmation data or the synchronization failure notification or the loop creation command is sent to the other terminal adapter.

Synchronization confirmation data, synchronization failure notification, or loop request confirmation signal from the partner terminal adapter is transmitted to the B channel data storage circuit 412 via the signal line 422, the ISDN interface circuit 403, and the signal line 408. Done. The synchronized reception data is supplied to the switching circuit 417, the signal line 427, the switching circuit 43.
1 and the synchronization confirmation data or the synchronization confirmation data and the loop creation command receiving circuit 432 ′ via the signal line 436, and are transmitted to the control circuit 445 via the signal line 446. The control circuit 445 identifies the synchronization confirmation data or the loop creation command, the synchronization confirmation data mismatch or the synchronization failure notification based on the received data. When a loop creation command is received, the control circuit 445 sets a signal line 503
The control circuit 501 controls the switching circuit 501 through the control circuit 500 so that all data on the signal line 437 is turned back to the signal line 500.

When the loop creation command is not received, after the completion of the synchronization confirmation sequence, the control circuit 445 transmits the signal line 4 in the switching circuit 413 via the signal line 419.
34 and the signal line 421, and the switching circuit 431 gives a switching signal for connecting the signal line 427 and the signal line 437. Also, a signal indicating that communication is possible is transmitted to the voice codec device 425. As a result, the audio data output from the audio codec device 425 includes the signal line 421,
The signal is transmitted to the partner terminal adapter via the switching circuit 413, the signal line 434, the switching circuit 406, the signal line 407, the ISDN interface circuit 403, the signal line 404, and the ISDN 13. The audio data transmitted from the partner terminal adapter is transmitted through the signal line 422 and the ISD
N interface circuit 403, signal line 408, B channel data storage circuit 412, signal line 429, switching circuit 4
17, signal line 427, switching circuit 431, and signal line 437
Is supplied to the data communication terminal 425 'via the.

In the second embodiment, only the procedure for transmitting test data and testing after forming the loop of the terminal adapter on the receiving side is disclosed. However, the communication state is automatically set after the test is completed. can do. It is obvious that this can be easily performed by inserting the synchronization confirmation sequence shown in FIG. 17 between the transmission / reception procedure of the synchronization confirmation data and the image data transmission / reception procedure of the sequence shown in FIG. Therefore, it is possible to include a procedure for checking whether the synchronization between the B1 channel and the B2 channel is ensured during the call setting sequence.

If the synchronization is not normally established in this check, the call setting is automatically performed again, so that a 128 Kbps communication path can be provided more efficiently and accurately.

Further, the transmission of the loop creation command for instructing the receiving side to form a loop and the subsequent test procedure are as follows:
It is not limited to performing at the time of call setup. That is, after the communication path is set, when the data communication terminal is operated (predetermined operation), control is performed so that the loop creation command is transmitted and the subsequent test procedure is executed. ISDN failures can be detected.

In the second embodiment, the failure is detected on the transmitting side, but it is also possible to detect the failure on the receiving side. In this case, a test request signal may be transmitted from the called side to the calling side, and processing conforming to the procedures in FIGS. 18 and 19 may be performed, or synchronization confirmation data and a loop creation command may be sent from the called side. .

Next, using a plurality of ISDN lines,
A third embodiment of a system for performing data communication at a communication speed exceeding 8 Kbps will be described.

FIG. 22 shows, for example, voice information at a communication speed of 384 Kbps using three ISDN basic interfaces and using the B1 and B2 channels of each line, that is, using six B channels simultaneously. FIG. 2 is a system configuration diagram in the case of communicating with. In FIG.
The connection of the terminal adapter, the audio codec device, the amplifier, the microphone, the speaker, and the broadcasting equipment is the same as that of FIG. 1 except for the input lines 16 and 1 to the ISDN.
7, 20, 21 and output lines 14, 15, 18, 19 are increasing.

FIG. 23 is a diagram showing a synchronization sequence when three ISDN basic interfaces are used. In FIG. 23, this synchronization sequence is performed for line 2, line 3
It is shown that the transmission and reception of the synchronization pattern should be performed for each of the B1 and B2 channels in the same manner as in FIG. 17, and therefore detailed description of the operation is omitted. In this figure, the synchronization sequence of synchronization pattern 2 is synchronization pattern 1
And the description of transmission and reception for each channel is also omitted. Also, the transmission side line 1 is not necessarily connected to the reception side line 1, but in this case, by transmitting the synchronization pattern 1 sequentially from the B1 channel of the line 1, the information from the call connection procedure is not used. In each case, it is possible to confirm which B channel of which line on the transmitting side is connected to which B channel of which line on the receiving side.

Further, by immediately transmitting the response pattern after receiving the synchronization pattern, the transmitting side of the synchronization pattern can transmit the response pattern from the transmission of the pattern to the reception of the response pattern. By measuring the time, the delay in the network of the B channel can be easily recognized.

The network delay time may cause a problem depending on the communication purpose. That is, when used as a video conference system according to the method of this embodiment, conversation between people is required. The delay time in the network during conversation is 50m
If it is about S, you will not feel strange, but this is 20
At about 0 ms, the conversation cannot be smoothly performed. Therefore, when the intra-network delay time exceeds a predetermined value, the call is automatically disconnected once, call setting is performed again, and the setting is repeated until the intra-network delay time becomes equal to or less than the predetermined value. Thus, by eliminating the delay time in the network, a smooth conversation becomes possible. This is especially effective for international calls. The reason is that it takes about 320 m
This is because a loss time of S occurs.

Next, the operation of the terminal adapter when using three lines will be described with reference to the block diagram shown in FIG. Note that the same reference numerals shown in circles in FIG. 24 indicate the same signal lines.

First, a call connection method for making and receiving calls will be described. The outgoing call is activated from the voice codec device to the control circuit 445 via the signal line 401, and the incoming call is sent from the ISDN interface circuits 403, 500, 530 to the signal line 4.
The control circuit 445 is activated via 43.

The control circuit 445 receives the signal via the signal line 443,
The signal line 404 from the ISDN interface circuit 403,
Via the 422, 502, 504, 532, and 534, an outgoing / incoming connection is made with the ISDN 13 using the D channel. After the termination of the call connection, the terminal adapter executes a synchronization establishment sequence process. The control circuit 445 controls the signal line 41
Synchronization pattern sending circuit 40 via 1, 520, 550
2,517,547 are activated and signal lines 442,518,
548 logic level to the B1 channel, signal line 444,
It instructs to transmit the logic levels 519 and 549 to the B2 channel. On the other hand, the ISDN interface circuit 40
From 3,500,530, signal lines 424,503,5
33, a B1 channel as shown in FIG.
A channel transmission timing signal is transmitted. The synchronous pattern sending circuits 402, 517, 547 detect this sending timing signal and output the signal lines 444, 442, 518, 5
The logic levels of 19, 548, 549 are changed to signal lines 430, 5
10, 540, the switching circuits 406, 509, 539, the signal lines 407, 521, 551, and the ISDN 13 to send to the partner terminal adapter. That is, in this state, in the switching circuits 406, 509, 539, the signal lines 407, 521, 551 are connected to the signal lines 430, 510, 54.
Connected to 0.

When transmitting the synchronization pattern 1 from the ISDN interface circuit 403 to the B1 channel, the control circuit 445 sets the signal line 444 to the logical level “0”,
The signal line 442 is set to the logic level “1”. When transmitting the synchronization pattern 1 to the B2 channel, the signal line 4
44 is set to the logic level “1”, and the signal line 442 is set to the logic level “0”. Subsequently, the synchronization pattern sending circuit 402
Indicates that all the data bits of the B1 channel 8 bits and the B2 channel 8 bits shown in FIG.
30, the switching circuit 406, the signal line 407, and the ISDN 13 to send the signal to the terminal adapter on the partner side. When transmitting the synchronization pattern 2 to the B1 channel and the B2 channel, both of the signal lines 444 and 442 are set to the logical level “1”. Subsequently, the synchronization pattern sending circuit 402
Makes all the data bits of the B1 channel 8 bits and the B2 channel 8 bits shown in FIG. 13 "1" and sends them to the partner terminal adapter on the same route as the synchronization pattern 1. When transmitting the synchronization patterns 1 and 2 to the ISDN interface circuits 500 and 530, the signal lines corresponding to the respective signal lines and the like may be controlled in the same manner as described above. ISDN interface circuits 403, 500,
When the synchronization pattern 3 is transmitted to the B1 channel and the B2 channel 530, the synchronization pattern 3 transmission circuit 486 is activated via the signal line 447. At this time, the switching circuits 406, 509, and 539 transmit the signals of the respective signal lines 492 to the signal lines 407, the signals of the signal lines 496 to the signal lines 521, via the signal lines 422 from the control circuit 445.
The signal of the signal line 497 is supplied to the signal line 551.

FIGS. 25 and 26 show signal waveforms in FIG. 24 when data is transmitted. FIG.
In (a), (d) and (f), I
SDN interface circuits 403, 500 and 53
These are switching timing signals for the B1 and B2 channels output from the signal lines 424, 503, and 533 of 0.
(B) is a signal waveform of the synchronization pattern 3 transmitted from the signal line 485. (C), (e) and (g) show the signal lines 492 and 49 of the transmission B channel data division circuit 498.
6 shows signal waveforms output from Nos. 6 and 497. Also,
26, (a) shows the signal waveform of the signal line 424, (b) shows the signal waveform of the signal line 434, and (c) to (h) show the time slot signal for each B channel of the signal line 428 (a to f). Is shown. (I) to (k) show the signal lines 492, 496 and 49 of the transmission B channel data division circuit 498.
7 shows the signal waveform of the data output from FIG.

The synchronous pattern 3 transmission circuit 486 outputs 48 data bits “0” of 8 bits to the signal line 485 for one cycle of the signal line 424, that is, for 6 B channels. The switching circuit 413 connects the signal line 485 to the signal line 434 by the signal lines 447 and 487 from the control circuit 445. Transmission B channel data dividing circuit 49
8 divides the data for the B1 and B2 channels for each line by the time slot signal for each B channel on the signal line 428 (A to F) shown in FIG. By multiplying by three (in this embodiment, six B channels are transmitted to each line for every two B channels, so from 384 Kbps to three 128 Kbps)
), And the signal lines 492 and 492 respectively.
14, as shown in FIG. 14, all the data bits of the B1 channel 8 bits and the B2 channel 8 bits shown in FIG. 13 are set to “0”, and the respective switching circuits 406, 509,
From 539, each ISDN interface circuit 403, 50
The data is transmitted to the partner terminal adapter through the route of 0,530. Note that the number of B channels used is 1, 2, 3,.
In the case of n, the number of time slots may be allocated and divided in one cycle of the timing signal line 424 as shown in FIG.

The timing clock for data transmission / reception output to the image codec device is 64 Kbps × n more than that output from the ISDN interface circuit.
(However, n is a natural number)
Timing signal 4 output from N interface circuit
The signal is generated by an analog PLL circuit 499 based on H.24 and is output to a voice codec device via a signal line 484.

Next, a method of detecting the synchronization patterns 1 and 2 will be described. The synchronization patterns 1 and 2 of each B1 channel transmitted from the partner terminal adapter are ISD
N13, signal lines 422, 502, 532, ISDN
The control circuit 455, B1 via the interface circuits 403, 500, 530 and the signal lines 408, 501, 531
Channel synchronization pattern 3 detection circuit 414, 505, 53
5 and B2 channel synchronization pattern 3 detection circuits 415, 5
06,536. The control circuit 445 detects the synchronization patterns 1 and 2 from the signal lines 408, 501 and 531 based on the transmission timing signals obtained from the signal lines 424, 503 and 533. The B1 channel synchronization pattern detection circuits 414, 505, 535 and the B2 channel synchronization pattern 3 detection circuits 415, 506, 536 are connected to the signal line 4
When reception is started by a start signal given from the control circuit 445 via the control circuit 47 and the synchronization pattern 3 is received, the signal lines 439, 507, 537 and 440, 508, 538 are received.
Data input / output control circuits 416, 516, 5
Notify 46. Data storage input / output control circuit 416,5
When receiving the synchronization pattern 3 detection notification from both of the B1 channel synchronization pattern 3 detection circuits 415, 506, and 536, the control circuit 445 notifies the control circuit 445 via the signal lines 410, 524, and 554. Thus, the synchronization establishment sequence processing ends.

After the completion of the synchronization establishment sequence processing, the synchronization confirmation data and the audio data in the subsequent communication processing routine are divided into a plurality of (six in this embodiment) channel data of the B1 and B2 channels of each line. The data is then transmitted and combined into one channel data after reception. At the time of transmission from the terminal adapter on the transmitting side, the delay amounts in the ISDN 13 often differ from each other even if the plurality of channel data are in a predetermined order. In that case, a reception delay difference occurs in the terminal adapter on the receiving side, and it becomes impossible to obtain normal combined channel data. Therefore, in the present embodiment, a method is used in which the reception delay difference between each line and the B1 channel and the B2 channel is absorbed to establish data synchronization. Hereinafter, this method will be described.

First, the operation of the synchronization confirmation sequence will be described. The control circuit 445 controls the signal lines 410, 524,
9 via the signal line 438 to the synchronization confirmation data transmission circuit 423.
Or the synchronization failure data shown in FIG. The synchronization confirmation data transmission circuit 423 includes a signal line 433, a switching circuit 413, a signal line 434, a transmission B channel data division circuit 498, signal lines 492, 496, and 4
97, switching circuits 406, 509, 539, signal line 40
7,521,551, ISDN interface circuit 40
3,500,530 and signal lines 404,504,534
After that, after passing through the ISDN 13, synchronization confirmation data or synchronization failure notification is sent to the partner terminal adapter. Synchronization confirmation data from the other terminal adapter,
Alternatively, the synchronization failure notification is transmitted by the signal lines 422, 502, 53
2. ISDN interface circuits 403, 500, 53
0, data is synchronized in the B channel data storage circuits 412, 415, 542 via the signal lines 408, 501, 531. The synchronized received data is input to the synchronization confirmation data receiving circuit 432 via the switching circuit 417, the signal line 427, the switching circuit 431, and the signal line 436, and is transmitted to the control circuit 445 via the signal line 446. The control circuit 445 recognizes the synchronization confirmation data, the synchronization confirmation data mismatch, or the synchronization failure notification based on the received data.

After completion of the synchronization confirmation sequence, the control circuit 44
Reference numeral 5 denotes a switching signal for connecting the signal line 434 and the signal line 421 in the switching circuit 413 and a switching signal for connecting the signal line 427 and the signal line 437 in the switching circuit 431 via a signal line 419. Also, a signal indicating that communication is possible is transmitted to the voice codec device 425. As a result, the audio data output from the audio codec device 425 is
1, switching circuit 413, signal line 434, transmission B channel dividing circuit 498, signal lines 492, 496, 497, switching circuits 406, 509, 539, signal lines 407, 521, 5
51, ISDN interface circuits 403, 500, 5
30, and are sent to the partner terminal adapter via the signal lines 404, 504, 534 and ISDN. Also,
The audio data transmitted from the partner terminal adapter is transmitted through signal lines 422, 502, 532, ISDN interface circuits 403, 500, 530, and signal lines 408, 5
01,531, B channel data storage circuits 412,51
2, 542, signal lines 429, 513, 543, switching circuit 417, signal line 427, switching circuit 431 and signal line 43
7, and is supplied to the audio codec device 425. As described above, by using both the B1 channel and the B2 channel of a plurality of lines and realizing synchronization of a plurality of channel data by an optimal algorithm, the transmission speed of each channel is 64 Kbp.
Communication between the voice codec devices can be performed at a transmission speed substantially n times (where n is a natural number) as compared with s.

Next, the timing for establishing synchronization will be described. FIG. 28 is a timing chart showing a method for establishing synchronization of reception data of a plurality of B channels. At what timing, the synchronization pattern 3 is received, how the data storage input / output circuit is controlled, and FIG. 9 is a diagram specifically explaining whether synchronization is established. In FIG. 28, (a), (c) and (e) are signal waveforms of the signal lines 424, 503 and 533, respectively. (B), (d) and (f) respectively show the signal line 4
It is a waveform of the received signal obtained from 08, 501, and 531. (G), (i), (k), (m), (p) and (r) are signal waveforms indicating the data accumulation timing output from the data accumulation input / output control circuit 416,
(H), (j), (l), (n), (q) and (s)
Is a signal waveform indicating the data read timing output from the data storage input / output control circuit 416. (T) is B
This is a series of data read from the channel data storage circuit 412, and (u) is a signal line 488 of the control circuit 516.
Is a data output enable signal output from.

First, the ISDN interface circuit 403
The case will be described. If you use multiple lines,
It is necessary to detect the synchronization pattern 3 of all the B channels and to change the cycle of a plurality of B channels transmitted next as shown in FIG. 27 (at times other than 128 Kbps). Therefore, it is necessary to (always) accumulate B channel data once. As shown in FIG. 28, as shown in FIG. 28, only the B1 channel following the detection of the synchronization pattern 3 in the B1 channel of the signal line 408 is sent to the B channel data storage circuit 412 via the signal line 418. And the data D1, after the synchronization pattern 3 of the B1 channel,
D7, D13 (according to the use of six B channels in this embodiment, every six data is accumulated).

Similarly, only the next B2 channel in which the synchronization pattern 3 is detected in the B2 channel of the signal line 408 is given a logical level “1” to the B-channel data storage circuit 412 via the signal line 491, Synchronization pattern 3
The subsequent data D2, D8, D14, D20... Are stored.

Thereafter, when the pattern 3 is detected in all the remaining B channels, the signal lines 410, 524, and 554 all have the logical level "1", and the second of the transmission timings of the signal line 424 under these three AND conditions. The data output enable signal of the signal line 488 is output to each of the data accumulation / input / output control circuits 416, 516, and 546 at the rising edge of. Here, the reason why the data output enable signal is output at the second rising edge of the transmission timing of the signal line 424 will be described with reference to FIG. If the output enable signal is output at the timing of the first rising edge, it is necessary to accumulate the B channel data in order to change the cycle.
The timing immediately after receiving the synchronization pattern 3 in all the Bch at 8 is the position of the head of D1 in FIG. 28B, but if data is output therefrom, all the data of D1 is input. Before that, all data of D1 must be output, which is impossible. (D in FIG. 29 (g)
1 and D1 in FIG. 29 (h) overlap, and in FIG. 29 (h), it is necessary to finish outputting data earlier, which is impossible. Therefore, the input enable signal (g) and the output enable signal (h) must have a difference of one cycle of the transmission timing 424 at worst. Therefore, a condition that the data output enable signal is output at the second rising edge is required.

Data storage input / output control circuits 416 and 51
6, 546, this signal and the time slot creation circuit 4
The time slot signals A to F given from FIG.
Signal line 49 of FIG. 28 obtained under the AND condition
0, 409, 522, 515, 552, and 553 at the logical level “1”, the respective B-channel data storage circuits 412, 5
Data is output from 12,542. Switching circuit 417
Indicates that the time slot signal output from the time slot creation circuit causes the data to be transmitted to the signal line 427 only while each B channel data storage circuit is outputting data.
Is transmitted to the synchronized data D1, D2, D. shown in the signal line 427 of FIG. ... can be obtained.

As described above, according to the terminal adapter of this embodiment, a series of data carrying information (voice information) is time-divisionally transmitted as divided data in a predetermined order for each channel of one or more lines. And when receiving,
By rearranging the obtained divided data in the predetermined order, the transmission rate of the series of data can be made equal to the total number of channels of the transmission rate specific to each channel (for example, 64 kbps). Audio data can be transmitted.

Next, the configuration of the audio codec devices 2 and 7 shown in FIGS. 1 and 22 will be described.

FIG. 29 is a block diagram showing the concept of the internal structure of the voice codec devices 2 and 7. In FIG. 29, reference numeral 601 denotes a digital interface circuit for interfacing with the terminal adapter. The digital interface circuit 601 is a signal line 421, 437, 424 or 428, 401, 419 of the terminal adapter.
Is connected to This interface format is C
Since it conforms to the X, 21 interface of the CITT recommendation, detailed description is omitted. An A / D 606 converts an analog audio signal into a digital signal.
An encoder circuit 605 compresses and encodes audio data obtained from the A / D conversion circuit 606 by a predetermined algorithm via a conversion circuit and a signal line 611. The audio signal obtained from the audio signal input terminal is an A / D converter. After being D-converted, it is encoded and input to the digital interface circuit 601.

Reference numeral 602 denotes a decoder circuit for expanding and decoding coded digital audio data obtained from the transmitting terminal via the ISDN and the terminal adapter.
Is a D / A conversion circuit for converting audio data, which is a digital signal obtained from the decoder circuit 602 via the signal line 610, into an analog signal. The audio data obtained from the digital interface circuit 601 is decoded by the decoder circuit. After that, it is D / A converted and output to the audio exit terminal.

A timing circuit 604 generates various control signals (such as clock signals) for operating the decoder circuit 602, the D / A conversion circuit 603, the encoder circuit 605, and the A / D conversion circuit. Various control signals are generated based on a clock signal (signal line) 424 or 484 obtained from a terminal adapter via a signal adapter 601 and a signal line 609.

FIG. 30 is a block diagram showing the configuration of the transmitting side of the voice codec devices 2 and 7. 30. Referring to FIG. 30, the left channel (L channel) portion will be described. 726 is an input terminal for connecting audio equipment, etc., 717 is an amplifier for amplifying an analog audio signal from the input terminal 726, and 713 is an output signal from the amplifier 717. A switch 711 for outputting / cutting off the output is a level control circuit for adjusting the level of the output signal from the switch 713.

Reference numeral 723 denotes a jack for connecting an Ike plug, reference numeral 721 denotes an amplifier for amplifying the analog audio signal from the jack 723, and reference numeral 715 denotes a switch for outputting / cutting off the output signal from the amplifier 721. Switch 7
The output from 15 is connected to the level control circuit 711. Note that the switch 713 is in a connected state when the microphone plug is not inserted into the jack 723, while the switch 715 is connected by the inverter 719 when the microphone plug is not inserted into the jack 723. Is in a disconnected state. Jack 72
When the microphone plug is not inserted into the switch 3, the states of the switches 713 and 715 are reversed.
The level control circuit 711 is configured to receive only one of an analog audio signal from the input terminal 726 and an analog audio signal from the jack 723.

Further, reference numeral 703 denotes an A / D conversion circuit for converting an analog output signal from the level control circuit 711 into a digital signal into a digital signal, and 701 compresses the digital output signal from the A / D conversion circuit 703 by a predetermined algorithm. , An encoder circuit for encoding. Also, 70
Reference numeral 5 denotes a level meter for measuring the level output to the output signal line from the level control circuit 711, and reference numeral 707 denotes an LED for displaying the measurement result of the level meter 705. Although not shown, a plurality of LEDs are provided, and a predetermined number of LEDs are turned on according to the level state.

Next, the right channel (R channel) will be described. The R channel has the same configuration as the L channel. That is, in the R channel portion, 727 is an input terminal, 718 is an amplifier, 714 is a switch, 712 is a level control circuit, 724 is a jack,
22 is an amplifier, 716 is a switch, 720 is an inverter, 704 is an A / D conversion circuit, 702 is an encoder circuit, 706 is a level meter, and 708 is an LED. The configuration and operation are the same as those of the L channel. Detailed description is omitted.

Next, the common parts will be described. 728 is a gain control circuit for controlling the level control circuits 711 and 712, 729 is a switch for instructing the gain control circuit 728 to increase the gain, and 730 is a gain control circuit 728.
, A switch for instructing to lower the gain, an indicator circuit 709 for reading the gain set by the gain control circuit 728, and an LED 710 for displaying the value read by the indicator circuit. In addition, LED7
A plurality of LEDs 10 are provided, and a predetermined number of LEDs are turned on according to the value of the gain.

Reference numeral 604 denotes A / D conversion circuits 703 and 7
And a timing circuit for generating control signals for controlling the encoder circuits 701 and 702, for example, A / D
Sampling signal to conversion circuit, encoder circuit 701
And a signal for controlling the output of the encoder circuit 702. Therefore, the outputs of the encoder circuits 701 and 702 are alternately output, and the audio data of the L channel and the R channel are output to the digital interface circuit 601 as one digital data.

FIG. 31 is a block diagram showing the configuration of the receiving side of the voice codec devices 2 and 7. Referring to FIG. 31, the L channel portion will be described. Reference numeral 751 denotes a decoder circuit for expanding and decoding encoded digital audio data by a predetermined algorithm, and reference numeral 753 converts a digital audio signal from the decoder circuit 751 into an analog audio signal. A D / A conversion circuit, 755 is a level control circuit for adjusting the level of the output signal from the D / A conversion circuit 753, 773 is a switch for outputting / cutting off the output signal from the level control circuit, and 765 is a switch from the switch 773. An amplifier 769 for amplifying the output signal is a terminal for outputting the analog audio signal from the amplifier 765 to audio equipment, broadcasting equipment, and the like.

Further, 777 is a switch for outputting / cutting off the output signal from the level control circuit, and 776 is a switch 7
An amplifier for amplifying an output signal from the amplifier 77 is a jack for outputting an analog audio signal from the amplifier 776 to headphones. Note that the switch 773 is in a connected state when a plug is not inserted into the jack 771, and at this time, the switch 777 is in a disconnected state by the inverter 775. Further, when a plug is inserted into the jack 771, the switches 713 and 777 are in the opposite state. As a result, the output destination is the output terminal 769 side or the jack 7
71 side.

Note that the switch 773, the switch 777, and the inverter 775 may be removed, and the output signal from the level control circuit may simply be multi-connected to the amplifiers 765 and 766. Thus, the audio signal can be output to audio equipment, broadcasting equipment, and the like while monitoring the output audio signal with the headphones.

Reference numeral 761 denotes a level control signal circuit 755.
This is a level meter for measuring the level of the output signal from the device, and although not shown, the level status is displayed on a plurality of LEDs.

Next, the R channel portion will be described. The R channel portion has the same configuration as the L channel. That is, in the R channel portion, 752 is a decoder circuit, 754 is a D / A conversion circuit, 756 is a level control circuit, 774 is a switch, 768 is an amplifier, 770
Is an output terminal, 778 is a switch, 767 is an amplifier, 77
Reference numeral 2 denotes a jack, 776 denotes an inverter, and 762 denotes a level meter. The configuration and operation thereof are the same as those of the L channel, and a detailed description thereof will be omitted.

Next, the common part will be described.
8 is a gain control circuit for controlling the level control circuits 755 and 756, 757 is a switch for instructing a gain to the gain control circuit 758, 759 is an indicator circuit for reading the value of the gain set by the gain control circuit 758, 760 Is an LED for displaying the value read by the indicator circuit 759. Note that a plurality of LEDs 760 are provided, and a predetermined number of LEDs 760 corresponding to the value of the gain are provided.
ED is turned on. Reference numeral 764 denotes a gain control circuit for controlling the output levels of the amplifiers 766 and 767, and reference numeral 763 denotes a switch for instructing the gain control circuit 764 of a gain. Note that each of the switch 757 and the switch 763 includes two switches, a switch for increasing the gain and a switch for decreasing the gain.

Further, 604 is a D / A conversion circuit 753,
754 and a timing circuit for generating a control signal for controlling the decoder circuits 751 and 752.
A decoding timing signal to the conversion circuit and a separation signal for separating a series of digital signals from the digital interface circuit 601 into an L channel and an R channel are output to the decoder circuits 751 and 752 in accordance with respective timings. are doing. As a result, each of the decoder circuits 751 and 752 receives the digital data from the digital interface circuit 601 based on the separated signal.

FIG. 32 is a block diagram showing the structure of the timing circuit 604.

In FIG. 32, 609 is a signal line obtained by extracting a clock signal obtained from a terminal adapter via a digital interface circuit, and 807 is a signal line 609
A counter circuit for dividing the clock signal from the input clock into 1/256, for example, a mode setting switch 808 for setting whether stereo mode audio communication or monaural mode audio communication,
09 is a bull-up resistor, 805 is a PLL circuit for matching the phase of an externally generated clock (signal line 609) with the internally generated system clock, and 806 is controlled by the PLL circuit to control the internal reference clock (for example, 24 .576
MHz), 802 is a programmable counter circuit that programmatically divides the reference clock from the clock generation circuit, and 804 is the system clock frequency generated by the programmable counter circuit that matches the external clock frequency of the signal line 609. The frequency of the system clock is arbitrarily divided so that the same
05 is a programmable counter circuit that gives feedback to the clock signal 05. The time 801 measures the time from the rise of the clock signal obtained from the counter circuit to the next rise, halves it, and calculates the reciprocal of the value to obtain an external clock (signal The frequency of the line 609) is determined, the mode setting switch 808 is read, and a one-chip microprocessor (hereinafter, referred to as the following) controls the programmable counter circuit 802 and the programmable counter circuit 804 based on the frequency of the external clock and the state of the mode setting switch 808. 803, A is derived from the system clock generated by the programmable counter circuit 802.
/ D conversion circuits 703, 704, D / A conversion circuit 753,
754, a timing clock generator for generating control signals necessary for the operation of the encoder circuits 701 and 702 and the decoder circuits 751 and 752.

FIG. 33 is a diagram showing a correspondence relationship between a frequency band that can be transmitted by the voice codec device and a clock rate (bearer communication speed) required at that time.

In FIG. 33, for example, when the cro
In the case of 4 kbps (using one B channel), the transmittable frequency band is 7.5 kHz, and the transmission mode at that time is a monaural format. Similarly, if the clock rate is 3
In the case of 84 kHz (using six B channels), the transmittable frequency band is 22 kHz, and the transmission mode at that time is a stereo format.

FIG. 34 is a diagram showing the correspondence between the audio signal transmission specifications and the control signals required at that time.

In FIG. 34, the transmission specification A2 of the audio signal
In contrast, when transmitting with the transmission specification, the clock A2 obtained (necessary to obtain) from the terminal adapter
2, the frequency division ratio A23 of the reference clock, the frequency A24 of the system clock at that time, and the frequency A25 of the required sampling clock are shown.

In this embodiment, an example is described in which the frequency of the system clock input to the encoder circuit and the decoder circuit is required to be 128 times the frequency of the sampling clock.

Therefore, for example, when transmitting a stereo audio signal in a transmission band of 22 kHz, the external clock that needs to be obtained from the terminal adapter is 384 kHz.
(That is, the required bearer communication speed is 384 kHz), and the required sampling clock frequency is 48
kHz, so the frequency of the system clock is
It is necessary to set the frequency to 6,144 (= 48 × 128) kHz obtained by dividing the reference clock (24,576 MHz) by ４.

Taking this into the opposite, the transmission specification of the audio signal is determined by the frequency of the external clock obtained from the terminal adapter and the transmission mode (stereo / monaural), whereby the system clock, sampling clock, etc. can be created. become. Hereinafter, this description will be described with reference to FIG.

FIG. 35 is a control flowchart of the microcomputer 801 shown in FIG.

In FIG. 35, after the microcomputer 801 initializes (S200), it determines whether or not a clock (external clock) is output from the counter 807 (S20).
1). When no clock is output, the programmable counter circuit 802 and the programmable counter circuit 8
04 is set to a predetermined default value (S20).
6).

On the other hand, when the clock is detected, the state of the mode setting switch 808 is read to recognize whether it is a stereo type or a monaural type (S202), and then the frequency of the external clock is counted (S203). Since the counting method has been described above, the description is omitted.

Next, it is determined whether or not the value of the frequency division ratio based on the state of the mode setting switch and the frequency of the external clock is a predetermined value (the default audio transmission format) (S204). For example, S206 is executed, and the processing is repeated from S201 again. On the other hand, if the value is the predetermined value, the voice transmission format is recognized, the programmable counter circuit 802 and the programmable counter circuit 804 are controlled to conform to the voice transmission format, and the frequency division ratio is set (S20).
5) The process is repeated from S201 again.

That is, if the frequency of the external clock from the terminal adapter is 192 kHz and the transmission mode is a stereo transmission mode, the frequency division ratio of the programmable counter circuit 802 is set to ８, and the frequency division ratio of the programmable counter circuit 804 is set. Set the ratio to 1/16.

As described above, the timing circuit 604 creates various control signals based on the mode setting switch 808 and the external clock from the terminal adapter.

Hereinafter, a case where the whole operation in FIG. 1 or FIG. 22 is transmitted from terminal 201 will be described as an example.

By operating the terminal adapter 3 of the terminal 201, a call for setting a call at a desired bearer communication speed is made. Then, a communication path (using one or more B channels) is set between the terminal adapter 3 and the terminal adapter 6 via the ISDN 13. Then, the voice codec devices 2 and 7 are connected to the terminal adapters 3 and 6 respectively.
A / D conversion circuit, D / A conversion circuit, based on an external clock obtained from
The encoder circuit and the decoder circuit are operated at a predetermined speed.

As a result, the amplifier 1 and the broadcasting equipment 8 are connected via the ISDN 13 and are in a state where a high-quality audio signal can be transmitted.

On the other hand, when terminating the communication, one of the terminal adapters is operated to perform a disconnection process to release the communication path between the terminal adapter 3 and the terminal adapter 6.

Note that the above-described voice codec device is L
It has a channel and an R channel, and is configured to enable stereo transmission. However, when performing monaural transmission, it is sufficient to transmit an audio signal using only the L channel portion.
The identical configuration supports both stereo transmission and monaural transmission.

Although the above description has been directed to the transmission of an audio signal, the present invention is not limited to the audio signal. That is, as shown in FIG. 36, if a picture transmission device that outputs an analog signal in the audio band is connected to the audio codec device, a high-quality image signal can be transmitted at a high speed.

Further, in the above embodiment, the ISD
Although the description has been made by taking the N basic interface as an example, the present invention can be applied to a primary group interface and further higher-level interfaces. In this case, the encoder circuit and the decoder circuit of the audio codec device are not particularly required, and the digital signal itself after the A / D conversion may be transmitted.

[0121]

According to the present invention, the voice transmission using the single or a plurality of B-channels according to the specification according to the purpose of use is performed by the IS.
This can be performed using DN.

Therefore, in a radio station that provides various programs such as sports broadcasting and concert broadcasting, audio signals can be relayed using ISDN with specifications according to the contents to be relayed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a communication device according to a first embodiment using ISDN of the present invention.

FIG. 2 is a diagram showing a synchronization sequence of the voice communication method using ISDN of the present invention.

FIG. 3 is a flowchart of an originating-side synchronization establishment sequence process.

FIG. 4 is a flowchart of an originating-side synchronization establishment sequence process.

FIG. 5 is a flowchart of an originating-side synchronization confirmation sequence process.

FIG. 6 is a flowchart of a called-side synchronization establishment sequence process.

FIG. 7 is a flowchart of a called-side synchronization establishment sequence process.

FIG. 8 is a flowchart of a called-side synchronization confirmation sequence process.

FIG. 9 is a pattern diagram of synchronization confirmation data.

FIG. 10 is a pattern diagram of synchronization confirmation mismatch data.

FIG. 11 is a data pattern diagram of a synchronization failure notification.

FIG. 12 is a block diagram of a terminal adapter in FIG. 1;

FIG. 13 is a data timing chart of the B1 channel and the B2 channel.

FIG. 14 is a timing chart of received data having no delay difference.

FIG. 15 is a timing chart of received data having a delay difference.

FIG. 16 is a timing chart of received data having a delay difference.

FIG. 17 is a diagram showing a synchronization sequence of the voice communication method in the second embodiment using the ISDN of the present invention.

FIG. 18 is a flowchart of an originating-side synchronization confirmation sequence process according to the second embodiment.

FIG. 19 is a flowchart of a called-side synchronization confirmation sequence process according to the second embodiment.

FIG. 20 is a pattern diagram of a loop creation command.

FIG. 21 is a configuration diagram of a communication apparatus according to a second embodiment using the ISDN of the present invention.

FIG. 22 is a configuration diagram of a communication device according to a third example of the present invention.

FIG. 23 is a diagram showing a synchronization sequence of the communication method according to the third embodiment using the ISDN of the present invention.

FIG. 24 is a block diagram of the terminal adapter in FIG. 22.

FIG. 25 is a pattern diagram of pattern 3 of synchronization confirmation data.

FIG. 26 is a timing chart of a time slot signal.

FIG. 27 is a timing chart of the B-channel multiplexing method.

FIG. 28 is a timing chart showing a method for establishing reception data synchronization of a plurality of B channels.

FIG. 29 is a configuration diagram of a speech codec device of the present invention.

FIG. 30 is a block diagram showing a configuration of an input side of the audio codec device of the present description.

FIG. 31 is a block diagram showing the configuration of the output side of the audio codec device of the present description.

FIG. 32 is a block diagram showing a timing circuit of the audio codec device of the present invention.

FIG. 33 is a diagram showing transmission speeds and specifications of audio signals that can be transmitted.

FIG. 34 illustrates an operation of the timing circuit.

FIG. 35 is a flowchart showing an operation of the one-chip microprocessor of the timing circuit.

FIG. 36 is a diagram illustrating a configuration of a communication device according to another embodiment of the present invention.

FIG. 37 is a block diagram of a terminal device using a conventional ISDN.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Amplifier 2,7 Voice codec device 3,6 Terminal adapter 8 Broadcasting equipment 9 Antenna 4,5,10,11 Subscriber line 13 ISDN 22 Speaker 23 Microphone

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-7752 (JP, A) JP-A-3-106156 (JP, A) JP-A-2-192254 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04M 1/00 H04M 1/24-1/253 H04M 1/58-1/62 H04M 1/66-1/82 H04M 11/00 303

Claims (2)

(57) [Claims] 1. An analog voice communication system connected to a communication terminal device for communicating digital signals at a desired bearer communication speed using at least one communication channel via an ISDN.
A voice communication device for transmitting a signal via ISDN,
According to the digital communication speed from the communication terminal device
A receiving means for receiving the timing signal;
A / D converter that converts log signals to digital audio signals
And a digital audio signal from the A / D conversion means.
Compression means for compressing the compressed data received from the ISDN.
Expansion means for expanding a digital audio signal,
Converts digital audio signal from stage to analog audio signal
D / A conversion means and sound indicating monaural / stereo
Setting means for setting the signal format, and the receiving means
Read the received timing signal and the setting means
The A / D conversion means, the compression means,
The operation clock of the D / A conversion means and the decompression means is
Timing clock generating means for generating and supplying
A voice communication device using ISDN. 2. A first communication terminal and a second communication terminal for communicating digital signals at a desired bearer communication rate using at least one or more communication channels via an ISDN.
Device and analog audio signal to ISDN
A voice communication device that transmits data via a first communication terminal device.
Timing signal corresponding to the digital communication speed
Indicates first receiving means for receiving and monaural / stereo
First setting means for setting the format of the audio signal;
A / D that converts an analog signal into a digital audio signal
Conversion means, and digital audio signal from the A / D conversion means.
Compression means for compressing the signal and the first reception means.
Read from the received timing signal and the first setting means.
The A / D conversion means and the compression means based on the
First timing clock for generating and supplying the operating clock of the stage
Lock generating means, and the voice communication device on the receiving side includes a second communication terminal device.
Timing signal corresponding to the digital communication speed
A second receiving means for receiving, and a transmitted audio signal format
Second setting means for setting, and compression received from ISDN
And expanding means for expanding di digital audio signal being,
The digital audio signal from the expansion means is converted into an analog audio signal.
D / A conversion means for converting the signal into a signal and the second receiving means.
From the received timing signal and the second setting means
The D / A conversion means and the
Second timing for generating and supplying an operating clock of the expansion means
A clock generating means.
Voice communication device using SDN.